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24#include "ctxgf100.h"
25
26#include <subdev/fb.h>
27#include <subdev/mc.h>
28
29
30
31
32
33static const struct gf100_gr_init
34gf117_grctx_init_ds_0[] = {
35 { 0x405800, 1, 0x04, 0x0f8000bf },
36 { 0x405830, 1, 0x04, 0x02180324 },
37 { 0x405834, 1, 0x04, 0x08000000 },
38 { 0x405838, 1, 0x04, 0x00000000 },
39 { 0x405854, 1, 0x04, 0x00000000 },
40 { 0x405870, 4, 0x04, 0x00000001 },
41 { 0x405a00, 2, 0x04, 0x00000000 },
42 { 0x405a18, 1, 0x04, 0x00000000 },
43 {}
44};
45
46static const struct gf100_gr_init
47gf117_grctx_init_pd_0[] = {
48 { 0x406020, 1, 0x04, 0x000103c1 },
49 { 0x406028, 4, 0x04, 0x00000001 },
50 { 0x4064a8, 1, 0x04, 0x00000000 },
51 { 0x4064ac, 1, 0x04, 0x00003fff },
52 { 0x4064b4, 3, 0x04, 0x00000000 },
53 { 0x4064c0, 1, 0x04, 0x801a0078 },
54 { 0x4064c4, 1, 0x04, 0x00c9ffff },
55 { 0x4064d0, 8, 0x04, 0x00000000 },
56 {}
57};
58
59static const struct gf100_gr_pack
60gf117_grctx_pack_hub[] = {
61 { gf100_grctx_init_main_0 },
62 { gf119_grctx_init_fe_0 },
63 { gf100_grctx_init_pri_0 },
64 { gf100_grctx_init_memfmt_0 },
65 { gf117_grctx_init_ds_0 },
66 { gf117_grctx_init_pd_0 },
67 { gf100_grctx_init_rstr2d_0 },
68 { gf100_grctx_init_scc_0 },
69 { gf119_grctx_init_be_0 },
70 {}
71};
72
73static const struct gf100_gr_init
74gf117_grctx_init_setup_0[] = {
75 { 0x418800, 1, 0x04, 0x7006860a },
76 { 0x418808, 3, 0x04, 0x00000000 },
77 { 0x418828, 1, 0x04, 0x00008442 },
78 { 0x418830, 1, 0x04, 0x10000001 },
79 { 0x4188d8, 1, 0x04, 0x00000008 },
80 { 0x4188e0, 1, 0x04, 0x01000000 },
81 { 0x4188e8, 5, 0x04, 0x00000000 },
82 { 0x4188fc, 1, 0x04, 0x20100018 },
83 {}
84};
85
86static const struct gf100_gr_pack
87gf117_grctx_pack_gpc[] = {
88 { gf100_grctx_init_gpc_unk_0 },
89 { gf119_grctx_init_prop_0 },
90 { gf119_grctx_init_gpc_unk_1 },
91 { gf117_grctx_init_setup_0 },
92 { gf100_grctx_init_zcull_0 },
93 { gf119_grctx_init_crstr_0 },
94 { gf108_grctx_init_gpm_0 },
95 { gf100_grctx_init_gcc_0 },
96 {}
97};
98
99const struct gf100_gr_init
100gf117_grctx_init_pe_0[] = {
101 { 0x419848, 1, 0x04, 0x00000000 },
102 { 0x419864, 1, 0x04, 0x00000129 },
103 { 0x419888, 1, 0x04, 0x00000000 },
104 {}
105};
106
107static const struct gf100_gr_init
108gf117_grctx_init_tex_0[] = {
109 { 0x419a00, 1, 0x04, 0x000001f0 },
110 { 0x419a04, 1, 0x04, 0x00000001 },
111 { 0x419a08, 1, 0x04, 0x00000023 },
112 { 0x419a0c, 1, 0x04, 0x00020000 },
113 { 0x419a10, 1, 0x04, 0x00000000 },
114 { 0x419a14, 1, 0x04, 0x00000200 },
115 { 0x419a1c, 1, 0x04, 0x00008000 },
116 { 0x419a20, 1, 0x04, 0x00000800 },
117 { 0x419ac4, 1, 0x04, 0x0017f440 },
118 {}
119};
120
121static const struct gf100_gr_init
122gf117_grctx_init_mpc_0[] = {
123 { 0x419c00, 1, 0x04, 0x0000000a },
124 { 0x419c04, 1, 0x04, 0x00000006 },
125 { 0x419c08, 1, 0x04, 0x00000002 },
126 { 0x419c20, 1, 0x04, 0x00000000 },
127 { 0x419c24, 1, 0x04, 0x00084210 },
128 { 0x419c28, 1, 0x04, 0x3efbefbe },
129 {}
130};
131
132static const struct gf100_gr_pack
133gf117_grctx_pack_tpc[] = {
134 { gf117_grctx_init_pe_0 },
135 { gf117_grctx_init_tex_0 },
136 { gf117_grctx_init_mpc_0 },
137 { gf104_grctx_init_l1c_0 },
138 { gf119_grctx_init_sm_0 },
139 {}
140};
141
142static const struct gf100_gr_init
143gf117_grctx_init_pes_0[] = {
144 { 0x41be24, 1, 0x04, 0x00000002 },
145 {}
146};
147
148static const struct gf100_gr_init
149gf117_grctx_init_cbm_0[] = {
150 { 0x41bec0, 1, 0x04, 0x12180000 },
151 { 0x41bec4, 1, 0x04, 0x00003fff },
152 { 0x41bee4, 1, 0x04, 0x03240218 },
153 {}
154};
155
156const struct gf100_gr_init
157gf117_grctx_init_wwdx_0[] = {
158 { 0x41bf00, 1, 0x04, 0x0a418820 },
159 { 0x41bf04, 1, 0x04, 0x062080e6 },
160 { 0x41bf08, 1, 0x04, 0x020398a4 },
161 { 0x41bf0c, 1, 0x04, 0x0e629062 },
162 { 0x41bf10, 1, 0x04, 0x0a418820 },
163 { 0x41bf14, 1, 0x04, 0x000000e6 },
164 { 0x41bfd0, 1, 0x04, 0x00900103 },
165 { 0x41bfe0, 1, 0x04, 0x00400001 },
166 { 0x41bfe4, 1, 0x04, 0x00000000 },
167 {}
168};
169
170static const struct gf100_gr_pack
171gf117_grctx_pack_ppc[] = {
172 { gf117_grctx_init_pes_0 },
173 { gf117_grctx_init_cbm_0 },
174 { gf117_grctx_init_wwdx_0 },
175 {}
176};
177
178
179
180
181
182void
183gf117_grctx_generate_attrib(struct gf100_grctx *info)
184{
185 struct gf100_gr *gr = info->gr;
186 const struct gf100_grctx_func *grctx = gr->func->grctx;
187 const u32 alpha = grctx->alpha_nr;
188 const u32 beta = grctx->attrib_nr;
189 const u32 size = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max);
190 const u32 access = NV_MEM_ACCESS_RW;
191 const int s = 12;
192 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access);
193 const int timeslice_mode = 1;
194 const int max_batches = 0xffff;
195 u32 bo = 0;
196 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total;
197 int gpc, ppc;
198
199 mmio_refn(info, 0x418810, 0x80000000, s, b);
200 mmio_refn(info, 0x419848, 0x10000000, s, b);
201 mmio_wr32(info, 0x405830, (beta << 16) | alpha);
202 mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
203
204 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
205 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
206 const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc];
207 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc];
208 const u32 t = timeslice_mode;
209 const u32 o = PPC_UNIT(gpc, ppc, 0);
210 if (!(gr->ppc_mask[gpc] & (1 << ppc)))
211 continue;
212 mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo);
213 mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo);
214 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
215 mmio_wr32(info, o + 0xe4, (a << 16) | ao);
216 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
217 }
218 }
219}
220
221void
222gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
223{
224 struct nvkm_device *device = gr->base.engine.subdev.device;
225 const struct gf100_grctx_func *grctx = gr->func->grctx;
226 int i;
227
228 nvkm_mc_unk260(device->mc, 0);
229
230 gf100_gr_mmio(gr, grctx->hub);
231 gf100_gr_mmio(gr, grctx->gpc);
232 gf100_gr_mmio(gr, grctx->zcull);
233 gf100_gr_mmio(gr, grctx->tpc);
234 gf100_gr_mmio(gr, grctx->ppc);
235
236 nvkm_wr32(device, 0x404154, 0x00000000);
237
238 grctx->bundle(info);
239 grctx->pagepool(info);
240 grctx->attrib(info);
241 grctx->unkn(gr);
242
243 gf100_grctx_generate_tpcid(gr);
244 gf100_grctx_generate_r406028(gr);
245 gf100_grctx_generate_r4060a8(gr);
246 gk104_grctx_generate_r418bb8(gr);
247 gf100_grctx_generate_r406800(gr);
248
249 for (i = 0; i < 8; i++)
250 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
251
252 gf100_gr_icmd(gr, grctx->icmd);
253 nvkm_wr32(device, 0x404154, 0x00000400);
254 gf100_gr_mthd(gr, grctx->mthd);
255 nvkm_mc_unk260(device->mc, 1);
256}
257
258const struct gf100_grctx_func
259gf117_grctx = {
260 .main = gf117_grctx_generate_main,
261 .unkn = gk104_grctx_generate_unkn,
262 .hub = gf117_grctx_pack_hub,
263 .gpc = gf117_grctx_pack_gpc,
264 .zcull = gf100_grctx_pack_zcull,
265 .tpc = gf117_grctx_pack_tpc,
266 .ppc = gf117_grctx_pack_ppc,
267 .icmd = gf119_grctx_pack_icmd,
268 .mthd = gf119_grctx_pack_mthd,
269 .bundle = gf100_grctx_generate_bundle,
270 .bundle_size = 0x1800,
271 .pagepool = gf100_grctx_generate_pagepool,
272 .pagepool_size = 0x8000,
273 .attrib = gf117_grctx_generate_attrib,
274 .attrib_nr_max = 0x324,
275 .attrib_nr = 0x218,
276 .alpha_nr_max = 0x7ff,
277 .alpha_nr = 0x324,
278};
279
