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9#include "drmP.h"
10#include "drm_gem_cma_helper.h"
11
12struct vc4_dev {
13 struct drm_device *dev;
14
15 struct vc4_hdmi *hdmi;
16 struct vc4_hvs *hvs;
17 struct vc4_crtc *crtc[3];
18 struct vc4_v3d *v3d;
19
20 struct drm_fbdev_cma *fbdev;
21
22 struct vc4_hang_state *hang_state;
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27
28 struct vc4_bo_cache {
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32
33 struct list_head *size_list;
34 uint32_t size_list_size;
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39
40 struct list_head time_list;
41 struct work_struct time_work;
42 struct timer_list time_timer;
43 } bo_cache;
44
45 struct vc4_bo_stats {
46 u32 num_allocated;
47 u32 size_allocated;
48 u32 num_cached;
49 u32 size_cached;
50 } bo_stats;
51
52
53 struct mutex bo_lock;
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58 uint64_t emit_seqno;
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63 uint64_t finished_seqno;
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69 struct list_head bin_job_list;
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76 struct list_head render_job_list;
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81 struct list_head job_done_list;
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85 spinlock_t job_lock;
86 wait_queue_head_t job_wait_queue;
87 struct work_struct job_done_work;
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92 struct list_head seqno_cb_list;
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99 struct vc4_bo *overflow_mem;
100 struct work_struct overflow_mem_work;
101
102 int power_refcount;
103
104
105 struct mutex power_lock;
106
107 struct {
108 struct timer_list timer;
109 struct work_struct reset_work;
110 } hangcheck;
111
112 struct semaphore async_modeset;
113};
114
115static inline struct vc4_dev *
116to_vc4_dev(struct drm_device *dev)
117{
118 return (struct vc4_dev *)dev->dev_private;
119}
120
121struct vc4_bo {
122 struct drm_gem_cma_object base;
123
124
125 uint64_t seqno;
126
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129
130 struct list_head unref_head;
131
132
133 unsigned long free_time;
134
135
136 struct list_head size_head;
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140
141 struct vc4_validated_shader_info *validated_shader;
142};
143
144static inline struct vc4_bo *
145to_vc4_bo(struct drm_gem_object *bo)
146{
147 return (struct vc4_bo *)bo;
148}
149
150struct vc4_seqno_cb {
151 struct work_struct work;
152 uint64_t seqno;
153 void (*func)(struct vc4_seqno_cb *cb);
154};
155
156struct vc4_v3d {
157 struct vc4_dev *vc4;
158 struct platform_device *pdev;
159 void __iomem *regs;
160};
161
162struct vc4_hvs {
163 struct platform_device *pdev;
164 void __iomem *regs;
165 u32 __iomem *dlist;
166
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169
170 struct drm_mm dlist_mm;
171
172 struct drm_mm lbm_mm;
173 spinlock_t mm_lock;
174
175 struct drm_mm_node mitchell_netravali_filter;
176};
177
178struct vc4_plane {
179 struct drm_plane base;
180};
181
182static inline struct vc4_plane *
183to_vc4_plane(struct drm_plane *plane)
184{
185 return (struct vc4_plane *)plane;
186}
187
188enum vc4_encoder_type {
189 VC4_ENCODER_TYPE_HDMI,
190 VC4_ENCODER_TYPE_VEC,
191 VC4_ENCODER_TYPE_DSI0,
192 VC4_ENCODER_TYPE_DSI1,
193 VC4_ENCODER_TYPE_SMI,
194 VC4_ENCODER_TYPE_DPI,
195};
196
197struct vc4_encoder {
198 struct drm_encoder base;
199 enum vc4_encoder_type type;
200 u32 clock_select;
201};
202
203static inline struct vc4_encoder *
204to_vc4_encoder(struct drm_encoder *encoder)
205{
206 return container_of(encoder, struct vc4_encoder, base);
207}
208
209#define V3D_READ(offset) readl(vc4->v3d->regs + offset)
210#define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
211#define HVS_READ(offset) readl(vc4->hvs->regs + offset)
212#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
213
214struct vc4_exec_info {
215
216 uint64_t seqno;
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221 uint32_t last_ct0ca, last_ct1ca;
222
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224 struct drm_vc4_submit_cl *args;
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229 struct drm_gem_cma_object **bo;
230 uint32_t bo_count;
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233 struct list_head head;
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238 struct list_head unref_list;
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243 uint32_t bo_index[2];
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248 struct drm_gem_cma_object *exec_bo;
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256 struct vc4_shader_state {
257 uint32_t addr;
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260
261 uint32_t max_index;
262 } *shader_state;
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265 uint32_t shader_state_size;
266
267 uint32_t shader_state_count;
268
269 bool found_tile_binning_mode_config_packet;
270 bool found_start_tile_binning_packet;
271 bool found_increment_semaphore_packet;
272 bool found_flush;
273 uint8_t bin_tiles_x, bin_tiles_y;
274 struct drm_gem_cma_object *tile_bo;
275 uint32_t tile_alloc_offset;
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281 uint32_t ct0ca, ct0ea;
282 uint32_t ct1ca, ct1ea;
283
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285 void *bin_u;
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292 void *shader_rec_u;
293 void *shader_rec_v;
294 uint32_t shader_rec_p;
295 uint32_t shader_rec_size;
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300 void *uniforms_u;
301 void *uniforms_v;
302 uint32_t uniforms_p;
303 uint32_t uniforms_size;
304};
305
306static inline struct vc4_exec_info *
307vc4_first_bin_job(struct vc4_dev *vc4)
308{
309 if (list_empty(&vc4->bin_job_list))
310 return NULL;
311 return list_first_entry(&vc4->bin_job_list, struct vc4_exec_info, head);
312}
313
314static inline struct vc4_exec_info *
315vc4_first_render_job(struct vc4_dev *vc4)
316{
317 if (list_empty(&vc4->render_job_list))
318 return NULL;
319 return list_first_entry(&vc4->render_job_list,
320 struct vc4_exec_info, head);
321}
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337struct vc4_texture_sample_info {
338 bool is_direct;
339 uint32_t p_offset[4];
340};
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352struct vc4_validated_shader_info {
353 uint32_t uniforms_size;
354 uint32_t uniforms_src_size;
355 uint32_t num_texture_samples;
356 struct vc4_texture_sample_info *texture_samples;
357};
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366
367#define _wait_for(COND, MS, W) ({ \
368 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
369 int ret__ = 0; \
370 while (!(COND)) { \
371 if (time_after(jiffies, timeout__)) { \
372 if (!(COND)) \
373 ret__ = -ETIMEDOUT; \
374 break; \
375 } \
376 if (W && drm_can_sleep()) { \
377 msleep(W); \
378 } else { \
379 cpu_relax(); \
380 } \
381 } \
382 ret__; \
383})
384
385#define wait_for(COND, MS) _wait_for(COND, MS, 1)
386
387
388struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
389void vc4_free_object(struct drm_gem_object *gem_obj);
390struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
391 bool from_cache);
392int vc4_dumb_create(struct drm_file *file_priv,
393 struct drm_device *dev,
394 struct drm_mode_create_dumb *args);
395struct dma_buf *vc4_prime_export(struct drm_device *dev,
396 struct drm_gem_object *obj, int flags);
397int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
398 struct drm_file *file_priv);
399int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
400 struct drm_file *file_priv);
401int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
402 struct drm_file *file_priv);
403int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
404 struct drm_file *file_priv);
405int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
406int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
407void *vc4_prime_vmap(struct drm_gem_object *obj);
408void vc4_bo_cache_init(struct drm_device *dev);
409void vc4_bo_cache_destroy(struct drm_device *dev);
410int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
411
412
413extern struct platform_driver vc4_crtc_driver;
414int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id);
415void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id);
416int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
417
418
419int vc4_debugfs_init(struct drm_minor *minor);
420void vc4_debugfs_cleanup(struct drm_minor *minor);
421
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423void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
424
425
426void vc4_gem_init(struct drm_device *dev);
427void vc4_gem_destroy(struct drm_device *dev);
428int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
429 struct drm_file *file_priv);
430int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
431 struct drm_file *file_priv);
432int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
433 struct drm_file *file_priv);
434void vc4_submit_next_bin_job(struct drm_device *dev);
435void vc4_submit_next_render_job(struct drm_device *dev);
436void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
437int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
438 uint64_t timeout_ns, bool interruptible);
439void vc4_job_handle_completed(struct vc4_dev *vc4);
440int vc4_queue_seqno_cb(struct drm_device *dev,
441 struct vc4_seqno_cb *cb, uint64_t seqno,
442 void (*func)(struct vc4_seqno_cb *cb));
443
444
445extern struct platform_driver vc4_hdmi_driver;
446int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
447
448
449irqreturn_t vc4_irq(int irq, void *arg);
450void vc4_irq_preinstall(struct drm_device *dev);
451int vc4_irq_postinstall(struct drm_device *dev);
452void vc4_irq_uninstall(struct drm_device *dev);
453void vc4_irq_reset(struct drm_device *dev);
454
455
456extern struct platform_driver vc4_hvs_driver;
457void vc4_hvs_dump_state(struct drm_device *dev);
458int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
459
460
461int vc4_kms_load(struct drm_device *dev);
462
463
464struct drm_plane *vc4_plane_init(struct drm_device *dev,
465 enum drm_plane_type type);
466u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
467u32 vc4_plane_dlist_size(struct drm_plane_state *state);
468void vc4_plane_async_set_fb(struct drm_plane *plane,
469 struct drm_framebuffer *fb);
470
471
472extern struct platform_driver vc4_v3d_driver;
473int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
474int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
475
476
477int
478vc4_validate_bin_cl(struct drm_device *dev,
479 void *validated,
480 void *unvalidated,
481 struct vc4_exec_info *exec);
482
483int
484vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
485
486struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
487 uint32_t hindex);
488
489int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
490
491bool vc4_check_tex_size(struct vc4_exec_info *exec,
492 struct drm_gem_cma_object *fbo,
493 uint32_t offset, uint8_t tiling_format,
494 uint32_t width, uint32_t height, uint8_t cpp);
495
496
497struct vc4_validated_shader_info *
498vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
499