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19#ifndef BNX2X_CMN_H
20#define BNX2X_CMN_H
21
22#include <linux/types.h>
23#include <linux/pci.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/irq.h>
27
28#include "bnx2x.h"
29#include "bnx2x_sriov.h"
30
31
32extern int bnx2x_load_count[2][3];
33extern int bnx2x_num_queues;
34
35
36#define BNX2X_PCI_FREE(x, y, size) \
37 do { \
38 if (x) { \
39 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
40 x = NULL; \
41 y = 0; \
42 } \
43 } while (0)
44
45#define BNX2X_FREE(x) \
46 do { \
47 if (x) { \
48 kfree((void *)x); \
49 x = NULL; \
50 } \
51 } while (0)
52
53#define BNX2X_PCI_ALLOC(y, size) \
54({ \
55 void *x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
56 if (x) \
57 DP(NETIF_MSG_HW, \
58 "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \
59 (unsigned long long)(*y), x); \
60 x; \
61})
62#define BNX2X_PCI_FALLOC(y, size) \
63({ \
64 void *x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
65 if (x) { \
66 memset(x, 0xff, size); \
67 DP(NETIF_MSG_HW, \
68 "BNX2X_PCI_FALLOC: Physical %Lx Virtual %p\n", \
69 (unsigned long long)(*y), x); \
70 } \
71 x; \
72})
73
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86
87u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
88
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93
94
95void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link);
96
97
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103
104
105
106int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
107 bool config_hash, bool enable);
108
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115
116
117
118void bnx2x__init_func_obj(struct bnx2x *bp);
119
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126
127
128int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
129 bool leading);
130
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134
135
136int bnx2x_setup_leading(struct bnx2x *bp);
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145
146
147u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
148
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153
154
155int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
156
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160
161
162void bnx2x_link_set(struct bnx2x *bp);
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168
169
170void bnx2x_force_link_reset(struct bnx2x *bp);
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179
180u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
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188
189
190void bnx2x_drv_pulse(struct bnx2x *bp);
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200
201
202void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
203 u16 index, u8 op, u8 update);
204
205
206void bnx2x_pf_disable(struct bnx2x *bp);
207int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
208
209
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212
213
214void bnx2x__link_status_update(struct bnx2x *bp);
215
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219
220
221void bnx2x_link_report(struct bnx2x *bp);
222
223
224void __bnx2x_link_report(struct bnx2x *bp);
225
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232
233u16 bnx2x_get_mf_speed(struct bnx2x *bp);
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240
241irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
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249irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
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256
257int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
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262
263
264void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
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269
270
271void bnx2x_setup_cnic_info(struct bnx2x *bp);
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276
277
278void bnx2x_int_enable(struct bnx2x *bp);
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289void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
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302void bnx2x_nic_init_cnic(struct bnx2x *bp);
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312
313
314void bnx2x_pre_irq_nic_init(struct bnx2x *bp);
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327void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code);
328
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331
332
333int bnx2x_alloc_mem_cnic(struct bnx2x *bp);
334
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337
338
339int bnx2x_alloc_mem(struct bnx2x *bp);
340
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344
345
346void bnx2x_free_mem_cnic(struct bnx2x *bp);
347
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351
352void bnx2x_free_mem(struct bnx2x *bp);
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358
359void bnx2x_set_num_queues(struct bnx2x *bp);
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372void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link);
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378
379
380int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
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387
388int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
389
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395int bnx2x_release_leader_lock(struct bnx2x *bp);
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404
405int bnx2x_set_eth_mac(struct bnx2x *bp, bool set);
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415
416void bnx2x_set_rx_mode_inner(struct bnx2x *bp);
417
418
419void bnx2x_set_pf_load(struct bnx2x *bp);
420bool bnx2x_clear_pf_load(struct bnx2x *bp);
421bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
422bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
423void bnx2x_set_reset_in_progress(struct bnx2x *bp);
424void bnx2x_set_reset_global(struct bnx2x *bp);
425void bnx2x_disable_close_the_gate(struct bnx2x *bp);
426int bnx2x_init_hw_func_cnic(struct bnx2x *bp);
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432
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434void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
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441void bnx2x_ilt_set_info(struct bnx2x *bp);
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447
448
449void bnx2x_ilt_set_info_cnic(struct bnx2x *bp);
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455
456void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem);
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465
466int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
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473
474void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
475
476void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
477
478
479int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link);
480
481
482int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
483
484
485netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
486
487
488int bnx2x_setup_tc(struct net_device *dev, u8 num_tc);
489int __bnx2x_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
490 struct tc_to_netdev *tc);
491
492int bnx2x_get_vf_config(struct net_device *dev, int vf,
493 struct ifla_vf_info *ivi);
494int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac);
495int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos);
496
497
498u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb,
499 void *accel_priv, select_queue_fallback_t fallback);
500
501static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
502 struct bnx2x_fastpath *fp,
503 u16 bd_prod, u16 rx_comp_prod,
504 u16 rx_sge_prod)
505{
506 struct ustorm_eth_rx_producers rx_prods = {0};
507 u32 i;
508
509
510 rx_prods.bd_prod = bd_prod;
511 rx_prods.cqe_prod = rx_comp_prod;
512 rx_prods.sge_prod = rx_sge_prod;
513
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515
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517
518
519
520
521 wmb();
522
523 for (i = 0; i < sizeof(rx_prods)/4; i++)
524 REG_WR(bp, fp->ustorm_rx_prods_offset + i*4,
525 ((u32 *)&rx_prods)[i]);
526
527 mmiowb();
528
529 DP(NETIF_MSG_RX_STATUS,
530 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
531 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
532}
533
534
535int bnx2x_reload_if_running(struct net_device *dev);
536
537int bnx2x_change_mac_addr(struct net_device *dev, void *p);
538
539
540int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata);
541
542
543int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
544int bnx2x_resume(struct pci_dev *pdev);
545
546
547void bnx2x_free_irq(struct bnx2x *bp);
548
549void bnx2x_free_fp_mem(struct bnx2x *bp);
550void bnx2x_init_rx_rings(struct bnx2x *bp);
551void bnx2x_init_rx_rings_cnic(struct bnx2x *bp);
552void bnx2x_free_skbs(struct bnx2x *bp);
553void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
554void bnx2x_netif_start(struct bnx2x *bp);
555int bnx2x_load_cnic(struct bnx2x *bp);
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557
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562
563
564
565int bnx2x_enable_msix(struct bnx2x *bp);
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567
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569
570
571
572int bnx2x_enable_msi(struct bnx2x *bp);
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577
578
579int bnx2x_alloc_mem_bp(struct bnx2x *bp);
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584
585
586void bnx2x_free_mem_bp(struct bnx2x *bp);
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595int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
596
597#ifdef NETDEV_FCOE_WWNN
598
599
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602
603
604
605
606int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type);
607#endif
608
609netdev_features_t bnx2x_fix_features(struct net_device *dev,
610 netdev_features_t features);
611int bnx2x_set_features(struct net_device *dev, netdev_features_t features);
612
613
614
615
616
617
618void bnx2x_tx_timeout(struct net_device *dev);
619
620
621
622
623
624
625
626void bnx2x_get_c2s_mapping(struct bnx2x *bp, u8 *c2s_map, u8 *c2s_default);
627
628
629
630static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
631{
632 barrier();
633 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
634}
635
636static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
637 u8 segment, u16 index, u8 op,
638 u8 update, u32 igu_addr)
639{
640 struct igu_regular cmd_data = {0};
641
642 cmd_data.sb_id_and_flags =
643 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
644 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
645 (update << IGU_REGULAR_BUPDATE_SHIFT) |
646 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
647
648 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
649 cmd_data.sb_id_and_flags, igu_addr);
650 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
651
652
653 mmiowb();
654 barrier();
655}
656
657static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
658 u8 storm, u16 index, u8 op, u8 update)
659{
660 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
661 COMMAND_REG_INT_ACK);
662 struct igu_ack_register igu_ack;
663
664 igu_ack.status_block_index = index;
665 igu_ack.sb_id_and_flags =
666 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
667 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
668 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
669 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
670
671 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
672
673
674 mmiowb();
675 barrier();
676}
677
678static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
679 u16 index, u8 op, u8 update)
680{
681 if (bp->common.int_block == INT_BLOCK_HC)
682 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
683 else {
684 u8 segment;
685
686 if (CHIP_INT_MODE_IS_BC(bp))
687 segment = storm;
688 else if (igu_sb_id != bp->igu_dsb_id)
689 segment = IGU_SEG_ACCESS_DEF;
690 else if (storm == ATTENTION_ID)
691 segment = IGU_SEG_ACCESS_ATTN;
692 else
693 segment = IGU_SEG_ACCESS_DEF;
694 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
695 }
696}
697
698static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
699{
700 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
701 COMMAND_REG_SIMD_MASK);
702 u32 result = REG_RD(bp, hc_addr);
703
704 barrier();
705 return result;
706}
707
708static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
709{
710 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
711 u32 result = REG_RD(bp, igu_addr);
712
713 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
714 result, igu_addr);
715
716 barrier();
717 return result;
718}
719
720static inline u16 bnx2x_ack_int(struct bnx2x *bp)
721{
722 barrier();
723 if (bp->common.int_block == INT_BLOCK_HC)
724 return bnx2x_hc_ack_int(bp);
725 else
726 return bnx2x_igu_ack_int(bp);
727}
728
729static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata)
730{
731
732 barrier();
733 return txdata->tx_pkt_prod != txdata->tx_pkt_cons;
734}
735
736static inline u16 bnx2x_tx_avail(struct bnx2x *bp,
737 struct bnx2x_fp_txdata *txdata)
738{
739 s16 used;
740 u16 prod;
741 u16 cons;
742
743 prod = txdata->tx_bd_prod;
744 cons = txdata->tx_bd_cons;
745
746 used = SUB_S16(prod, cons);
747
748#ifdef BNX2X_STOP_ON_ERROR
749 WARN_ON(used < 0);
750 WARN_ON(used > txdata->tx_ring_size);
751 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL);
752#endif
753
754 return (s16)(txdata->tx_ring_size) - used;
755}
756
757static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
758{
759 u16 hw_cons;
760
761
762 barrier();
763 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
764 return hw_cons != txdata->tx_pkt_cons;
765}
766
767static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
768{
769 u8 cos;
770 for_each_cos_in_tx_queue(fp, cos)
771 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
772 return true;
773 return false;
774}
775
776#define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0)
777#define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF)
778static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
779{
780 u16 cons;
781 union eth_rx_cqe *cqe;
782 struct eth_fast_path_rx_cqe *cqe_fp;
783
784 cons = RCQ_BD(fp->rx_comp_cons);
785 cqe = &fp->rx_comp_ring[cons];
786 cqe_fp = &cqe->fast_path_cqe;
787 return BNX2X_IS_CQE_COMPLETED(cqe_fp);
788}
789
790
791
792
793
794
795static inline void bnx2x_tx_disable(struct bnx2x *bp)
796{
797 netif_tx_disable(bp->dev);
798 netif_carrier_off(bp->dev);
799}
800
801static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
802 struct bnx2x_fastpath *fp, u16 index)
803{
804 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
805 struct page *page = sw_buf->page;
806 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
807
808
809 if (!page)
810 return;
811
812
813
814
815 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
816 SGE_PAGE_SIZE, DMA_FROM_DEVICE);
817
818 put_page(page);
819
820 sw_buf->page = NULL;
821 sge->addr_hi = 0;
822 sge->addr_lo = 0;
823}
824
825static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp)
826{
827 int i;
828
829 for_each_rx_queue_cnic(bp, i) {
830 napi_hash_del(&bnx2x_fp(bp, i, napi));
831 netif_napi_del(&bnx2x_fp(bp, i, napi));
832 }
833}
834
835static inline void bnx2x_del_all_napi(struct bnx2x *bp)
836{
837 int i;
838
839 for_each_eth_queue(bp, i) {
840 napi_hash_del(&bnx2x_fp(bp, i, napi));
841 netif_napi_del(&bnx2x_fp(bp, i, napi));
842 }
843}
844
845int bnx2x_set_int_mode(struct bnx2x *bp);
846
847static inline void bnx2x_disable_msi(struct bnx2x *bp)
848{
849 if (bp->flags & USING_MSIX_FLAG) {
850 pci_disable_msix(bp->pdev);
851 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG);
852 } else if (bp->flags & USING_MSI_FLAG) {
853 pci_disable_msi(bp->pdev);
854 bp->flags &= ~USING_MSI_FLAG;
855 }
856}
857
858static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
859{
860 int i, j;
861
862 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
863 int idx = RX_SGE_CNT * i - 1;
864
865 for (j = 0; j < 2; j++) {
866 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
867 idx--;
868 }
869 }
870}
871
872static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
873{
874
875 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
876
877
878
879
880
881 bnx2x_clear_sge_mask_next_elems(fp);
882}
883
884
885
886
887
888
889static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp,
890 u16 cons, u16 prod)
891{
892 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
893 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
894 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
895 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
896
897 dma_unmap_addr_set(prod_rx_buf, mapping,
898 dma_unmap_addr(cons_rx_buf, mapping));
899 prod_rx_buf->data = cons_rx_buf->data;
900 *prod_bd = *cons_bd;
901}
902
903
904
905
906static inline int func_by_vn(struct bnx2x *bp, int vn)
907{
908 return 2 * vn + BP_PORT(bp);
909}
910
911static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash)
912{
913 return bnx2x_rss(bp, &bp->rss_conf_obj, config_hash, true);
914}
915
916
917
918
919
920
921
922
923static inline int bnx2x_func_start(struct bnx2x *bp)
924{
925 struct bnx2x_func_state_params func_params = {NULL};
926 struct bnx2x_func_start_params *start_params =
927 &func_params.params.start;
928 u16 port;
929
930
931 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
932
933 func_params.f_obj = &bp->func_obj;
934 func_params.cmd = BNX2X_F_CMD_START;
935
936
937 start_params->mf_mode = bp->mf_mode;
938 start_params->sd_vlan_tag = bp->mf_ov;
939
940
941 if (IS_MF_BD(bp)) {
942 DP(NETIF_MSG_IFUP, "Configuring ethertype 0x88a8 for BD\n");
943 start_params->sd_vlan_eth_type = ETH_P_8021AD;
944 REG_WR(bp, PRS_REG_VLAN_TYPE_0, ETH_P_8021AD);
945 REG_WR(bp, PBF_REG_VLAN_TYPE_0, ETH_P_8021AD);
946 REG_WR(bp, NIG_REG_LLH_E1HOV_TYPE_1, ETH_P_8021AD);
947
948 bnx2x_get_c2s_mapping(bp, start_params->c2s_pri,
949 &start_params->c2s_pri_default);
950 start_params->c2s_pri_valid = 1;
951
952 DP(NETIF_MSG_IFUP,
953 "Inner-to-Outer priority: %02x %02x %02x %02x %02x %02x %02x %02x [Default %02x]\n",
954 start_params->c2s_pri[0], start_params->c2s_pri[1],
955 start_params->c2s_pri[2], start_params->c2s_pri[3],
956 start_params->c2s_pri[4], start_params->c2s_pri[5],
957 start_params->c2s_pri[6], start_params->c2s_pri[7],
958 start_params->c2s_pri_default);
959 }
960
961 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
962 start_params->network_cos_mode = STATIC_COS;
963 else
964 start_params->network_cos_mode = FW_WRR;
965 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) {
966 port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].dst_port;
967 start_params->vxlan_dst_port = port;
968 }
969 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) {
970 port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].dst_port;
971 start_params->geneve_dst_port = port;
972 }
973
974 start_params->inner_rss = 1;
975
976 if (IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
977 start_params->class_fail_ethtype = ETH_P_FIP;
978 start_params->class_fail = 1;
979 start_params->no_added_tags = 1;
980 }
981
982 return bnx2x_func_state_change(bp, &func_params);
983}
984
985
986
987
988
989
990
991
992
993static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
994 __le16 *fw_lo, u8 *mac)
995{
996 ((u8 *)fw_hi)[0] = mac[1];
997 ((u8 *)fw_hi)[1] = mac[0];
998 ((u8 *)fw_mid)[0] = mac[3];
999 ((u8 *)fw_mid)[1] = mac[2];
1000 ((u8 *)fw_lo)[0] = mac[5];
1001 ((u8 *)fw_lo)[1] = mac[4];
1002}
1003
1004static inline void bnx2x_free_rx_mem_pool(struct bnx2x *bp,
1005 struct bnx2x_alloc_pool *pool)
1006{
1007 if (!pool->page)
1008 return;
1009
1010 put_page(pool->page);
1011
1012 pool->page = NULL;
1013}
1014
1015static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
1016 struct bnx2x_fastpath *fp, int last)
1017{
1018 int i;
1019
1020 if (fp->mode == TPA_MODE_DISABLED)
1021 return;
1022
1023 for (i = 0; i < last; i++)
1024 bnx2x_free_rx_sge(bp, fp, i);
1025
1026 bnx2x_free_rx_mem_pool(bp, &fp->page_pool);
1027}
1028
1029static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
1030{
1031 int i;
1032
1033 for (i = 1; i <= NUM_RX_RINGS; i++) {
1034 struct eth_rx_bd *rx_bd;
1035
1036 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
1037 rx_bd->addr_hi =
1038 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
1039 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1040 rx_bd->addr_lo =
1041 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
1042 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1043 }
1044}
1045
1046
1047
1048
1049static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp)
1050{
1051 struct bnx2x *bp = fp->bp;
1052 if (!CHIP_IS_E1x(bp)) {
1053
1054 if (IS_FCOE_FP(fp))
1055 return bp->cnic_base_cl_id + (bp->pf_num >> 1);
1056 return fp->cl_id;
1057 }
1058 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x;
1059}
1060
1061static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp,
1062 bnx2x_obj_type obj_type)
1063{
1064 struct bnx2x *bp = fp->bp;
1065
1066
1067 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id,
1068 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata),
1069 bnx2x_sp_mapping(bp, mac_rdata),
1070 BNX2X_FILTER_MAC_PENDING,
1071 &bp->sp_state, obj_type,
1072 &bp->macs_pool);
1073
1074 if (!CHIP_IS_E1x(bp))
1075 bnx2x_init_vlan_obj(bp, &bnx2x_sp_obj(bp, fp).vlan_obj,
1076 fp->cl_id, fp->cid, BP_FUNC(bp),
1077 bnx2x_sp(bp, vlan_rdata),
1078 bnx2x_sp_mapping(bp, vlan_rdata),
1079 BNX2X_FILTER_VLAN_PENDING,
1080 &bp->sp_state, obj_type,
1081 &bp->vlans_pool);
1082}
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp)
1093{
1094 u8 func_num = 0, i;
1095
1096
1097 if (CHIP_IS_E1(bp))
1098 return 1;
1099
1100
1101
1102
1103 if (CHIP_REV_IS_SLOW(bp)) {
1104 if (IS_MF(bp))
1105 func_num = 4;
1106 else
1107 func_num = 2;
1108 } else {
1109 for (i = 0; i < E1H_FUNC_MAX / 2; i++) {
1110 u32 func_config =
1111 MF_CFG_RD(bp,
1112 func_mf_config[BP_PORT(bp) + 2 * i].
1113 config);
1114 func_num +=
1115 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1);
1116 }
1117 }
1118
1119 WARN_ON(!func_num);
1120
1121 return func_num;
1122}
1123
1124static inline void bnx2x_init_bp_objs(struct bnx2x *bp)
1125{
1126
1127 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj);
1128
1129
1130 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid,
1131 BP_FUNC(bp), BP_FUNC(bp),
1132 bnx2x_sp(bp, mcast_rdata),
1133 bnx2x_sp_mapping(bp, mcast_rdata),
1134 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state,
1135 BNX2X_OBJ_TYPE_RX);
1136
1137
1138 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp),
1139 bnx2x_get_path_func_num(bp));
1140
1141 bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_FUNC(bp),
1142 bnx2x_get_path_func_num(bp));
1143
1144
1145 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id,
1146 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp),
1147 bnx2x_sp(bp, rss_rdata),
1148 bnx2x_sp_mapping(bp, rss_rdata),
1149 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state,
1150 BNX2X_OBJ_TYPE_RX);
1151
1152 bp->vlan_credit = PF_VLAN_CREDIT_E2(bp, bnx2x_get_path_func_num(bp));
1153}
1154
1155static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
1156{
1157 if (CHIP_IS_E1x(fp->bp))
1158 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
1159 else
1160 return fp->cl_id;
1161}
1162
1163static inline void bnx2x_init_txdata(struct bnx2x *bp,
1164 struct bnx2x_fp_txdata *txdata, u32 cid,
1165 int txq_index, __le16 *tx_cons_sb,
1166 struct bnx2x_fastpath *fp)
1167{
1168 txdata->cid = cid;
1169 txdata->txq_index = txq_index;
1170 txdata->tx_cons_sb = tx_cons_sb;
1171 txdata->parent_fp = fp;
1172 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size;
1173
1174 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n",
1175 txdata->cid, txdata->txq_index);
1176}
1177
1178static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx)
1179{
1180 return bp->cnic_base_cl_id + cl_idx +
1181 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
1182}
1183
1184static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
1185{
1186
1187 return bp->base_fw_ndsb;
1188}
1189
1190static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
1191{
1192 return bp->igu_base_sb;
1193}
1194
1195static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
1196 struct bnx2x_fp_txdata *txdata)
1197{
1198 int cnt = 1000;
1199
1200 while (bnx2x_has_tx_work_unload(txdata)) {
1201 if (!cnt) {
1202 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1203 txdata->txq_index, txdata->tx_pkt_prod,
1204 txdata->tx_pkt_cons);
1205#ifdef BNX2X_STOP_ON_ERROR
1206 bnx2x_panic();
1207 return -EBUSY;
1208#else
1209 break;
1210#endif
1211 }
1212 cnt--;
1213 usleep_range(1000, 2000);
1214 }
1215
1216 return 0;
1217}
1218
1219int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1220
1221static inline void __storm_memset_struct(struct bnx2x *bp,
1222 u32 addr, size_t size, u32 *data)
1223{
1224 int i;
1225 for (i = 0; i < size/4; i++)
1226 REG_WR(bp, addr + (i * 4), data[i]);
1227}
1228
1229
1230
1231
1232
1233
1234
1235static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
1236{
1237 int tout = 5000;
1238
1239 while (tout--) {
1240 smp_mb();
1241 netif_addr_lock_bh(bp->dev);
1242 if (!(bp->sp_state & mask)) {
1243 netif_addr_unlock_bh(bp->dev);
1244 return true;
1245 }
1246 netif_addr_unlock_bh(bp->dev);
1247
1248 usleep_range(1000, 2000);
1249 }
1250
1251 smp_mb();
1252
1253 netif_addr_lock_bh(bp->dev);
1254 if (bp->sp_state & mask) {
1255 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n",
1256 bp->sp_state, mask);
1257 netif_addr_unlock_bh(bp->dev);
1258 return false;
1259 }
1260 netif_addr_unlock_bh(bp->dev);
1261
1262 return true;
1263}
1264
1265
1266
1267
1268
1269
1270
1271
1272void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
1273 u32 cid);
1274
1275void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
1276 u8 sb_index, u8 disable, u16 usec);
1277void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1278void bnx2x_release_phy_lock(struct bnx2x *bp);
1279
1280
1281
1282
1283
1284
1285
1286
1287static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
1288{
1289 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1290 FUNC_MF_CFG_MAX_BW_SHIFT;
1291 if (!max_cfg) {
1292 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
1293 "Max BW configured to 0 - using 100 instead\n");
1294 max_cfg = 100;
1295 }
1296 return max_cfg;
1297}
1298
1299
1300static inline bool bnx2x_mtu_allows_gro(int mtu)
1301{
1302
1303 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE);
1304
1305
1306
1307
1308
1309 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS;
1310}
1311
1312
1313
1314
1315
1316
1317
1318void bnx2x_get_iscsi_info(struct bnx2x *bp);
1319
1320
1321
1322
1323
1324
1325
1326static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
1327{
1328 int func;
1329 int vn;
1330
1331
1332 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
1333 if (vn == BP_VN(bp))
1334 continue;
1335
1336 func = func_by_vn(bp, vn);
1337 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
1338 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
1339 }
1340}
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set)
1351{
1352 if (SHMEM2_HAS(bp, drv_flags)) {
1353 u32 drv_flags;
1354 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1355 drv_flags = SHMEM2_RD(bp, drv_flags);
1356
1357 if (set)
1358 SET_FLAGS(drv_flags, flags);
1359 else
1360 RESET_FLAGS(drv_flags, flags);
1361
1362 SHMEM2_WR(bp, drv_flags, drv_flags);
1363 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags);
1364 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1365 }
1366}
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len);
1379
1380int bnx2x_drain_tx_queues(struct bnx2x *bp);
1381void bnx2x_squeeze_objects(struct bnx2x *bp);
1382
1383void bnx2x_schedule_sp_rtnl(struct bnx2x*, enum sp_rtnl_flag,
1384 u32 verbose);
1385
1386
1387
1388
1389
1390
1391
1392void bnx2x_set_os_driver_state(struct bnx2x *bp, u32 state);
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1403 int buf_size);
1404
1405#endif
1406