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21#ifndef BNX2X_SP_VERBS
22#define BNX2X_SP_VERBS
23
24struct bnx2x;
25struct eth_context;
26
27
28enum {
29 RAMROD_TX,
30 RAMROD_RX,
31
32 RAMROD_COMP_WAIT,
33
34 RAMROD_DRV_CLR_ONLY,
35
36 RAMROD_RESTORE,
37
38 RAMROD_EXEC,
39
40
41
42
43 RAMROD_CONT,
44
45
46
47
48
49 RAMROD_RETRY,
50};
51
52typedef enum {
53 BNX2X_OBJ_TYPE_RX,
54 BNX2X_OBJ_TYPE_TX,
55 BNX2X_OBJ_TYPE_RX_TX,
56} bnx2x_obj_type;
57
58
59enum {
60 BNX2X_FILTER_MAC_PENDING,
61 BNX2X_FILTER_VLAN_PENDING,
62 BNX2X_FILTER_VLAN_MAC_PENDING,
63 BNX2X_FILTER_RX_MODE_PENDING,
64 BNX2X_FILTER_RX_MODE_SCHED,
65 BNX2X_FILTER_ISCSI_ETH_START_SCHED,
66 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
67 BNX2X_FILTER_FCOE_ETH_START_SCHED,
68 BNX2X_FILTER_FCOE_ETH_STOP_SCHED,
69 BNX2X_FILTER_MCAST_PENDING,
70 BNX2X_FILTER_MCAST_SCHED,
71 BNX2X_FILTER_RSS_CONF_PENDING,
72 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING,
73 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
74};
75
76struct bnx2x_raw_obj {
77 u8 func_id;
78
79
80 u8 cl_id;
81 u32 cid;
82
83
84 void *rdata;
85 dma_addr_t rdata_mapping;
86
87
88 int state;
89 unsigned long *pstate;
90
91 bnx2x_obj_type obj_type;
92
93 int (*wait_comp)(struct bnx2x *bp,
94 struct bnx2x_raw_obj *o);
95
96 bool (*check_pending)(struct bnx2x_raw_obj *o);
97 void (*clear_pending)(struct bnx2x_raw_obj *o);
98 void (*set_pending)(struct bnx2x_raw_obj *o);
99};
100
101
102struct bnx2x_mac_ramrod_data {
103 u8 mac[ETH_ALEN];
104 u8 is_inner_mac;
105};
106
107struct bnx2x_vlan_ramrod_data {
108 u16 vlan;
109};
110
111struct bnx2x_vlan_mac_ramrod_data {
112 u8 mac[ETH_ALEN];
113 u8 is_inner_mac;
114 u16 vlan;
115};
116
117union bnx2x_classification_ramrod_data {
118 struct bnx2x_mac_ramrod_data mac;
119 struct bnx2x_vlan_ramrod_data vlan;
120 struct bnx2x_vlan_mac_ramrod_data vlan_mac;
121};
122
123
124enum bnx2x_vlan_mac_cmd {
125 BNX2X_VLAN_MAC_ADD,
126 BNX2X_VLAN_MAC_DEL,
127 BNX2X_VLAN_MAC_MOVE,
128};
129
130struct bnx2x_vlan_mac_data {
131
132 enum bnx2x_vlan_mac_cmd cmd;
133
134
135
136 unsigned long vlan_mac_flags;
137
138
139 struct bnx2x_vlan_mac_obj *target_obj;
140
141 union bnx2x_classification_ramrod_data u;
142};
143
144
145union bnx2x_exe_queue_cmd_data {
146 struct bnx2x_vlan_mac_data vlan_mac;
147
148 struct {
149
150 } mcast;
151};
152
153struct bnx2x_exeq_elem {
154 struct list_head link;
155
156
157 int cmd_len;
158
159 union bnx2x_exe_queue_cmd_data cmd_data;
160};
161
162union bnx2x_qable_obj;
163
164union bnx2x_exeq_comp_elem {
165 union event_ring_elem *elem;
166};
167
168struct bnx2x_exe_queue_obj;
169
170typedef int (*exe_q_validate)(struct bnx2x *bp,
171 union bnx2x_qable_obj *o,
172 struct bnx2x_exeq_elem *elem);
173
174typedef int (*exe_q_remove)(struct bnx2x *bp,
175 union bnx2x_qable_obj *o,
176 struct bnx2x_exeq_elem *elem);
177
178
179
180
181typedef int (*exe_q_optimize)(struct bnx2x *bp,
182 union bnx2x_qable_obj *o,
183 struct bnx2x_exeq_elem *elem);
184typedef int (*exe_q_execute)(struct bnx2x *bp,
185 union bnx2x_qable_obj *o,
186 struct list_head *exe_chunk,
187 unsigned long *ramrod_flags);
188typedef struct bnx2x_exeq_elem *
189 (*exe_q_get)(struct bnx2x_exe_queue_obj *o,
190 struct bnx2x_exeq_elem *elem);
191
192struct bnx2x_exe_queue_obj {
193
194 struct list_head exe_queue;
195
196
197 struct list_head pending_comp;
198
199 spinlock_t lock;
200
201
202 int exe_chunk_len;
203
204 union bnx2x_qable_obj *owner;
205
206
207
208
209
210
211
212
213 exe_q_validate validate;
214
215
216
217
218
219 exe_q_remove remove;
220
221
222
223
224
225
226
227
228
229 exe_q_optimize optimize;
230
231
232
233
234 exe_q_execute execute;
235
236
237
238
239
240 exe_q_get get;
241};
242
243
244
245
246
247struct bnx2x_vlan_mac_registry_elem {
248 struct list_head link;
249
250
251
252
253
254 int cam_offset;
255
256
257 unsigned long vlan_mac_flags;
258
259 union bnx2x_classification_ramrod_data u;
260};
261
262
263enum {
264 BNX2X_UC_LIST_MAC,
265 BNX2X_ETH_MAC,
266 BNX2X_ISCSI_ETH_MAC,
267 BNX2X_NETQ_ETH_MAC,
268 BNX2X_DONT_CONSUME_CAM_CREDIT,
269 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
270};
271
272#define BNX2X_VLAN_MAC_CMP_MASK (1 << BNX2X_UC_LIST_MAC | \
273 1 << BNX2X_ETH_MAC | \
274 1 << BNX2X_ISCSI_ETH_MAC | \
275 1 << BNX2X_NETQ_ETH_MAC)
276#define BNX2X_VLAN_MAC_CMP_FLAGS(flags) \
277 ((flags) & BNX2X_VLAN_MAC_CMP_MASK)
278
279struct bnx2x_vlan_mac_ramrod_params {
280
281 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
282
283
284 unsigned long ramrod_flags;
285
286
287 struct bnx2x_vlan_mac_data user_req;
288};
289
290struct bnx2x_vlan_mac_obj {
291 struct bnx2x_raw_obj raw;
292
293
294
295
296 struct list_head head;
297
298
299
300 u8 head_reader;
301 bool head_exe_request;
302 unsigned long saved_ramrod_flags;
303
304
305 struct bnx2x_exe_queue_obj exe_queue;
306
307
308 struct bnx2x_credit_pool_obj *macs_pool;
309
310
311 struct bnx2x_credit_pool_obj *vlans_pool;
312
313
314 int ramrod_cmd;
315
316
317
318
319
320
321
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323
324
325
326 int (*get_n_elements)(struct bnx2x *bp,
327 struct bnx2x_vlan_mac_obj *o, int n, u8 *base,
328 u8 stride, u8 size);
329
330
331
332
333
334
335
336 int (*check_add)(struct bnx2x *bp,
337 struct bnx2x_vlan_mac_obj *o,
338 union bnx2x_classification_ramrod_data *data);
339
340
341
342
343
344
345 struct bnx2x_vlan_mac_registry_elem *
346 (*check_del)(struct bnx2x *bp,
347 struct bnx2x_vlan_mac_obj *o,
348 union bnx2x_classification_ramrod_data *data);
349
350
351
352
353
354
355 bool (*check_move)(struct bnx2x *bp,
356 struct bnx2x_vlan_mac_obj *src_o,
357 struct bnx2x_vlan_mac_obj *dst_o,
358 union bnx2x_classification_ramrod_data *data);
359
360
361
362
363
364 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o);
365 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o);
366 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset);
367 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset);
368
369
370
371
372 void (*set_one_rule)(struct bnx2x *bp,
373 struct bnx2x_vlan_mac_obj *o,
374 struct bnx2x_exeq_elem *elem, int rule_idx,
375 int cam_offset);
376
377
378
379
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381
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385
386
387
388
389
390
391
392
393
394 int (*delete_all)(struct bnx2x *bp,
395 struct bnx2x_vlan_mac_obj *o,
396 unsigned long *vlan_mac_flags,
397 unsigned long *ramrod_flags);
398
399
400
401
402
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407
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409
410
411
412
413
414 int (*restore)(struct bnx2x *bp,
415 struct bnx2x_vlan_mac_ramrod_params *p,
416 struct bnx2x_vlan_mac_registry_elem **ppos);
417
418
419
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421
422
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424
425
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427
428
429
430
431
432
433
434
435 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
436 union event_ring_elem *cqe,
437 unsigned long *ramrod_flags);
438
439
440
441
442
443
444 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o);
445};
446
447enum {
448 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0,
449 BNX2X_LLH_CAM_ETH_LINE,
450 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
451};
452
453
454
455
456
457
458enum {
459 BNX2X_RX_MODE_FCOE_ETH,
460 BNX2X_RX_MODE_ISCSI_ETH,
461};
462
463enum {
464 BNX2X_ACCEPT_UNICAST,
465 BNX2X_ACCEPT_MULTICAST,
466 BNX2X_ACCEPT_ALL_UNICAST,
467 BNX2X_ACCEPT_ALL_MULTICAST,
468 BNX2X_ACCEPT_BROADCAST,
469 BNX2X_ACCEPT_UNMATCHED,
470 BNX2X_ACCEPT_ANY_VLAN
471};
472
473struct bnx2x_rx_mode_ramrod_params {
474 struct bnx2x_rx_mode_obj *rx_mode_obj;
475 unsigned long *pstate;
476 int state;
477 u8 cl_id;
478 u32 cid;
479 u8 func_id;
480 unsigned long ramrod_flags;
481 unsigned long rx_mode_flags;
482
483
484
485
486 void *rdata;
487 dma_addr_t rdata_mapping;
488
489
490 unsigned long rx_accept_flags;
491
492
493 unsigned long tx_accept_flags;
494};
495
496struct bnx2x_rx_mode_obj {
497 int (*config_rx_mode)(struct bnx2x *bp,
498 struct bnx2x_rx_mode_ramrod_params *p);
499
500 int (*wait_comp)(struct bnx2x *bp,
501 struct bnx2x_rx_mode_ramrod_params *p);
502};
503
504
505
506struct bnx2x_mcast_list_elem {
507 struct list_head link;
508 u8 *mac;
509};
510
511union bnx2x_mcast_config_data {
512 u8 *mac;
513 u8 bin;
514};
515
516struct bnx2x_mcast_ramrod_params {
517 struct bnx2x_mcast_obj *mcast_obj;
518
519
520 unsigned long ramrod_flags;
521
522 struct list_head mcast_list;
523
524
525
526
527
528
529
530
531 int mcast_list_len;
532};
533
534enum bnx2x_mcast_cmd {
535 BNX2X_MCAST_CMD_ADD,
536 BNX2X_MCAST_CMD_CONT,
537 BNX2X_MCAST_CMD_DEL,
538 BNX2X_MCAST_CMD_RESTORE,
539};
540
541struct bnx2x_mcast_obj {
542 struct bnx2x_raw_obj raw;
543
544 union {
545 struct {
546 #define BNX2X_MCAST_BINS_NUM 256
547 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64)
548 u64 vec[BNX2X_MCAST_VEC_SZ];
549
550
551
552
553
554 int num_bins_set;
555 } aprox_match;
556
557 struct {
558 struct list_head macs;
559 int num_macs_set;
560 } exact_match;
561 } registry;
562
563
564 struct list_head pending_cmds_head;
565
566
567 int sched_state;
568
569
570 int max_cmd_len;
571
572
573
574
575 int total_pending_num;
576
577 u8 engine_id;
578
579
580
581
582 int (*config_mcast)(struct bnx2x *bp,
583 struct bnx2x_mcast_ramrod_params *p,
584 enum bnx2x_mcast_cmd cmd);
585
586
587
588
589
590
591
592
593
594
595
596
597 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
598 int start_bin, int *rdata_idx);
599
600 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
601 struct bnx2x_mcast_ramrod_params *p,
602 enum bnx2x_mcast_cmd cmd);
603
604 void (*set_one_rule)(struct bnx2x *bp,
605 struct bnx2x_mcast_obj *o, int idx,
606 union bnx2x_mcast_config_data *cfg_data,
607 enum bnx2x_mcast_cmd cmd);
608
609
610
611
612 bool (*check_pending)(struct bnx2x_mcast_obj *o);
613
614
615
616
617 void (*set_sched)(struct bnx2x_mcast_obj *o);
618 void (*clear_sched)(struct bnx2x_mcast_obj *o);
619 bool (*check_sched)(struct bnx2x_mcast_obj *o);
620
621
622 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o);
623
624
625
626
627
628
629 int (*validate)(struct bnx2x *bp,
630 struct bnx2x_mcast_ramrod_params *p,
631 enum bnx2x_mcast_cmd cmd);
632
633
634
635
636 void (*revert)(struct bnx2x *bp,
637 struct bnx2x_mcast_ramrod_params *p,
638 int old_num_bins);
639
640 int (*get_registry_size)(struct bnx2x_mcast_obj *o);
641 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n);
642};
643
644
645struct bnx2x_credit_pool_obj {
646
647
648 atomic_t credit;
649
650
651 int pool_sz;
652
653
654
655
656
657
658
659#define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
660 u64 pool_mirror[BNX2X_POOL_VEC_SIZE];
661
662
663 int base_pool_offset;
664
665
666
667
668
669
670 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry);
671
672
673
674
675
676
677
678 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry);
679
680
681
682
683
684
685
686 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt);
687
688
689
690
691
692
693
694 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt);
695
696
697
698
699 int (*check)(struct bnx2x_credit_pool_obj *o);
700};
701
702
703enum {
704
705 BNX2X_RSS_MODE_DISABLED,
706 BNX2X_RSS_MODE_REGULAR,
707
708 BNX2X_RSS_SET_SRCH,
709
710 BNX2X_RSS_IPV4,
711 BNX2X_RSS_IPV4_TCP,
712 BNX2X_RSS_IPV4_UDP,
713 BNX2X_RSS_IPV6,
714 BNX2X_RSS_IPV6_TCP,
715 BNX2X_RSS_IPV6_UDP,
716
717 BNX2X_RSS_IPV4_VXLAN,
718 BNX2X_RSS_IPV6_VXLAN,
719 BNX2X_RSS_TUNN_INNER_HDRS,
720};
721
722struct bnx2x_config_rss_params {
723 struct bnx2x_rss_config_obj *rss_obj;
724
725
726 unsigned long ramrod_flags;
727
728
729 unsigned long rss_flags;
730
731
732 u8 rss_result_mask;
733
734
735 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
736
737
738 u32 rss_key[10];
739
740
741 u16 toe_rss_bitmap;
742};
743
744struct bnx2x_rss_config_obj {
745 struct bnx2x_raw_obj raw;
746
747
748 u8 engine_id;
749
750
751 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
752
753
754 u8 udp_rss_v4;
755 u8 udp_rss_v6;
756
757 int (*config_rss)(struct bnx2x *bp,
758 struct bnx2x_config_rss_params *p);
759};
760
761
762
763
764enum {
765 BNX2X_Q_UPDATE_IN_VLAN_REM,
766 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
767 BNX2X_Q_UPDATE_OUT_VLAN_REM,
768 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
769 BNX2X_Q_UPDATE_ANTI_SPOOF,
770 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG,
771 BNX2X_Q_UPDATE_ACTIVATE,
772 BNX2X_Q_UPDATE_ACTIVATE_CHNG,
773 BNX2X_Q_UPDATE_DEF_VLAN_EN,
774 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
775 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
776 BNX2X_Q_UPDATE_SILENT_VLAN_REM,
777 BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
778 BNX2X_Q_UPDATE_TX_SWITCHING,
779 BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
780 BNX2X_Q_UPDATE_PTP_PKTS,
781};
782
783
784enum bnx2x_q_state {
785 BNX2X_Q_STATE_RESET,
786 BNX2X_Q_STATE_INITIALIZED,
787 BNX2X_Q_STATE_ACTIVE,
788 BNX2X_Q_STATE_MULTI_COS,
789 BNX2X_Q_STATE_MCOS_TERMINATED,
790 BNX2X_Q_STATE_INACTIVE,
791 BNX2X_Q_STATE_STOPPED,
792 BNX2X_Q_STATE_TERMINATED,
793 BNX2X_Q_STATE_FLRED,
794 BNX2X_Q_STATE_MAX,
795};
796
797
798enum bnx2x_q_logical_state {
799 BNX2X_Q_LOGICAL_STATE_ACTIVE,
800 BNX2X_Q_LOGICAL_STATE_STOPPED,
801};
802
803
804enum bnx2x_queue_cmd {
805 BNX2X_Q_CMD_INIT,
806 BNX2X_Q_CMD_SETUP,
807 BNX2X_Q_CMD_SETUP_TX_ONLY,
808 BNX2X_Q_CMD_DEACTIVATE,
809 BNX2X_Q_CMD_ACTIVATE,
810 BNX2X_Q_CMD_UPDATE,
811 BNX2X_Q_CMD_UPDATE_TPA,
812 BNX2X_Q_CMD_HALT,
813 BNX2X_Q_CMD_CFC_DEL,
814 BNX2X_Q_CMD_TERMINATE,
815 BNX2X_Q_CMD_EMPTY,
816 BNX2X_Q_CMD_MAX,
817};
818
819
820enum {
821 BNX2X_Q_FLG_TPA,
822 BNX2X_Q_FLG_TPA_IPV6,
823 BNX2X_Q_FLG_TPA_GRO,
824 BNX2X_Q_FLG_STATS,
825 BNX2X_Q_FLG_ZERO_STATS,
826 BNX2X_Q_FLG_ACTIVE,
827 BNX2X_Q_FLG_OV,
828 BNX2X_Q_FLG_VLAN,
829 BNX2X_Q_FLG_COS,
830 BNX2X_Q_FLG_HC,
831 BNX2X_Q_FLG_HC_EN,
832 BNX2X_Q_FLG_DHC,
833 BNX2X_Q_FLG_FCOE,
834 BNX2X_Q_FLG_LEADING_RSS,
835 BNX2X_Q_FLG_MCAST,
836 BNX2X_Q_FLG_DEF_VLAN,
837 BNX2X_Q_FLG_TX_SWITCH,
838 BNX2X_Q_FLG_TX_SEC,
839 BNX2X_Q_FLG_ANTI_SPOOF,
840 BNX2X_Q_FLG_SILENT_VLAN_REM,
841 BNX2X_Q_FLG_FORCE_DEFAULT_PRI,
842 BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN,
843 BNX2X_Q_FLG_PCSUM_ON_PKT,
844 BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
845};
846
847
848enum bnx2x_q_type {
849
850
851
852 BNX2X_Q_TYPE_HAS_RX,
853 BNX2X_Q_TYPE_HAS_TX,
854};
855
856#define BNX2X_PRIMARY_CID_INDEX 0
857#define BNX2X_MULTI_TX_COS_E1X 3
858#define BNX2X_MULTI_TX_COS_E2_E3A0 2
859#define BNX2X_MULTI_TX_COS_E3B0 3
860#define BNX2X_MULTI_TX_COS 3
861
862#define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
863
864
865
866#define FW_DMAE_CMD_ID 6
867
868struct bnx2x_queue_init_params {
869 struct {
870 unsigned long flags;
871 u16 hc_rate;
872 u8 fw_sb_id;
873 u8 sb_cq_index;
874 } tx;
875
876 struct {
877 unsigned long flags;
878 u16 hc_rate;
879 u8 fw_sb_id;
880 u8 sb_cq_index;
881 } rx;
882
883
884 struct eth_context *cxts[BNX2X_MULTI_TX_COS];
885
886
887 u8 max_cos;
888};
889
890struct bnx2x_queue_terminate_params {
891
892 u8 cid_index;
893};
894
895struct bnx2x_queue_cfc_del_params {
896
897 u8 cid_index;
898};
899
900struct bnx2x_queue_update_params {
901 unsigned long update_flags;
902 u16 def_vlan;
903 u16 silent_removal_value;
904 u16 silent_removal_mask;
905
906 u8 cid_index;
907};
908
909struct bnx2x_queue_update_tpa_params {
910 dma_addr_t sge_map;
911 u8 update_ipv4;
912 u8 update_ipv6;
913 u8 max_tpa_queues;
914 u8 max_sges_pkt;
915 u8 complete_on_both_clients;
916 u8 dont_verify_thr;
917 u8 tpa_mode;
918 u8 _pad;
919
920 u16 sge_buff_sz;
921 u16 max_agg_sz;
922
923 u16 sge_pause_thr_low;
924 u16 sge_pause_thr_high;
925};
926
927struct rxq_pause_params {
928 u16 bd_th_lo;
929 u16 bd_th_hi;
930 u16 rcq_th_lo;
931 u16 rcq_th_hi;
932 u16 sge_th_lo;
933 u16 sge_th_hi;
934 u16 pri_map;
935};
936
937
938struct bnx2x_general_setup_params {
939
940 u8 stat_id;
941
942 u8 spcl_id;
943 u16 mtu;
944 u8 cos;
945
946 u8 fp_hsi;
947};
948
949struct bnx2x_rxq_setup_params {
950
951 dma_addr_t dscr_map;
952 dma_addr_t sge_map;
953 dma_addr_t rcq_map;
954 dma_addr_t rcq_np_map;
955
956 u16 drop_flags;
957 u16 buf_sz;
958 u8 fw_sb_id;
959 u8 cl_qzone_id;
960
961
962 u16 tpa_agg_sz;
963 u16 sge_buf_sz;
964 u8 max_sges_pkt;
965 u8 max_tpa_queues;
966 u8 rss_engine_id;
967
968
969 u8 mcast_engine_id;
970
971 u8 cache_line_log;
972
973 u8 sb_cq_index;
974
975
976 u16 silent_removal_value;
977 u16 silent_removal_mask;
978};
979
980struct bnx2x_txq_setup_params {
981
982 dma_addr_t dscr_map;
983
984 u8 fw_sb_id;
985 u8 sb_cq_index;
986 u8 cos;
987 u16 traffic_type;
988
989 u8 tss_leading_cl_id;
990
991
992 u16 default_vlan;
993};
994
995struct bnx2x_queue_setup_params {
996 struct bnx2x_general_setup_params gen_params;
997 struct bnx2x_txq_setup_params txq_params;
998 struct bnx2x_rxq_setup_params rxq_params;
999 struct rxq_pause_params pause_params;
1000 unsigned long flags;
1001};
1002
1003struct bnx2x_queue_setup_tx_only_params {
1004 struct bnx2x_general_setup_params gen_params;
1005 struct bnx2x_txq_setup_params txq_params;
1006 unsigned long flags;
1007
1008 u8 cid_index;
1009};
1010
1011struct bnx2x_queue_state_params {
1012 struct bnx2x_queue_sp_obj *q_obj;
1013
1014
1015 enum bnx2x_queue_cmd cmd;
1016
1017
1018 unsigned long ramrod_flags;
1019
1020
1021 union {
1022 struct bnx2x_queue_update_params update;
1023 struct bnx2x_queue_update_tpa_params update_tpa;
1024 struct bnx2x_queue_setup_params setup;
1025 struct bnx2x_queue_init_params init;
1026 struct bnx2x_queue_setup_tx_only_params tx_only;
1027 struct bnx2x_queue_terminate_params terminate;
1028 struct bnx2x_queue_cfc_del_params cfc_del;
1029 } params;
1030};
1031
1032struct bnx2x_viflist_params {
1033 u8 echo_res;
1034 u8 func_bit_map_res;
1035};
1036
1037struct bnx2x_queue_sp_obj {
1038 u32 cids[BNX2X_MULTI_TX_COS];
1039 u8 cl_id;
1040 u8 func_id;
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050 u8 max_cos;
1051 u8 num_tx_only, next_tx_only;
1052
1053 enum bnx2x_q_state state, next_state;
1054
1055
1056 unsigned long type;
1057
1058
1059
1060
1061
1062
1063 unsigned long pending;
1064
1065
1066 void *rdata;
1067 dma_addr_t rdata_mapping;
1068
1069
1070
1071
1072
1073
1074 int (*send_cmd)(struct bnx2x *bp,
1075 struct bnx2x_queue_state_params *params);
1076
1077
1078
1079
1080 int (*set_pending)(struct bnx2x_queue_sp_obj *o,
1081 struct bnx2x_queue_state_params *params);
1082
1083
1084
1085
1086 int (*check_transition)(struct bnx2x *bp,
1087 struct bnx2x_queue_sp_obj *o,
1088 struct bnx2x_queue_state_params *params);
1089
1090
1091
1092
1093 int (*complete_cmd)(struct bnx2x *bp,
1094 struct bnx2x_queue_sp_obj *o,
1095 enum bnx2x_queue_cmd);
1096
1097 int (*wait_comp)(struct bnx2x *bp,
1098 struct bnx2x_queue_sp_obj *o,
1099 enum bnx2x_queue_cmd cmd);
1100};
1101
1102
1103
1104
1105enum {
1106 BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
1107 BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
1108 BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
1109 BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,
1110 BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
1111 BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
1112 BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
1113 BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
1114 BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
1115 BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
1116 BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
1117};
1118
1119
1120enum bnx2x_func_state {
1121 BNX2X_F_STATE_RESET,
1122 BNX2X_F_STATE_INITIALIZED,
1123 BNX2X_F_STATE_STARTED,
1124 BNX2X_F_STATE_TX_STOPPED,
1125 BNX2X_F_STATE_MAX,
1126};
1127
1128
1129enum bnx2x_func_cmd {
1130 BNX2X_F_CMD_HW_INIT,
1131 BNX2X_F_CMD_START,
1132 BNX2X_F_CMD_STOP,
1133 BNX2X_F_CMD_HW_RESET,
1134 BNX2X_F_CMD_AFEX_UPDATE,
1135 BNX2X_F_CMD_AFEX_VIFLISTS,
1136 BNX2X_F_CMD_TX_STOP,
1137 BNX2X_F_CMD_TX_START,
1138 BNX2X_F_CMD_SWITCH_UPDATE,
1139 BNX2X_F_CMD_SET_TIMESYNC,
1140 BNX2X_F_CMD_MAX,
1141};
1142
1143struct bnx2x_func_hw_init_params {
1144
1145
1146
1147
1148
1149
1150
1151
1152 u32 load_phase;
1153};
1154
1155struct bnx2x_func_hw_reset_params {
1156
1157
1158
1159
1160
1161
1162
1163
1164 u32 reset_phase;
1165};
1166
1167struct bnx2x_func_start_params {
1168
1169
1170
1171
1172
1173 u16 mf_mode;
1174
1175
1176 u16 sd_vlan_tag;
1177
1178
1179 u8 network_cos_mode;
1180
1181
1182 u16 vxlan_dst_port;
1183
1184
1185 u16 geneve_dst_port;
1186
1187
1188 u8 inner_clss_l2gre;
1189
1190
1191 u8 inner_clss_l2geneve;
1192
1193
1194 u8 inner_clss_vxlan;
1195
1196
1197 u8 inner_rss;
1198
1199
1200
1201
1202 u8 class_fail;
1203 u16 class_fail_ethtype;
1204
1205
1206 u8 sd_vlan_force_pri;
1207 u8 sd_vlan_force_pri_val;
1208
1209
1210 u16 sd_vlan_eth_type;
1211
1212
1213 u8 no_added_tags;
1214
1215
1216 u8 c2s_pri[MAX_VLAN_PRIORITIES];
1217 u8 c2s_pri_default;
1218 u8 c2s_pri_valid;
1219};
1220
1221struct bnx2x_func_switch_update_params {
1222 unsigned long changes;
1223 u16 vlan;
1224 u16 vlan_eth_type;
1225 u8 vlan_force_prio;
1226 u16 vxlan_dst_port;
1227 u16 geneve_dst_port;
1228};
1229
1230struct bnx2x_func_afex_update_params {
1231 u16 vif_id;
1232 u16 afex_default_vlan;
1233 u8 allowed_priorities;
1234};
1235
1236struct bnx2x_func_afex_viflists_params {
1237 u16 vif_list_index;
1238 u8 func_bit_map;
1239 u8 afex_vif_list_command;
1240 u8 func_to_clear;
1241};
1242
1243struct bnx2x_func_tx_start_params {
1244 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1245 u8 dcb_enabled;
1246 u8 dcb_version;
1247 u8 dont_add_pri_0_en;
1248 u8 dcb_outer_pri[MAX_TRAFFIC_TYPES];
1249};
1250
1251struct bnx2x_func_set_timesync_params {
1252
1253 u8 drift_adjust_cmd;
1254
1255
1256 u8 offset_cmd;
1257
1258
1259 u8 add_sub_drift_adjust_value;
1260
1261
1262
1263
1264 u8 drift_adjust_value;
1265 u32 drift_adjust_period;
1266 u64 offset_delta;
1267};
1268
1269struct bnx2x_func_state_params {
1270 struct bnx2x_func_sp_obj *f_obj;
1271
1272
1273 enum bnx2x_func_cmd cmd;
1274
1275
1276 unsigned long ramrod_flags;
1277
1278
1279 union {
1280 struct bnx2x_func_hw_init_params hw_init;
1281 struct bnx2x_func_hw_reset_params hw_reset;
1282 struct bnx2x_func_start_params start;
1283 struct bnx2x_func_switch_update_params switch_update;
1284 struct bnx2x_func_afex_update_params afex_update;
1285 struct bnx2x_func_afex_viflists_params afex_viflists;
1286 struct bnx2x_func_tx_start_params tx_start;
1287 struct bnx2x_func_set_timesync_params set_timesync;
1288 } params;
1289};
1290
1291struct bnx2x_func_sp_drv_ops {
1292
1293
1294
1295
1296
1297
1298 int (*init_hw_cmn_chip)(struct bnx2x *bp);
1299 int (*init_hw_cmn)(struct bnx2x *bp);
1300 int (*init_hw_port)(struct bnx2x *bp);
1301 int (*init_hw_func)(struct bnx2x *bp);
1302
1303
1304 void (*reset_hw_cmn)(struct bnx2x *bp);
1305 void (*reset_hw_port)(struct bnx2x *bp);
1306 void (*reset_hw_func)(struct bnx2x *bp);
1307
1308
1309 int (*gunzip_init)(struct bnx2x *bp);
1310 void (*gunzip_end)(struct bnx2x *bp);
1311
1312
1313 int (*init_fw)(struct bnx2x *bp);
1314 void (*release_fw)(struct bnx2x *bp);
1315};
1316
1317struct bnx2x_func_sp_obj {
1318 enum bnx2x_func_state state, next_state;
1319
1320
1321
1322
1323
1324
1325 unsigned long pending;
1326
1327
1328 void *rdata;
1329 dma_addr_t rdata_mapping;
1330
1331
1332
1333
1334
1335 void *afex_rdata;
1336 dma_addr_t afex_rdata_mapping;
1337
1338
1339
1340
1341 struct mutex one_pending_mutex;
1342
1343
1344 struct bnx2x_func_sp_drv_ops *drv;
1345
1346
1347
1348
1349
1350
1351 int (*send_cmd)(struct bnx2x *bp,
1352 struct bnx2x_func_state_params *params);
1353
1354
1355
1356
1357 int (*check_transition)(struct bnx2x *bp,
1358 struct bnx2x_func_sp_obj *o,
1359 struct bnx2x_func_state_params *params);
1360
1361
1362
1363
1364 int (*complete_cmd)(struct bnx2x *bp,
1365 struct bnx2x_func_sp_obj *o,
1366 enum bnx2x_func_cmd cmd);
1367
1368 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o,
1369 enum bnx2x_func_cmd cmd);
1370};
1371
1372
1373
1374union bnx2x_qable_obj {
1375 struct bnx2x_vlan_mac_obj vlan_mac;
1376};
1377
1378void bnx2x_init_func_obj(struct bnx2x *bp,
1379 struct bnx2x_func_sp_obj *obj,
1380 void *rdata, dma_addr_t rdata_mapping,
1381 void *afex_rdata, dma_addr_t afex_rdata_mapping,
1382 struct bnx2x_func_sp_drv_ops *drv_iface);
1383
1384int bnx2x_func_state_change(struct bnx2x *bp,
1385 struct bnx2x_func_state_params *params);
1386
1387enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
1388 struct bnx2x_func_sp_obj *o);
1389
1390void bnx2x_init_queue_obj(struct bnx2x *bp,
1391 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids,
1392 u8 cid_cnt, u8 func_id, void *rdata,
1393 dma_addr_t rdata_mapping, unsigned long type);
1394
1395int bnx2x_queue_state_change(struct bnx2x *bp,
1396 struct bnx2x_queue_state_params *params);
1397
1398int bnx2x_get_q_logical_state(struct bnx2x *bp,
1399 struct bnx2x_queue_sp_obj *obj);
1400
1401
1402void bnx2x_init_mac_obj(struct bnx2x *bp,
1403 struct bnx2x_vlan_mac_obj *mac_obj,
1404 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1405 dma_addr_t rdata_mapping, int state,
1406 unsigned long *pstate, bnx2x_obj_type type,
1407 struct bnx2x_credit_pool_obj *macs_pool);
1408
1409void bnx2x_init_vlan_obj(struct bnx2x *bp,
1410 struct bnx2x_vlan_mac_obj *vlan_obj,
1411 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1412 dma_addr_t rdata_mapping, int state,
1413 unsigned long *pstate, bnx2x_obj_type type,
1414 struct bnx2x_credit_pool_obj *vlans_pool);
1415
1416void bnx2x_init_vlan_mac_obj(struct bnx2x *bp,
1417 struct bnx2x_vlan_mac_obj *vlan_mac_obj,
1418 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1419 dma_addr_t rdata_mapping, int state,
1420 unsigned long *pstate, bnx2x_obj_type type,
1421 struct bnx2x_credit_pool_obj *macs_pool,
1422 struct bnx2x_credit_pool_obj *vlans_pool);
1423
1424int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp,
1425 struct bnx2x_vlan_mac_obj *o);
1426void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp,
1427 struct bnx2x_vlan_mac_obj *o);
1428int bnx2x_vlan_mac_h_write_lock(struct bnx2x *bp,
1429 struct bnx2x_vlan_mac_obj *o);
1430int bnx2x_config_vlan_mac(struct bnx2x *bp,
1431 struct bnx2x_vlan_mac_ramrod_params *p);
1432
1433int bnx2x_vlan_mac_move(struct bnx2x *bp,
1434 struct bnx2x_vlan_mac_ramrod_params *p,
1435 struct bnx2x_vlan_mac_obj *dest_o);
1436
1437
1438
1439void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
1440 struct bnx2x_rx_mode_obj *o);
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451int bnx2x_config_rx_mode(struct bnx2x *bp,
1452 struct bnx2x_rx_mode_ramrod_params *p);
1453
1454
1455
1456void bnx2x_init_mcast_obj(struct bnx2x *bp,
1457 struct bnx2x_mcast_obj *mcast_obj,
1458 u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
1459 u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
1460 int state, unsigned long *pstate,
1461 bnx2x_obj_type type);
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483int bnx2x_config_mcast(struct bnx2x *bp,
1484 struct bnx2x_mcast_ramrod_params *p,
1485 enum bnx2x_mcast_cmd cmd);
1486
1487
1488void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
1489 struct bnx2x_credit_pool_obj *p, u8 func_id,
1490 u8 func_num);
1491void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
1492 struct bnx2x_credit_pool_obj *p, u8 func_id,
1493 u8 func_num);
1494void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p,
1495 int base, int credit);
1496
1497
1498void bnx2x_init_rss_config_obj(struct bnx2x *bp,
1499 struct bnx2x_rss_config_obj *rss_obj,
1500 u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
1501 void *rdata, dma_addr_t rdata_mapping,
1502 int state, unsigned long *pstate,
1503 bnx2x_obj_type type);
1504
1505
1506
1507
1508
1509
1510int bnx2x_config_rss(struct bnx2x *bp,
1511 struct bnx2x_config_rss_params *p);
1512
1513
1514
1515
1516
1517
1518
1519
1520void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
1521 u8 *ind_table);
1522
1523#define PF_MAC_CREDIT_E2(bp, func_num) \
1524 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(bp) * VF_MAC_CREDIT_CNT) / \
1525 func_num + GET_NUM_VFS_PER_PF(bp) * VF_MAC_CREDIT_CNT)
1526
1527#define PF_VLAN_CREDIT_E2(bp, func_num) \
1528 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(bp) * VF_VLAN_CREDIT_CNT) / \
1529 func_num + GET_NUM_VFS_PER_PF(bp) * VF_VLAN_CREDIT_CNT)
1530
1531#endif
1532