LXR linux/drivers/net/ethernet/cavium/liquidio/cn66xx

   1/**********************************************************************
   2* Author: Cavium, Inc.
   3*
   4* Contact: support@cavium.com
   5*          Please include "LiquidIO" in the subject.
   6*
   7* Copyright (c) 2003-2015 Cavium, Inc.
   8*
   9* This file is free software; you can redistribute it and/or modify
  10* it under the terms of the GNU General Public License, Version 2, as
  11* published by the Free Software Foundation.
  12*
  13* This file is distributed in the hope that it will be useful, but
  14* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16* NONINFRINGEMENT.  See the GNU General Public License for more
  17* details.
  18*
  19* This file may also be available under a different license from Cavium.
  20* Contact Cavium, Inc. for more information
  21**********************************************************************/
  22
  23/*! \file  cn66xx_device.h
  24 *  \brief Host Driver: Routines that perform CN66XX specific operations.
  25 */
  26
  27#ifndef __CN66XX_DEVICE_H__
  28#define  __CN66XX_DEVICE_H__
  29
  30/* Register address and configuration for a CN6XXX devices.
  31 * If device specific changes need to be made then add a struct to include
  32 * device specific fields as shown in the commented section
  33 */
  34struct octeon_cn6xxx {
  35        /** PCI interrupt summary register */
  36        u8 __iomem *intr_sum_reg64;
  37
  38        /** PCI interrupt enable register */
  39        u8 __iomem *intr_enb_reg64;
  40
  41        /** The PCI interrupt mask used by interrupt handler */
  42        u64 intr_mask64;
  43
  44        struct octeon_config *conf;
  45
  46        /* Example additional fields - not used currently
  47         *  struct {
  48         *  }cn6xyz;
  49         */
  50
  51        /* For the purpose of atomic access to interrupt enable reg */
  52        spinlock_t lock_for_droq_int_enb_reg;
  53
  54};
  55
  56enum octeon_pcie_mps {
  57        PCIE_MPS_DEFAULT = -1,  /* Use the default setup by BIOS */
  58        PCIE_MPS_128B = 0,
  59        PCIE_MPS_256B = 1
  60};
  61
  62enum octeon_pcie_mrrs {
  63        PCIE_MRRS_DEFAULT = -1, /* Use the default setup by BIOS */
  64        PCIE_MRRS_128B = 0,
  65        PCIE_MRRS_256B = 1,
  66        PCIE_MRRS_512B = 2,
  67        PCIE_MRRS_1024B = 3,
  68        PCIE_MRRS_2048B = 4,
  69        PCIE_MRRS_4096B = 5
  70};
  71
  72/* Common functions for 66xx and 68xx */
  73int lio_cn6xxx_soft_reset(struct octeon_device *oct);
  74void lio_cn6xxx_enable_error_reporting(struct octeon_device *oct);
  75void lio_cn6xxx_setup_pcie_mps(struct octeon_device *oct,
  76                               enum octeon_pcie_mps mps);
  77void lio_cn6xxx_setup_pcie_mrrs(struct octeon_device *oct,
  78                                enum octeon_pcie_mrrs mrrs);
  79void lio_cn6xxx_setup_global_input_regs(struct octeon_device *oct);
  80void lio_cn6xxx_setup_global_output_regs(struct octeon_device *oct);
  81void lio_cn6xxx_setup_iq_regs(struct octeon_device *oct, u32 iq_no);
  82void lio_cn6xxx_setup_oq_regs(struct octeon_device *oct, u32 oq_no);
  83void lio_cn6xxx_enable_io_queues(struct octeon_device *oct);
  84void lio_cn6xxx_disable_io_queues(struct octeon_device *oct);
  85void lio_cn6xxx_process_pcie_error_intr(struct octeon_device *oct, u64 intr64);
  86int lio_cn6xxx_process_droq_intr_regs(struct octeon_device *oct);
  87irqreturn_t lio_cn6xxx_process_interrupt_regs(void *dev);
  88void lio_cn6xxx_reinit_regs(struct octeon_device *oct);
  89void lio_cn6xxx_bar1_idx_setup(struct octeon_device *oct, u64 core_addr,
  90                               u32 idx, int valid);
  91void lio_cn6xxx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask);
  92u32 lio_cn6xxx_bar1_idx_read(struct octeon_device *oct, u32 idx);
  93u32
  94lio_cn6xxx_update_read_index(struct octeon_device *oct __attribute__((unused)),
  95                             struct octeon_instr_queue *iq);
  96void lio_cn6xxx_enable_interrupt(void *chip);
  97void lio_cn6xxx_disable_interrupt(void *chip);
  98void cn6xxx_get_pcie_qlmport(struct octeon_device *oct);
  99void lio_cn6xxx_setup_reg_address(struct octeon_device *oct, void *chip,
 100                                  struct octeon_reg_list *reg_list);
 101u32 lio_cn6xxx_coprocessor_clock(struct octeon_device *oct);
 102u32 lio_cn6xxx_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us);
 103int lio_setup_cn66xx_octeon_device(struct octeon_device *);
 104int lio_validate_cn6xxx_config_info(struct octeon_device *oct,
 105                                    struct octeon_config *);
 106
 107#endif
 108