linux/drivers/net/ethernet/cavium/liquidio/octeon_console.c
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   1/**********************************************************************
   2* Author: Cavium, Inc.
   3*
   4* Contact: support@cavium.com
   5*          Please include "LiquidIO" in the subject.
   6*
   7* Copyright (c) 2003-2015 Cavium, Inc.
   8*
   9* This file is free software; you can redistribute it and/or modify
  10* it under the terms of the GNU General Public License, Version 2, as
  11* published by the Free Software Foundation.
  12*
  13* This file is distributed in the hope that it will be useful, but
  14* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16* NONINFRINGEMENT.  See the GNU General Public License for more
  17* details.
  18*
  19* This file may also be available under a different license from Cavium.
  20* Contact Cavium, Inc. for more information
  21**********************************************************************/
  22
  23/**
  24 * @file octeon_console.c
  25 */
  26#include <linux/version.h>
  27#include <linux/types.h>
  28#include <linux/list.h>
  29#include <linux/interrupt.h>
  30#include <linux/pci.h>
  31#include <linux/kthread.h>
  32#include <linux/netdevice.h>
  33#include "octeon_config.h"
  34#include "liquidio_common.h"
  35#include "octeon_droq.h"
  36#include "octeon_iq.h"
  37#include "response_manager.h"
  38#include "octeon_device.h"
  39#include "octeon_nic.h"
  40#include "octeon_main.h"
  41#include "octeon_network.h"
  42#include "cn66xx_regs.h"
  43#include "cn66xx_device.h"
  44#include "cn68xx_regs.h"
  45#include "cn68xx_device.h"
  46#include "liquidio_image.h"
  47#include "octeon_mem_ops.h"
  48
  49static void octeon_remote_lock(void);
  50static void octeon_remote_unlock(void);
  51static u64 cvmx_bootmem_phy_named_block_find(struct octeon_device *oct,
  52                                             const char *name,
  53                                             u32 flags);
  54
  55#define MIN(a, b) min((a), (b))
  56#define CAST_ULL(v) ((u64)(v))
  57
  58#define BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR    0x0006c008
  59#define BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR     0x0006c004
  60#define BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR   0x0006c000
  61#define BOOTLOADER_PCI_READ_DESC_ADDR           0x0006c100
  62#define BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN     248
  63
  64#define OCTEON_PCI_IO_BUF_OWNER_OCTEON    0x00000001
  65#define OCTEON_PCI_IO_BUF_OWNER_HOST      0x00000002
  66
  67/** Can change without breaking ABI */
  68#define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64
  69
  70/** minimum alignment of bootmem alloced blocks */
  71#define CVMX_BOOTMEM_ALIGNMENT_SIZE     (16ull)
  72
  73/** CVMX bootmem descriptor major version */
  74#define CVMX_BOOTMEM_DESC_MAJ_VER   3
  75/* CVMX bootmem descriptor minor version */
  76#define CVMX_BOOTMEM_DESC_MIN_VER   0
  77
  78/* Current versions */
  79#define OCTEON_PCI_CONSOLE_MAJOR_VERSION    1
  80#define OCTEON_PCI_CONSOLE_MINOR_VERSION    0
  81#define OCTEON_PCI_CONSOLE_BLOCK_NAME   "__pci_console"
  82#define OCTEON_CONSOLE_POLL_INTERVAL_MS  100    /* 10 times per second */
  83
  84/* First three members of cvmx_bootmem_desc are left in original
  85** positions for backwards compatibility.
  86** Assumes big endian target
  87*/
  88struct cvmx_bootmem_desc {
  89        /** spinlock to control access to list */
  90        u32 lock;
  91
  92        /** flags for indicating various conditions */
  93        u32 flags;
  94
  95        u64 head_addr;
  96
  97        /** incremented changed when incompatible changes made */
  98        u32 major_version;
  99
 100        /** incremented changed when compatible changes made,
 101         *  reset to zero when major incremented
 102         */
 103        u32 minor_version;
 104
 105        u64 app_data_addr;
 106        u64 app_data_size;
 107
 108        /** number of elements in named blocks array */
 109        u32 nb_num_blocks;
 110
 111        /** length of name array in bootmem blocks */
 112        u32 named_block_name_len;
 113
 114        /** address of named memory block descriptors */
 115        u64 named_block_array_addr;
 116};
 117
 118/* Structure that defines a single console.
 119 *
 120 * Note: when read_index == write_index, the buffer is empty.
 121 * The actual usable size of each console is console_buf_size -1;
 122 */
 123struct octeon_pci_console {
 124        u64 input_base_addr;
 125        u32 input_read_index;
 126        u32 input_write_index;
 127        u64 output_base_addr;
 128        u32 output_read_index;
 129        u32 output_write_index;
 130        u32 lock;
 131        u32 buf_size;
 132};
 133
 134/* This is the main container structure that contains all the information
 135 * about all PCI consoles.  The address of this structure is passed to various
 136 * routines that operation on PCI consoles.
 137 */
 138struct octeon_pci_console_desc {
 139        u32 major_version;
 140        u32 minor_version;
 141        u32 lock;
 142        u32 flags;
 143        u32 num_consoles;
 144        u32 pad;
 145        /* must be 64 bit aligned here... */
 146        /* Array of addresses of octeon_pci_console structures */
 147        u64 console_addr_array[0];
 148        /* Implicit storage for console_addr_array */
 149};
 150
 151/**
 152 * This macro returns the size of a member of a structure.
 153 * Logically it is the same as "sizeof(s::field)" in C++, but
 154 * C lacks the "::" operator.
 155 */
 156#define SIZEOF_FIELD(s, field) sizeof(((s *)NULL)->field)
 157
 158/**
 159 * This macro returns a member of the cvmx_bootmem_desc
 160 * structure. These members can't be directly addressed as
 161 * they might be in memory not directly reachable. In the case
 162 * where bootmem is compiled with LINUX_HOST, the structure
 163 * itself might be located on a remote Octeon. The argument
 164 * "field" is the member name of the cvmx_bootmem_desc to read.
 165 * Regardless of the type of the field, the return type is always
 166 * a u64.
 167 */
 168#define CVMX_BOOTMEM_DESC_GET_FIELD(oct, field)                              \
 169        __cvmx_bootmem_desc_get(oct, oct->bootmem_desc_addr,                 \
 170                                offsetof(struct cvmx_bootmem_desc, field),   \
 171                                SIZEOF_FIELD(struct cvmx_bootmem_desc, field))
 172
 173#define __cvmx_bootmem_lock(flags)
 174#define __cvmx_bootmem_unlock(flags)
 175
 176/**
 177 * This macro returns a member of the
 178 * cvmx_bootmem_named_block_desc structure. These members can't
 179 * be directly addressed as they might be in memory not directly
 180 * reachable. In the case where bootmem is compiled with
 181 * LINUX_HOST, the structure itself might be located on a remote
 182 * Octeon. The argument "field" is the member name of the
 183 * cvmx_bootmem_named_block_desc to read. Regardless of the type
 184 * of the field, the return type is always a u64. The "addr"
 185 * parameter is the physical address of the structure.
 186 */
 187#define CVMX_BOOTMEM_NAMED_GET_FIELD(oct, addr, field)                   \
 188        __cvmx_bootmem_desc_get(oct, addr,                               \
 189                offsetof(struct cvmx_bootmem_named_block_desc, field),   \
 190                SIZEOF_FIELD(struct cvmx_bootmem_named_block_desc, field))
 191
 192/**
 193 * This function is the implementation of the get macros defined
 194 * for individual structure members. The argument are generated
 195 * by the macros inorder to read only the needed memory.
 196 *
 197 * @param oct    Pointer to current octeon device
 198 * @param base   64bit physical address of the complete structure
 199 * @param offset Offset from the beginning of the structure to the member being
 200 *               accessed.
 201 * @param size   Size of the structure member.
 202 *
 203 * @return Value of the structure member promoted into a u64.
 204 */
 205static inline u64 __cvmx_bootmem_desc_get(struct octeon_device *oct,
 206                                          u64 base,
 207                                          u32 offset,
 208                                          u32 size)
 209{
 210        base = (1ull << 63) | (base + offset);
 211        switch (size) {
 212        case 4:
 213                return octeon_read_device_mem32(oct, base);
 214        case 8:
 215                return octeon_read_device_mem64(oct, base);
 216        default:
 217                return 0;
 218        }
 219}
 220
 221/**
 222 * This function retrieves the string name of a named block. It is
 223 * more complicated than a simple memcpy() since the named block
 224 * descriptor may not be directly accessible.
 225 *
 226 * @param addr   Physical address of the named block descriptor
 227 * @param str    String to receive the named block string name
 228 * @param len    Length of the string buffer, which must match the length
 229 *               stored in the bootmem descriptor.
 230 */
 231static void CVMX_BOOTMEM_NAMED_GET_NAME(struct octeon_device *oct,
 232                                        u64 addr,
 233                                        char *str,
 234                                        u32 len)
 235{
 236        addr += offsetof(struct cvmx_bootmem_named_block_desc, name);
 237        octeon_pci_read_core_mem(oct, addr, str, len);
 238        str[len] = 0;
 239}
 240
 241/* See header file for descriptions of functions */
 242
 243/**
 244 * Check the version information on the bootmem descriptor
 245 *
 246 * @param exact_match
 247 *               Exact major version to check against. A zero means
 248 *               check that the version supports named blocks.
 249 *
 250 * @return Zero if the version is correct. Negative if the version is
 251 *         incorrect. Failures also cause a message to be displayed.
 252 */
 253static int __cvmx_bootmem_check_version(struct octeon_device *oct,
 254                                        u32 exact_match)
 255{
 256        u32 major_version;
 257        u32 minor_version;
 258
 259        if (!oct->bootmem_desc_addr)
 260                oct->bootmem_desc_addr =
 261                        octeon_read_device_mem64(oct,
 262                                                 BOOTLOADER_PCI_READ_DESC_ADDR);
 263        major_version =
 264                (u32)CVMX_BOOTMEM_DESC_GET_FIELD(oct, major_version);
 265        minor_version =
 266                (u32)CVMX_BOOTMEM_DESC_GET_FIELD(oct, minor_version);
 267        dev_dbg(&oct->pci_dev->dev, "%s: major_version=%d\n", __func__,
 268                major_version);
 269        if ((major_version > 3) ||
 270            (exact_match && major_version != exact_match)) {
 271                dev_err(&oct->pci_dev->dev, "bootmem ver mismatch %d.%d addr:0x%llx\n",
 272                        major_version, minor_version,
 273                        CAST_ULL(oct->bootmem_desc_addr));
 274                return -1;
 275        } else {
 276                return 0;
 277        }
 278}
 279
 280static const struct cvmx_bootmem_named_block_desc
 281*__cvmx_bootmem_find_named_block_flags(struct octeon_device *oct,
 282                                        const char *name, u32 flags)
 283{
 284        struct cvmx_bootmem_named_block_desc *desc =
 285                &oct->bootmem_named_block_desc;
 286        u64 named_addr = cvmx_bootmem_phy_named_block_find(oct, name, flags);
 287
 288        if (named_addr) {
 289                desc->base_addr = CVMX_BOOTMEM_NAMED_GET_FIELD(oct, named_addr,
 290                                                               base_addr);
 291                desc->size =
 292                        CVMX_BOOTMEM_NAMED_GET_FIELD(oct, named_addr, size);
 293                strncpy(desc->name, name, sizeof(desc->name));
 294                desc->name[sizeof(desc->name) - 1] = 0;
 295                return &oct->bootmem_named_block_desc;
 296        } else {
 297                return NULL;
 298        }
 299}
 300
 301static u64 cvmx_bootmem_phy_named_block_find(struct octeon_device *oct,
 302                                             const char *name,
 303                                             u32 flags)
 304{
 305        u64 result = 0;
 306
 307        __cvmx_bootmem_lock(flags);
 308        if (!__cvmx_bootmem_check_version(oct, 3)) {
 309                u32 i;
 310                u64 named_block_array_addr =
 311                        CVMX_BOOTMEM_DESC_GET_FIELD(oct,
 312                                                    named_block_array_addr);
 313                u32 num_blocks = (u32)
 314                        CVMX_BOOTMEM_DESC_GET_FIELD(oct, nb_num_blocks);
 315                u32 name_length = (u32)
 316                        CVMX_BOOTMEM_DESC_GET_FIELD(oct, named_block_name_len);
 317                u64 named_addr = named_block_array_addr;
 318
 319                for (i = 0; i < num_blocks; i++) {
 320                        u64 named_size =
 321                                CVMX_BOOTMEM_NAMED_GET_FIELD(oct, named_addr,
 322                                                             size);
 323                        if (name && named_size) {
 324                                char *name_tmp =
 325                                        kmalloc(name_length + 1, GFP_KERNEL);
 326                                CVMX_BOOTMEM_NAMED_GET_NAME(oct, named_addr,
 327                                                            name_tmp,
 328                                                            name_length);
 329                                if (!strncmp(name, name_tmp, name_length)) {
 330                                        result = named_addr;
 331                                        kfree(name_tmp);
 332                                        break;
 333                                }
 334                                kfree(name_tmp);
 335                        } else if (!name && !named_size) {
 336                                result = named_addr;
 337                                break;
 338                        }
 339
 340                        named_addr +=
 341                                sizeof(struct cvmx_bootmem_named_block_desc);
 342                }
 343        }
 344        __cvmx_bootmem_unlock(flags);
 345        return result;
 346}
 347
 348/**
 349 * Find a named block on the remote Octeon
 350 *
 351 * @param name      Name of block to find
 352 * @param base_addr Address the block is at (OUTPUT)
 353 * @param size      The size of the block (OUTPUT)
 354 *
 355 * @return Zero on success, One on failure.
 356 */
 357static int octeon_named_block_find(struct octeon_device *oct, const char *name,
 358                                   u64 *base_addr, u64 *size)
 359{
 360        const struct cvmx_bootmem_named_block_desc *named_block;
 361
 362        octeon_remote_lock();
 363        named_block = __cvmx_bootmem_find_named_block_flags(oct, name, 0);
 364        octeon_remote_unlock();
 365        if (named_block) {
 366                *base_addr = named_block->base_addr;
 367                *size = named_block->size;
 368                return 0;
 369        }
 370        return 1;
 371}
 372
 373static void octeon_remote_lock(void)
 374{
 375        /* fill this in if any sharing is needed */
 376}
 377
 378static void octeon_remote_unlock(void)
 379{
 380        /* fill this in if any sharing is needed */
 381}
 382
 383int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str,
 384                            u32 wait_hundredths)
 385{
 386        u32 len = strlen(cmd_str);
 387
 388        dev_dbg(&oct->pci_dev->dev, "sending \"%s\" to bootloader\n", cmd_str);
 389
 390        if (len > BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN - 1) {
 391                dev_err(&oct->pci_dev->dev, "Command string too long, max length is: %d\n",
 392                        BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN - 1);
 393                return -1;
 394        }
 395
 396        if (octeon_wait_for_bootloader(oct, wait_hundredths) != 0) {
 397                dev_err(&oct->pci_dev->dev, "Bootloader not ready for command.\n");
 398                return -1;
 399        }
 400
 401        /* Write command to bootloader */
 402        octeon_remote_lock();
 403        octeon_pci_write_core_mem(oct, BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR,
 404                                  (u8 *)cmd_str, len);
 405        octeon_write_device_mem32(oct, BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR,
 406                                  len);
 407        octeon_write_device_mem32(oct, BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR,
 408                                  OCTEON_PCI_IO_BUF_OWNER_OCTEON);
 409
 410        /* Bootloader should accept command very quickly
 411         * if it really was ready
 412         */
 413        if (octeon_wait_for_bootloader(oct, 200) != 0) {
 414                octeon_remote_unlock();
 415                dev_err(&oct->pci_dev->dev, "Bootloader did not accept command.\n");
 416                return -1;
 417        }
 418        octeon_remote_unlock();
 419        return 0;
 420}
 421
 422int octeon_wait_for_bootloader(struct octeon_device *oct,
 423                               u32 wait_time_hundredths)
 424{
 425        dev_dbg(&oct->pci_dev->dev, "waiting %d0 ms for bootloader\n",
 426                wait_time_hundredths);
 427
 428        if (octeon_mem_access_ok(oct))
 429                return -1;
 430
 431        while (wait_time_hundredths > 0 &&
 432               octeon_read_device_mem32(oct,
 433                                        BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR)
 434               != OCTEON_PCI_IO_BUF_OWNER_HOST) {
 435                if (--wait_time_hundredths <= 0)
 436                        return -1;
 437                schedule_timeout_uninterruptible(HZ / 100);
 438        }
 439        return 0;
 440}
 441
 442static void octeon_console_handle_result(struct octeon_device *oct,
 443                                         size_t console_num,
 444                                         char *buffer, s32 bytes_read)
 445{
 446        struct octeon_console *console;
 447
 448        console = &oct->console[console_num];
 449
 450        console->waiting = 0;
 451}
 452
 453static char console_buffer[OCTEON_CONSOLE_MAX_READ_BYTES];
 454
 455static void output_console_line(struct octeon_device *oct,
 456                                struct octeon_console *console,
 457                                size_t console_num,
 458                                char *console_buffer,
 459                                s32 bytes_read)
 460{
 461        char *line;
 462        s32 i;
 463
 464        line = console_buffer;
 465        for (i = 0; i < bytes_read; i++) {
 466                /* Output a line at a time, prefixed */
 467                if (console_buffer[i] == '\n') {
 468                        console_buffer[i] = '\0';
 469                        if (console->leftover[0]) {
 470                                dev_info(&oct->pci_dev->dev, "%lu: %s%s\n",
 471                                         console_num, console->leftover,
 472                                         line);
 473                                console->leftover[0] = '\0';
 474                        } else {
 475                                dev_info(&oct->pci_dev->dev, "%lu: %s\n",
 476                                         console_num, line);
 477                        }
 478                        line = &console_buffer[i + 1];
 479                }
 480        }
 481
 482        /* Save off any leftovers */
 483        if (line != &console_buffer[bytes_read]) {
 484                console_buffer[bytes_read] = '\0';
 485                strcpy(console->leftover, line);
 486        }
 487}
 488
 489static void check_console(struct work_struct *work)
 490{
 491        s32 bytes_read, tries, total_read;
 492        struct octeon_console *console;
 493        struct cavium_wk *wk = (struct cavium_wk *)work;
 494        struct octeon_device *oct = (struct octeon_device *)wk->ctxptr;
 495        size_t console_num = wk->ctxul;
 496        u32 delay;
 497
 498        console = &oct->console[console_num];
 499        tries = 0;
 500        total_read = 0;
 501
 502        do {
 503                /* Take console output regardless of whether it will
 504                 * be logged
 505                 */
 506                bytes_read =
 507                        octeon_console_read(oct, console_num, console_buffer,
 508                                            sizeof(console_buffer) - 1, 0);
 509                if (bytes_read > 0) {
 510                        total_read += bytes_read;
 511                        if (console->waiting) {
 512                                octeon_console_handle_result(oct, console_num,
 513                                                             console_buffer,
 514                                                             bytes_read);
 515                        }
 516                        if (octeon_console_debug_enabled(console_num)) {
 517                                output_console_line(oct, console, console_num,
 518                                                    console_buffer, bytes_read);
 519                        }
 520                } else if (bytes_read < 0) {
 521                        dev_err(&oct->pci_dev->dev, "Error reading console %lu, ret=%d\n",
 522                                console_num, bytes_read);
 523                }
 524
 525                tries++;
 526        } while ((bytes_read > 0) && (tries < 16));
 527
 528        /* If nothing is read after polling the console,
 529         * output any leftovers if any
 530         */
 531        if (octeon_console_debug_enabled(console_num) &&
 532            (total_read == 0) && (console->leftover[0])) {
 533                dev_info(&oct->pci_dev->dev, "%lu: %s\n",
 534                         console_num, console->leftover);
 535                console->leftover[0] = '\0';
 536        }
 537
 538        delay = OCTEON_CONSOLE_POLL_INTERVAL_MS;
 539
 540        schedule_delayed_work(&wk->work, msecs_to_jiffies(delay));
 541}
 542
 543int octeon_init_consoles(struct octeon_device *oct)
 544{
 545        int ret = 0;
 546        u64 addr, size;
 547
 548        ret = octeon_mem_access_ok(oct);
 549        if (ret) {
 550                dev_err(&oct->pci_dev->dev, "Memory access not okay'\n");
 551                return ret;
 552        }
 553
 554        ret = octeon_named_block_find(oct, OCTEON_PCI_CONSOLE_BLOCK_NAME, &addr,
 555                                      &size);
 556        if (ret) {
 557                dev_err(&oct->pci_dev->dev, "Could not find console '%s'\n",
 558                        OCTEON_PCI_CONSOLE_BLOCK_NAME);
 559                return ret;
 560        }
 561
 562        /* num_consoles > 0, is an indication that the consoles
 563         * are accessible
 564         */
 565        oct->num_consoles = octeon_read_device_mem32(oct,
 566                addr + offsetof(struct octeon_pci_console_desc,
 567                        num_consoles));
 568        oct->console_desc_addr = addr;
 569
 570        dev_dbg(&oct->pci_dev->dev, "Initialized consoles. %d available\n",
 571                oct->num_consoles);
 572
 573        return ret;
 574}
 575
 576int octeon_add_console(struct octeon_device *oct, u32 console_num)
 577{
 578        int ret = 0;
 579        u32 delay;
 580        u64 coreaddr;
 581        struct delayed_work *work;
 582        struct octeon_console *console;
 583
 584        if (console_num >= oct->num_consoles) {
 585                dev_err(&oct->pci_dev->dev,
 586                        "trying to read from console number %d when only 0 to %d exist\n",
 587                        console_num, oct->num_consoles);
 588        } else {
 589                console = &oct->console[console_num];
 590
 591                console->waiting = 0;
 592
 593                coreaddr = oct->console_desc_addr + console_num * 8 +
 594                        offsetof(struct octeon_pci_console_desc,
 595                                 console_addr_array);
 596                console->addr = octeon_read_device_mem64(oct, coreaddr);
 597                coreaddr = console->addr + offsetof(struct octeon_pci_console,
 598                                                    buf_size);
 599                console->buffer_size = octeon_read_device_mem32(oct, coreaddr);
 600                coreaddr = console->addr + offsetof(struct octeon_pci_console,
 601                                                    input_base_addr);
 602                console->input_base_addr =
 603                        octeon_read_device_mem64(oct, coreaddr);
 604                coreaddr = console->addr + offsetof(struct octeon_pci_console,
 605                                                    output_base_addr);
 606                console->output_base_addr =
 607                        octeon_read_device_mem64(oct, coreaddr);
 608                console->leftover[0] = '\0';
 609
 610                work = &oct->console_poll_work[console_num].work;
 611
 612                INIT_DELAYED_WORK(work, check_console);
 613                oct->console_poll_work[console_num].ctxptr = (void *)oct;
 614                oct->console_poll_work[console_num].ctxul = console_num;
 615                delay = OCTEON_CONSOLE_POLL_INTERVAL_MS;
 616                schedule_delayed_work(work, msecs_to_jiffies(delay));
 617
 618                if (octeon_console_debug_enabled(console_num)) {
 619                        ret = octeon_console_send_cmd(oct,
 620                                                      "setenv pci_console_active 1",
 621                                                      2000);
 622                }
 623
 624                console->active = 1;
 625        }
 626
 627        return ret;
 628}
 629
 630/**
 631 * Removes all consoles
 632 *
 633 * @param oct         octeon device
 634 */
 635void octeon_remove_consoles(struct octeon_device *oct)
 636{
 637        u32 i;
 638        struct octeon_console *console;
 639
 640        for (i = 0; i < oct->num_consoles; i++) {
 641                console = &oct->console[i];
 642
 643                if (!console->active)
 644                        continue;
 645
 646                cancel_delayed_work_sync(&oct->console_poll_work[i].
 647                                                work);
 648                console->addr = 0;
 649                console->buffer_size = 0;
 650                console->input_base_addr = 0;
 651                console->output_base_addr = 0;
 652        }
 653
 654        oct->num_consoles = 0;
 655}
 656
 657static inline int octeon_console_free_bytes(u32 buffer_size,
 658                                            u32 wr_idx,
 659                                            u32 rd_idx)
 660{
 661        if (rd_idx >= buffer_size || wr_idx >= buffer_size)
 662                return -1;
 663
 664        return ((buffer_size - 1) - (wr_idx - rd_idx)) % buffer_size;
 665}
 666
 667static inline int octeon_console_avail_bytes(u32 buffer_size,
 668                                             u32 wr_idx,
 669                                             u32 rd_idx)
 670{
 671        if (rd_idx >= buffer_size || wr_idx >= buffer_size)
 672                return -1;
 673
 674        return buffer_size - 1 -
 675               octeon_console_free_bytes(buffer_size, wr_idx, rd_idx);
 676}
 677
 678int octeon_console_read(struct octeon_device *oct, u32 console_num,
 679                        char *buffer, u32 buf_size, u32 flags)
 680{
 681        int bytes_to_read;
 682        u32 rd_idx, wr_idx;
 683        struct octeon_console *console;
 684
 685        if (console_num >= oct->num_consoles) {
 686                dev_err(&oct->pci_dev->dev, "Attempted to read from disabled console %d\n",
 687                        console_num);
 688                return 0;
 689        }
 690
 691        console = &oct->console[console_num];
 692
 693        /* Check to see if any data is available.
 694         * Maybe optimize this with 64-bit read.
 695         */
 696        rd_idx = octeon_read_device_mem32(oct, console->addr +
 697                offsetof(struct octeon_pci_console, output_read_index));
 698        wr_idx = octeon_read_device_mem32(oct, console->addr +
 699                offsetof(struct octeon_pci_console, output_write_index));
 700
 701        bytes_to_read = octeon_console_avail_bytes(console->buffer_size,
 702                                                   wr_idx, rd_idx);
 703        if (bytes_to_read <= 0)
 704                return bytes_to_read;
 705
 706        bytes_to_read = MIN(bytes_to_read, (s32)buf_size);
 707
 708        /* Check to see if what we want to read is not contiguous, and limit
 709         * ourselves to the contiguous block
 710         */
 711        if (rd_idx + bytes_to_read >= console->buffer_size)
 712                bytes_to_read = console->buffer_size - rd_idx;
 713
 714        octeon_pci_read_core_mem(oct, console->output_base_addr + rd_idx,
 715                                 buffer, bytes_to_read);
 716        octeon_write_device_mem32(oct, console->addr +
 717                                  offsetof(struct octeon_pci_console,
 718                                           output_read_index),
 719                                  (rd_idx + bytes_to_read) %
 720                                  console->buffer_size);
 721
 722        return bytes_to_read;
 723}
 724