linux/drivers/net/wireless/st/cw1200/hwio.h
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   1/*
   2 * Low-level API for mac80211 ST-Ericsson CW1200 drivers
   3 *
   4 * Copyright (c) 2010, ST-Ericsson
   5 * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
   6 *
   7 * Based on:
   8 * ST-Ericsson UMAC CW1200 driver which is
   9 * Copyright (c) 2010, ST-Ericsson
  10 * Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License version 2 as
  14 * published by the Free Software Foundation.
  15 */
  16
  17#ifndef CW1200_HWIO_H_INCLUDED
  18#define CW1200_HWIO_H_INCLUDED
  19
  20/* extern */ struct cw1200_common;
  21
  22#define CW1200_CUT_11_ID_STR            (0x302E3830)
  23#define CW1200_CUT_22_ID_STR1           (0x302e3132)
  24#define CW1200_CUT_22_ID_STR2           (0x32302e30)
  25#define CW1200_CUT_22_ID_STR3           (0x3335)
  26#define CW1200_CUT_ID_ADDR              (0xFFF17F90)
  27#define CW1200_CUT2_ID_ADDR             (0xFFF1FF90)
  28
  29/* Download control area */
  30/* boot loader start address in SRAM */
  31#define DOWNLOAD_BOOT_LOADER_OFFSET     (0x00000000)
  32/* 32K, 0x4000 to 0xDFFF */
  33#define DOWNLOAD_FIFO_OFFSET            (0x00004000)
  34/* 32K */
  35#define DOWNLOAD_FIFO_SIZE              (0x00008000)
  36/* 128 bytes, 0xFF80 to 0xFFFF */
  37#define DOWNLOAD_CTRL_OFFSET            (0x0000FF80)
  38#define DOWNLOAD_CTRL_DATA_DWORDS       (32-6)
  39
  40struct download_cntl_t {
  41        /* size of whole firmware file (including Cheksum), host init */
  42        u32 image_size;
  43        /* downloading flags */
  44        u32 flags;
  45        /* No. of bytes put into the download, init & updated by host */
  46        u32 put;
  47        /* last traced program counter, last ARM reg_pc */
  48        u32 trace_pc;
  49        /* No. of bytes read from the download, host init, device updates */
  50        u32 get;
  51        /* r0, boot losader status, host init to pending, device updates */
  52        u32 status;
  53        /* Extra debug info, r1 to r14 if status=r0=DOWNLOAD_EXCEPTION */
  54        u32 debug_data[DOWNLOAD_CTRL_DATA_DWORDS];
  55};
  56
  57#define DOWNLOAD_IMAGE_SIZE_REG         \
  58        (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, image_size))
  59#define DOWNLOAD_FLAGS_REG              \
  60        (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, flags))
  61#define DOWNLOAD_PUT_REG                \
  62        (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, put))
  63#define DOWNLOAD_TRACE_PC_REG           \
  64        (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, trace_pc))
  65#define DOWNLOAD_GET_REG                \
  66        (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, get))
  67#define DOWNLOAD_STATUS_REG             \
  68        (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, status))
  69#define DOWNLOAD_DEBUG_DATA_REG         \
  70        (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, debug_data))
  71#define DOWNLOAD_DEBUG_DATA_LEN         (108)
  72
  73#define DOWNLOAD_BLOCK_SIZE             (1024)
  74
  75/* For boot loader detection */
  76#define DOWNLOAD_ARE_YOU_HERE           (0x87654321)
  77#define DOWNLOAD_I_AM_HERE              (0x12345678)
  78
  79/* Download error code */
  80#define DOWNLOAD_PENDING                (0xFFFFFFFF)
  81#define DOWNLOAD_SUCCESS                (0)
  82#define DOWNLOAD_EXCEPTION              (1)
  83#define DOWNLOAD_ERR_MEM_1              (2)
  84#define DOWNLOAD_ERR_MEM_2              (3)
  85#define DOWNLOAD_ERR_SOFTWARE           (4)
  86#define DOWNLOAD_ERR_FILE_SIZE          (5)
  87#define DOWNLOAD_ERR_CHECKSUM           (6)
  88#define DOWNLOAD_ERR_OVERFLOW           (7)
  89#define DOWNLOAD_ERR_IMAGE              (8)
  90#define DOWNLOAD_ERR_HOST               (9)
  91#define DOWNLOAD_ERR_ABORT              (10)
  92
  93
  94#define SYS_BASE_ADDR_SILICON           (0)
  95#define PAC_BASE_ADDRESS_SILICON        (SYS_BASE_ADDR_SILICON + 0x09000000)
  96#define PAC_SHARED_MEMORY_SILICON       (PAC_BASE_ADDRESS_SILICON)
  97
  98#define CW1200_APB(addr)                (PAC_SHARED_MEMORY_SILICON + (addr))
  99
 100/* Device register definitions */
 101
 102/* WBF - SPI Register Addresses */
 103#define ST90TDS_ADDR_ID_BASE            (0x0000)
 104/* 16/32 bits */
 105#define ST90TDS_CONFIG_REG_ID           (0x0000)
 106/* 16/32 bits */
 107#define ST90TDS_CONTROL_REG_ID          (0x0001)
 108/* 16 bits, Q mode W/R */
 109#define ST90TDS_IN_OUT_QUEUE_REG_ID     (0x0002)
 110/* 32 bits, AHB bus R/W */
 111#define ST90TDS_AHB_DPORT_REG_ID        (0x0003)
 112/* 16/32 bits */
 113#define ST90TDS_SRAM_BASE_ADDR_REG_ID   (0x0004)
 114/* 32 bits, APB bus R/W */
 115#define ST90TDS_SRAM_DPORT_REG_ID       (0x0005)
 116/* 32 bits, t_settle/general */
 117#define ST90TDS_TSET_GEN_R_W_REG_ID     (0x0006)
 118/* 16 bits, Q mode read, no length */
 119#define ST90TDS_FRAME_OUT_REG_ID        (0x0007)
 120#define ST90TDS_ADDR_ID_MAX             (ST90TDS_FRAME_OUT_REG_ID)
 121
 122/* WBF - Control register bit set */
 123/* next o/p length, bit 11 to 0 */
 124#define ST90TDS_CONT_NEXT_LEN_MASK      (0x0FFF)
 125#define ST90TDS_CONT_WUP_BIT            (BIT(12))
 126#define ST90TDS_CONT_RDY_BIT            (BIT(13))
 127#define ST90TDS_CONT_IRQ_ENABLE         (BIT(14))
 128#define ST90TDS_CONT_RDY_ENABLE         (BIT(15))
 129#define ST90TDS_CONT_IRQ_RDY_ENABLE     (BIT(14)|BIT(15))
 130
 131/* SPI Config register bit set */
 132#define ST90TDS_CONFIG_FRAME_BIT        (BIT(2))
 133#define ST90TDS_CONFIG_WORD_MODE_BITS   (BIT(3)|BIT(4))
 134#define ST90TDS_CONFIG_WORD_MODE_1      (BIT(3))
 135#define ST90TDS_CONFIG_WORD_MODE_2      (BIT(4))
 136#define ST90TDS_CONFIG_ERROR_0_BIT      (BIT(5))
 137#define ST90TDS_CONFIG_ERROR_1_BIT      (BIT(6))
 138#define ST90TDS_CONFIG_ERROR_2_BIT      (BIT(7))
 139/* TBD: Sure??? */
 140#define ST90TDS_CONFIG_CSN_FRAME_BIT    (BIT(7))
 141#define ST90TDS_CONFIG_ERROR_3_BIT      (BIT(8))
 142#define ST90TDS_CONFIG_ERROR_4_BIT      (BIT(9))
 143/* QueueM */
 144#define ST90TDS_CONFIG_ACCESS_MODE_BIT  (BIT(10))
 145/* AHB bus */
 146#define ST90TDS_CONFIG_AHB_PRFETCH_BIT  (BIT(11))
 147#define ST90TDS_CONFIG_CPU_CLK_DIS_BIT  (BIT(12))
 148/* APB bus */
 149#define ST90TDS_CONFIG_PRFETCH_BIT      (BIT(13))
 150/* cpu reset */
 151#define ST90TDS_CONFIG_CPU_RESET_BIT    (BIT(14))
 152#define ST90TDS_CONFIG_CLEAR_INT_BIT    (BIT(15))
 153
 154/* For CW1200 the IRQ Enable and Ready Bits are in CONFIG register */
 155#define ST90TDS_CONF_IRQ_ENABLE         (BIT(16))
 156#define ST90TDS_CONF_RDY_ENABLE         (BIT(17))
 157#define ST90TDS_CONF_IRQ_RDY_ENABLE     (BIT(16)|BIT(17))
 158
 159int cw1200_data_read(struct cw1200_common *priv,
 160                     void *buf, size_t buf_len);
 161int cw1200_data_write(struct cw1200_common *priv,
 162                      const void *buf, size_t buf_len);
 163
 164int cw1200_reg_read(struct cw1200_common *priv, u16 addr,
 165                    void *buf, size_t buf_len);
 166int cw1200_reg_write(struct cw1200_common *priv, u16 addr,
 167                     const void *buf, size_t buf_len);
 168
 169static inline int cw1200_reg_read_16(struct cw1200_common *priv,
 170                                     u16 addr, u16 *val)
 171{
 172        __le32 tmp;
 173        int i;
 174        i = cw1200_reg_read(priv, addr, &tmp, sizeof(tmp));
 175        *val = le32_to_cpu(tmp) & 0xfffff;
 176        return i;
 177}
 178
 179static inline int cw1200_reg_write_16(struct cw1200_common *priv,
 180                                      u16 addr, u16 val)
 181{
 182        __le32 tmp = cpu_to_le32((u32)val);
 183        return cw1200_reg_write(priv, addr, &tmp, sizeof(tmp));
 184}
 185
 186static inline int cw1200_reg_read_32(struct cw1200_common *priv,
 187                                     u16 addr, u32 *val)
 188{
 189        __le32 tmp;
 190        int i = cw1200_reg_read(priv, addr, &tmp, sizeof(tmp));
 191        *val = le32_to_cpu(tmp);
 192        return i;
 193}
 194
 195static inline int cw1200_reg_write_32(struct cw1200_common *priv,
 196                                      u16 addr, u32 val)
 197{
 198        __le32 tmp = cpu_to_le32(val);
 199        return cw1200_reg_write(priv, addr, &tmp, sizeof(val));
 200}
 201
 202int cw1200_indirect_read(struct cw1200_common *priv, u32 addr, void *buf,
 203                         size_t buf_len, u32 prefetch, u16 port_addr);
 204int cw1200_apb_write(struct cw1200_common *priv, u32 addr, const void *buf,
 205                     size_t buf_len);
 206
 207static inline int cw1200_apb_read(struct cw1200_common *priv, u32 addr,
 208                                  void *buf, size_t buf_len)
 209{
 210        return cw1200_indirect_read(priv, addr, buf, buf_len,
 211                                    ST90TDS_CONFIG_PRFETCH_BIT,
 212                                    ST90TDS_SRAM_DPORT_REG_ID);
 213}
 214
 215static inline int cw1200_ahb_read(struct cw1200_common *priv, u32 addr,
 216                                  void *buf, size_t buf_len)
 217{
 218        return cw1200_indirect_read(priv, addr, buf, buf_len,
 219                                    ST90TDS_CONFIG_AHB_PRFETCH_BIT,
 220                                    ST90TDS_AHB_DPORT_REG_ID);
 221}
 222
 223static inline int cw1200_apb_read_32(struct cw1200_common *priv,
 224                                     u32 addr, u32 *val)
 225{
 226        __le32 tmp;
 227        int i = cw1200_apb_read(priv, addr, &tmp, sizeof(tmp));
 228        *val = le32_to_cpu(tmp);
 229        return i;
 230}
 231
 232static inline int cw1200_apb_write_32(struct cw1200_common *priv,
 233                                      u32 addr, u32 val)
 234{
 235        __le32 tmp = cpu_to_le32(val);
 236        return cw1200_apb_write(priv, addr, &tmp, sizeof(val));
 237}
 238static inline int cw1200_ahb_read_32(struct cw1200_common *priv,
 239                                     u32 addr, u32 *val)
 240{
 241        __le32 tmp;
 242        int i = cw1200_ahb_read(priv, addr, &tmp, sizeof(tmp));
 243        *val = le32_to_cpu(tmp);
 244        return i;
 245}
 246
 247#endif /* CW1200_HWIO_H_INCLUDED */
 248
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.