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22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/idr.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/kthread.h>
29#include <linux/pci.h>
30#include <linux/spinlock.h>
31#include <linux/ctype.h>
32#include <linux/aer.h>
33#include <linux/slab.h>
34#include <linux/firmware.h>
35#include <linux/miscdevice.h>
36#include <linux/percpu.h>
37
38#include <scsi/scsi.h>
39#include <scsi/scsi_device.h>
40#include <scsi/scsi_host.h>
41#include <scsi/scsi_transport_fc.h>
42
43#include "lpfc_hw4.h"
44#include "lpfc_hw.h"
45#include "lpfc_sli.h"
46#include "lpfc_sli4.h"
47#include "lpfc_nl.h"
48#include "lpfc_disc.h"
49#include "lpfc_scsi.h"
50#include "lpfc.h"
51#include "lpfc_logmsg.h"
52#include "lpfc_crtn.h"
53#include "lpfc_vport.h"
54#include "lpfc_version.h"
55
56char *_dump_buf_data;
57unsigned long _dump_buf_data_order;
58char *_dump_buf_dif;
59unsigned long _dump_buf_dif_order;
60spinlock_t _dump_buf_lock;
61
62
63uint16_t *lpfc_used_cpu;
64uint32_t lpfc_present_cpu;
65
66static void lpfc_get_hba_model_desc(struct lpfc_hba *, uint8_t *, uint8_t *);
67static int lpfc_post_rcv_buf(struct lpfc_hba *);
68static int lpfc_sli4_queue_verify(struct lpfc_hba *);
69static int lpfc_create_bootstrap_mbox(struct lpfc_hba *);
70static int lpfc_setup_endian_order(struct lpfc_hba *);
71static void lpfc_destroy_bootstrap_mbox(struct lpfc_hba *);
72static void lpfc_free_els_sgl_list(struct lpfc_hba *);
73static void lpfc_init_sgl_list(struct lpfc_hba *);
74static int lpfc_init_active_sgl_array(struct lpfc_hba *);
75static void lpfc_free_active_sgl(struct lpfc_hba *);
76static int lpfc_hba_down_post_s3(struct lpfc_hba *phba);
77static int lpfc_hba_down_post_s4(struct lpfc_hba *phba);
78static int lpfc_sli4_cq_event_pool_create(struct lpfc_hba *);
79static void lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *);
80static void lpfc_sli4_cq_event_release_all(struct lpfc_hba *);
81static void lpfc_sli4_disable_intr(struct lpfc_hba *);
82static uint32_t lpfc_sli4_enable_intr(struct lpfc_hba *, uint32_t);
83static void lpfc_sli4_oas_verify(struct lpfc_hba *phba);
84
85static struct scsi_transport_template *lpfc_transport_template = NULL;
86static struct scsi_transport_template *lpfc_vport_transport_template = NULL;
87static DEFINE_IDR(lpfc_hba_index);
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103int
104lpfc_config_port_prep(struct lpfc_hba *phba)
105{
106 lpfc_vpd_t *vp = &phba->vpd;
107 int i = 0, rc;
108 LPFC_MBOXQ_t *pmb;
109 MAILBOX_t *mb;
110 char *lpfc_vpd_data = NULL;
111 uint16_t offset = 0;
112 static char licensed[56] =
113 "key unlock for use with gnu public licensed code only\0";
114 static int init_key = 1;
115
116 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
117 if (!pmb) {
118 phba->link_state = LPFC_HBA_ERROR;
119 return -ENOMEM;
120 }
121
122 mb = &pmb->u.mb;
123 phba->link_state = LPFC_INIT_MBX_CMDS;
124
125 if (lpfc_is_LC_HBA(phba->pcidev->device)) {
126 if (init_key) {
127 uint32_t *ptext = (uint32_t *) licensed;
128
129 for (i = 0; i < 56; i += sizeof (uint32_t), ptext++)
130 *ptext = cpu_to_be32(*ptext);
131 init_key = 0;
132 }
133
134 lpfc_read_nv(phba, pmb);
135 memset((char*)mb->un.varRDnvp.rsvd3, 0,
136 sizeof (mb->un.varRDnvp.rsvd3));
137 memcpy((char*)mb->un.varRDnvp.rsvd3, licensed,
138 sizeof (licensed));
139
140 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
141
142 if (rc != MBX_SUCCESS) {
143 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
144 "0324 Config Port initialization "
145 "error, mbxCmd x%x READ_NVPARM, "
146 "mbxStatus x%x\n",
147 mb->mbxCommand, mb->mbxStatus);
148 mempool_free(pmb, phba->mbox_mem_pool);
149 return -ERESTART;
150 }
151 memcpy(phba->wwnn, (char *)mb->un.varRDnvp.nodename,
152 sizeof(phba->wwnn));
153 memcpy(phba->wwpn, (char *)mb->un.varRDnvp.portname,
154 sizeof(phba->wwpn));
155 }
156
157 phba->sli3_options = 0x0;
158
159
160 lpfc_read_rev(phba, pmb);
161 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
162 if (rc != MBX_SUCCESS) {
163 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
164 "0439 Adapter failed to init, mbxCmd x%x "
165 "READ_REV, mbxStatus x%x\n",
166 mb->mbxCommand, mb->mbxStatus);
167 mempool_free( pmb, phba->mbox_mem_pool);
168 return -ERESTART;
169 }
170
171
172
173
174
175
176 if (mb->un.varRdRev.rr == 0) {
177 vp->rev.rBit = 0;
178 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
179 "0440 Adapter failed to init, READ_REV has "
180 "missing revision information.\n");
181 mempool_free(pmb, phba->mbox_mem_pool);
182 return -ERESTART;
183 }
184
185 if (phba->sli_rev == 3 && !mb->un.varRdRev.v3rsp) {
186 mempool_free(pmb, phba->mbox_mem_pool);
187 return -EINVAL;
188 }
189
190
191 vp->rev.rBit = 1;
192 memcpy(&vp->sli3Feat, &mb->un.varRdRev.sli3Feat, sizeof(uint32_t));
193 vp->rev.sli1FwRev = mb->un.varRdRev.sli1FwRev;
194 memcpy(vp->rev.sli1FwName, (char*) mb->un.varRdRev.sli1FwName, 16);
195 vp->rev.sli2FwRev = mb->un.varRdRev.sli2FwRev;
196 memcpy(vp->rev.sli2FwName, (char *) mb->un.varRdRev.sli2FwName, 16);
197 vp->rev.biuRev = mb->un.varRdRev.biuRev;
198 vp->rev.smRev = mb->un.varRdRev.smRev;
199 vp->rev.smFwRev = mb->un.varRdRev.un.smFwRev;
200 vp->rev.endecRev = mb->un.varRdRev.endecRev;
201 vp->rev.fcphHigh = mb->un.varRdRev.fcphHigh;
202 vp->rev.fcphLow = mb->un.varRdRev.fcphLow;
203 vp->rev.feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
204 vp->rev.feaLevelLow = mb->un.varRdRev.feaLevelLow;
205 vp->rev.postKernRev = mb->un.varRdRev.postKernRev;
206 vp->rev.opFwRev = mb->un.varRdRev.opFwRev;
207
208
209
210
211
212 if (vp->rev.feaLevelHigh < 9)
213 phba->sli3_options |= LPFC_SLI3_VPORT_TEARDOWN;
214
215 if (lpfc_is_LC_HBA(phba->pcidev->device))
216 memcpy(phba->RandomData, (char *)&mb->un.varWords[24],
217 sizeof (phba->RandomData));
218
219
220 lpfc_vpd_data = kmalloc(DMP_VPD_SIZE, GFP_KERNEL);
221 if (!lpfc_vpd_data)
222 goto out_free_mbox;
223 do {
224 lpfc_dump_mem(phba, pmb, offset, DMP_REGION_VPD);
225 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
226
227 if (rc != MBX_SUCCESS) {
228 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
229 "0441 VPD not present on adapter, "
230 "mbxCmd x%x DUMP VPD, mbxStatus x%x\n",
231 mb->mbxCommand, mb->mbxStatus);
232 mb->un.varDmp.word_cnt = 0;
233 }
234
235
236
237 if (mb->un.varDmp.word_cnt == 0)
238 break;
239 if (mb->un.varDmp.word_cnt > DMP_VPD_SIZE - offset)
240 mb->un.varDmp.word_cnt = DMP_VPD_SIZE - offset;
241 lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,
242 lpfc_vpd_data + offset,
243 mb->un.varDmp.word_cnt);
244 offset += mb->un.varDmp.word_cnt;
245 } while (mb->un.varDmp.word_cnt && offset < DMP_VPD_SIZE);
246 lpfc_parse_vpd(phba, lpfc_vpd_data, offset);
247
248 kfree(lpfc_vpd_data);
249out_free_mbox:
250 mempool_free(pmb, phba->mbox_mem_pool);
251 return 0;
252}
253
254
255
256
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259
260
261
262
263
264static void
265lpfc_config_async_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
266{
267 if (pmboxq->u.mb.mbxStatus == MBX_SUCCESS)
268 phba->temp_sensor_support = 1;
269 else
270 phba->temp_sensor_support = 0;
271 mempool_free(pmboxq, phba->mbox_mem_pool);
272 return;
273}
274
275
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278
279
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281
282
283
284
285static void
286lpfc_dump_wakeup_param_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq)
287{
288 struct prog_id *prg;
289 uint32_t prog_id_word;
290 char dist = ' ';
291
292 char dist_char[] = "nabx";
293
294 if (pmboxq->u.mb.mbxStatus != MBX_SUCCESS) {
295 mempool_free(pmboxq, phba->mbox_mem_pool);
296 return;
297 }
298
299 prg = (struct prog_id *) &prog_id_word;
300
301
302 prog_id_word = pmboxq->u.mb.un.varWords[7];
303
304
305 if (prg->dist < 4)
306 dist = dist_char[prg->dist];
307
308 if ((prg->dist == 3) && (prg->num == 0))
309 snprintf(phba->OptionROMVersion, 32, "%d.%d%d",
310 prg->ver, prg->rev, prg->lev);
311 else
312 snprintf(phba->OptionROMVersion, 32, "%d.%d%d%c%d",
313 prg->ver, prg->rev, prg->lev,
314 dist, prg->num);
315 mempool_free(pmboxq, phba->mbox_mem_pool);
316 return;
317}
318
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325
326
327
328void
329lpfc_update_vport_wwn(struct lpfc_vport *vport)
330{
331
332 if (vport->phba->cfg_soft_wwnn)
333 u64_to_wwn(vport->phba->cfg_soft_wwnn,
334 vport->fc_sparam.nodeName.u.wwn);
335 if (vport->phba->cfg_soft_wwpn)
336 u64_to_wwn(vport->phba->cfg_soft_wwpn,
337 vport->fc_sparam.portName.u.wwn);
338
339
340
341
342
343 if (vport->fc_nodename.u.wwn[0] == 0 || vport->phba->cfg_soft_wwnn)
344 memcpy(&vport->fc_nodename, &vport->fc_sparam.nodeName,
345 sizeof(struct lpfc_name));
346 else
347 memcpy(&vport->fc_sparam.nodeName, &vport->fc_nodename,
348 sizeof(struct lpfc_name));
349
350 if (vport->fc_portname.u.wwn[0] == 0 || vport->phba->cfg_soft_wwpn)
351 memcpy(&vport->fc_portname, &vport->fc_sparam.portName,
352 sizeof(struct lpfc_name));
353 else
354 memcpy(&vport->fc_sparam.portName, &vport->fc_portname,
355 sizeof(struct lpfc_name));
356}
357
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369
370
371int
372lpfc_config_port_post(struct lpfc_hba *phba)
373{
374 struct lpfc_vport *vport = phba->pport;
375 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
376 LPFC_MBOXQ_t *pmb;
377 MAILBOX_t *mb;
378 struct lpfc_dmabuf *mp;
379 struct lpfc_sli *psli = &phba->sli;
380 uint32_t status, timeout;
381 int i, j;
382 int rc;
383
384 spin_lock_irq(&phba->hbalock);
385
386
387
388
389 if (phba->over_temp_state == HBA_OVER_TEMP)
390 phba->over_temp_state = HBA_NORMAL_TEMP;
391 spin_unlock_irq(&phba->hbalock);
392
393 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
394 if (!pmb) {
395 phba->link_state = LPFC_HBA_ERROR;
396 return -ENOMEM;
397 }
398 mb = &pmb->u.mb;
399
400
401 rc = lpfc_read_sparam(phba, pmb, 0);
402 if (rc) {
403 mempool_free(pmb, phba->mbox_mem_pool);
404 return -ENOMEM;
405 }
406
407 pmb->vport = vport;
408 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
409 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
410 "0448 Adapter failed init, mbxCmd x%x "
411 "READ_SPARM mbxStatus x%x\n",
412 mb->mbxCommand, mb->mbxStatus);
413 phba->link_state = LPFC_HBA_ERROR;
414 mp = (struct lpfc_dmabuf *) pmb->context1;
415 mempool_free(pmb, phba->mbox_mem_pool);
416 lpfc_mbuf_free(phba, mp->virt, mp->phys);
417 kfree(mp);
418 return -EIO;
419 }
420
421 mp = (struct lpfc_dmabuf *) pmb->context1;
422
423 memcpy(&vport->fc_sparam, mp->virt, sizeof (struct serv_parm));
424 lpfc_mbuf_free(phba, mp->virt, mp->phys);
425 kfree(mp);
426 pmb->context1 = NULL;
427 lpfc_update_vport_wwn(vport);
428
429
430 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
431 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
432 fc_host_max_npiv_vports(shost) = phba->max_vpi;
433
434
435
436 if (phba->SerialNumber[0] == 0) {
437 uint8_t *outptr;
438
439 outptr = &vport->fc_nodename.u.s.IEEE[0];
440 for (i = 0; i < 12; i++) {
441 status = *outptr++;
442 j = ((status & 0xf0) >> 4);
443 if (j <= 9)
444 phba->SerialNumber[i] =
445 (char)((uint8_t) 0x30 + (uint8_t) j);
446 else
447 phba->SerialNumber[i] =
448 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
449 i++;
450 j = (status & 0xf);
451 if (j <= 9)
452 phba->SerialNumber[i] =
453 (char)((uint8_t) 0x30 + (uint8_t) j);
454 else
455 phba->SerialNumber[i] =
456 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
457 }
458 }
459
460 lpfc_read_config(phba, pmb);
461 pmb->vport = vport;
462 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
463 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
464 "0453 Adapter failed to init, mbxCmd x%x "
465 "READ_CONFIG, mbxStatus x%x\n",
466 mb->mbxCommand, mb->mbxStatus);
467 phba->link_state = LPFC_HBA_ERROR;
468 mempool_free( pmb, phba->mbox_mem_pool);
469 return -EIO;
470 }
471
472
473 lpfc_sli_read_link_ste(phba);
474
475
476 i = (mb->un.varRdConfig.max_xri + 1);
477 if (phba->cfg_hba_queue_depth > i) {
478 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
479 "3359 HBA queue depth changed from %d to %d\n",
480 phba->cfg_hba_queue_depth, i);
481 phba->cfg_hba_queue_depth = i;
482 }
483
484
485 i = (mb->un.varRdConfig.max_xri >> 3);
486 if (phba->pport->cfg_lun_queue_depth > i) {
487 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
488 "3360 LUN queue depth changed from %d to %d\n",
489 phba->pport->cfg_lun_queue_depth, i);
490 phba->pport->cfg_lun_queue_depth = i;
491 }
492
493 phba->lmt = mb->un.varRdConfig.lmt;
494
495
496 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
497
498 phba->link_state = LPFC_LINK_DOWN;
499
500
501 if (psli->ring[psli->extra_ring].sli.sli3.cmdringaddr)
502 psli->ring[psli->extra_ring].flag |= LPFC_STOP_IOCB_EVENT;
503 if (psli->ring[psli->fcp_ring].sli.sli3.cmdringaddr)
504 psli->ring[psli->fcp_ring].flag |= LPFC_STOP_IOCB_EVENT;
505 if (psli->ring[psli->next_ring].sli.sli3.cmdringaddr)
506 psli->ring[psli->next_ring].flag |= LPFC_STOP_IOCB_EVENT;
507
508
509 if (phba->sli_rev != 3)
510 lpfc_post_rcv_buf(phba);
511
512
513
514
515 if (phba->intr_type == MSIX) {
516 rc = lpfc_config_msi(phba, pmb);
517 if (rc) {
518 mempool_free(pmb, phba->mbox_mem_pool);
519 return -EIO;
520 }
521 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
522 if (rc != MBX_SUCCESS) {
523 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
524 "0352 Config MSI mailbox command "
525 "failed, mbxCmd x%x, mbxStatus x%x\n",
526 pmb->u.mb.mbxCommand,
527 pmb->u.mb.mbxStatus);
528 mempool_free(pmb, phba->mbox_mem_pool);
529 return -EIO;
530 }
531 }
532
533 spin_lock_irq(&phba->hbalock);
534
535 phba->hba_flag &= ~HBA_ERATT_HANDLED;
536
537
538 if (lpfc_readl(phba->HCregaddr, &status)) {
539 spin_unlock_irq(&phba->hbalock);
540 return -EIO;
541 }
542 status |= HC_MBINT_ENA | HC_ERINT_ENA | HC_LAINT_ENA;
543 if (psli->num_rings > 0)
544 status |= HC_R0INT_ENA;
545 if (psli->num_rings > 1)
546 status |= HC_R1INT_ENA;
547 if (psli->num_rings > 2)
548 status |= HC_R2INT_ENA;
549 if (psli->num_rings > 3)
550 status |= HC_R3INT_ENA;
551
552 if ((phba->cfg_poll & ENABLE_FCP_RING_POLLING) &&
553 (phba->cfg_poll & DISABLE_FCP_RING_INT))
554 status &= ~(HC_R0INT_ENA);
555
556 writel(status, phba->HCregaddr);
557 readl(phba->HCregaddr);
558 spin_unlock_irq(&phba->hbalock);
559
560
561 timeout = phba->fc_ratov * 2;
562 mod_timer(&vport->els_tmofunc,
563 jiffies + msecs_to_jiffies(1000 * timeout));
564
565 mod_timer(&phba->hb_tmofunc,
566 jiffies + msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
567 phba->hb_outstanding = 0;
568 phba->last_completion_time = jiffies;
569
570 mod_timer(&phba->eratt_poll,
571 jiffies + msecs_to_jiffies(1000 * LPFC_ERATT_POLL_INTERVAL));
572
573 if (phba->hba_flag & LINK_DISABLED) {
574 lpfc_printf_log(phba,
575 KERN_ERR, LOG_INIT,
576 "2598 Adapter Link is disabled.\n");
577 lpfc_down_link(phba, pmb);
578 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
579 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
580 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
581 lpfc_printf_log(phba,
582 KERN_ERR, LOG_INIT,
583 "2599 Adapter failed to issue DOWN_LINK"
584 " mbox command rc 0x%x\n", rc);
585
586 mempool_free(pmb, phba->mbox_mem_pool);
587 return -EIO;
588 }
589 } else if (phba->cfg_suppress_link_up == LPFC_INITIALIZE_LINK) {
590 mempool_free(pmb, phba->mbox_mem_pool);
591 rc = phba->lpfc_hba_init_link(phba, MBX_NOWAIT);
592 if (rc)
593 return rc;
594 }
595
596 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
597 if (!pmb) {
598 phba->link_state = LPFC_HBA_ERROR;
599 return -ENOMEM;
600 }
601
602 lpfc_config_async(phba, pmb, LPFC_ELS_RING);
603 pmb->mbox_cmpl = lpfc_config_async_cmpl;
604 pmb->vport = phba->pport;
605 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
606
607 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
608 lpfc_printf_log(phba,
609 KERN_ERR,
610 LOG_INIT,
611 "0456 Adapter failed to issue "
612 "ASYNCEVT_ENABLE mbox status x%x\n",
613 rc);
614 mempool_free(pmb, phba->mbox_mem_pool);
615 }
616
617
618 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
619 if (!pmb) {
620 phba->link_state = LPFC_HBA_ERROR;
621 return -ENOMEM;
622 }
623
624 lpfc_dump_wakeup_param(phba, pmb);
625 pmb->mbox_cmpl = lpfc_dump_wakeup_param_cmpl;
626 pmb->vport = phba->pport;
627 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
628
629 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
630 lpfc_printf_log(phba, KERN_ERR, LOG_INIT, "0435 Adapter failed "
631 "to get Option ROM version status x%x\n", rc);
632 mempool_free(pmb, phba->mbox_mem_pool);
633 }
634
635 return 0;
636}
637
638
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641
642
643
644
645
646
647
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649
650
651
652static int
653lpfc_hba_init_link(struct lpfc_hba *phba, uint32_t flag)
654{
655 return lpfc_hba_init_link_fc_topology(phba, phba->cfg_topology, flag);
656}
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673int
674lpfc_hba_init_link_fc_topology(struct lpfc_hba *phba, uint32_t fc_topology,
675 uint32_t flag)
676{
677 struct lpfc_vport *vport = phba->pport;
678 LPFC_MBOXQ_t *pmb;
679 MAILBOX_t *mb;
680 int rc;
681
682 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
683 if (!pmb) {
684 phba->link_state = LPFC_HBA_ERROR;
685 return -ENOMEM;
686 }
687 mb = &pmb->u.mb;
688 pmb->vport = vport;
689
690 if ((phba->cfg_link_speed > LPFC_USER_LINK_SPEED_MAX) ||
691 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_1G) &&
692 !(phba->lmt & LMT_1Gb)) ||
693 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_2G) &&
694 !(phba->lmt & LMT_2Gb)) ||
695 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_4G) &&
696 !(phba->lmt & LMT_4Gb)) ||
697 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_8G) &&
698 !(phba->lmt & LMT_8Gb)) ||
699 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_10G) &&
700 !(phba->lmt & LMT_10Gb)) ||
701 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_16G) &&
702 !(phba->lmt & LMT_16Gb)) ||
703 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_32G) &&
704 !(phba->lmt & LMT_32Gb))) {
705
706 lpfc_printf_log(phba, KERN_ERR, LOG_LINK_EVENT,
707 "1302 Invalid speed for this board:%d "
708 "Reset link speed to auto.\n",
709 phba->cfg_link_speed);
710 phba->cfg_link_speed = LPFC_USER_LINK_SPEED_AUTO;
711 }
712 lpfc_init_link(phba, pmb, fc_topology, phba->cfg_link_speed);
713 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
714 if (phba->sli_rev < LPFC_SLI_REV4)
715 lpfc_set_loopback_flag(phba);
716 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
717 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
718 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
719 "0498 Adapter failed to init, mbxCmd x%x "
720 "INIT_LINK, mbxStatus x%x\n",
721 mb->mbxCommand, mb->mbxStatus);
722 if (phba->sli_rev <= LPFC_SLI_REV3) {
723
724 writel(0, phba->HCregaddr);
725 readl(phba->HCregaddr);
726
727 writel(0xffffffff, phba->HAregaddr);
728 readl(phba->HAregaddr);
729 }
730 phba->link_state = LPFC_HBA_ERROR;
731 if (rc != MBX_BUSY || flag == MBX_POLL)
732 mempool_free(pmb, phba->mbox_mem_pool);
733 return -EIO;
734 }
735 phba->cfg_suppress_link_up = LPFC_INITIALIZE_LINK;
736 if (flag == MBX_POLL)
737 mempool_free(pmb, phba->mbox_mem_pool);
738
739 return 0;
740}
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755static int
756lpfc_hba_down_link(struct lpfc_hba *phba, uint32_t flag)
757{
758 LPFC_MBOXQ_t *pmb;
759 int rc;
760
761 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
762 if (!pmb) {
763 phba->link_state = LPFC_HBA_ERROR;
764 return -ENOMEM;
765 }
766
767 lpfc_printf_log(phba,
768 KERN_ERR, LOG_INIT,
769 "0491 Adapter Link is disabled.\n");
770 lpfc_down_link(phba, pmb);
771 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
772 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
773 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
774 lpfc_printf_log(phba,
775 KERN_ERR, LOG_INIT,
776 "2522 Adapter failed to issue DOWN_LINK"
777 " mbox command rc 0x%x\n", rc);
778
779 mempool_free(pmb, phba->mbox_mem_pool);
780 return -EIO;
781 }
782 if (flag == MBX_POLL)
783 mempool_free(pmb, phba->mbox_mem_pool);
784
785 return 0;
786}
787
788
789
790
791
792
793
794
795
796
797
798
799int
800lpfc_hba_down_prep(struct lpfc_hba *phba)
801{
802 struct lpfc_vport **vports;
803 int i;
804
805 if (phba->sli_rev <= LPFC_SLI_REV3) {
806
807 writel(0, phba->HCregaddr);
808 readl(phba->HCregaddr);
809 }
810
811 if (phba->pport->load_flag & FC_UNLOADING)
812 lpfc_cleanup_discovery_resources(phba->pport);
813 else {
814 vports = lpfc_create_vport_work_array(phba);
815 if (vports != NULL)
816 for (i = 0; i <= phba->max_vports &&
817 vports[i] != NULL; i++)
818 lpfc_cleanup_discovery_resources(vports[i]);
819 lpfc_destroy_vport_work_array(phba, vports);
820 }
821 return 0;
822}
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837static void
838lpfc_sli4_free_sp_events(struct lpfc_hba *phba)
839{
840 struct lpfc_iocbq *rspiocbq;
841 struct hbq_dmabuf *dmabuf;
842 struct lpfc_cq_event *cq_event;
843
844 spin_lock_irq(&phba->hbalock);
845 phba->hba_flag &= ~HBA_SP_QUEUE_EVT;
846 spin_unlock_irq(&phba->hbalock);
847
848 while (!list_empty(&phba->sli4_hba.sp_queue_event)) {
849
850 spin_lock_irq(&phba->hbalock);
851 list_remove_head(&phba->sli4_hba.sp_queue_event,
852 cq_event, struct lpfc_cq_event, list);
853 spin_unlock_irq(&phba->hbalock);
854
855 switch (bf_get(lpfc_wcqe_c_code, &cq_event->cqe.wcqe_cmpl)) {
856 case CQE_CODE_COMPL_WQE:
857 rspiocbq = container_of(cq_event, struct lpfc_iocbq,
858 cq_event);
859 lpfc_sli_release_iocbq(phba, rspiocbq);
860 break;
861 case CQE_CODE_RECEIVE:
862 case CQE_CODE_RECEIVE_V1:
863 dmabuf = container_of(cq_event, struct hbq_dmabuf,
864 cq_event);
865 lpfc_in_buf_free(phba, &dmabuf->dbuf);
866 }
867 }
868}
869
870
871
872
873
874
875
876
877
878
879
880
881static void
882lpfc_hba_free_post_buf(struct lpfc_hba *phba)
883{
884 struct lpfc_sli *psli = &phba->sli;
885 struct lpfc_sli_ring *pring;
886 struct lpfc_dmabuf *mp, *next_mp;
887 LIST_HEAD(buflist);
888 int count;
889
890 if (phba->sli3_options & LPFC_SLI3_HBQ_ENABLED)
891 lpfc_sli_hbqbuf_free_all(phba);
892 else {
893
894 pring = &psli->ring[LPFC_ELS_RING];
895 spin_lock_irq(&phba->hbalock);
896 list_splice_init(&pring->postbufq, &buflist);
897 spin_unlock_irq(&phba->hbalock);
898
899 count = 0;
900 list_for_each_entry_safe(mp, next_mp, &buflist, list) {
901 list_del(&mp->list);
902 count++;
903 lpfc_mbuf_free(phba, mp->virt, mp->phys);
904 kfree(mp);
905 }
906
907 spin_lock_irq(&phba->hbalock);
908 pring->postbufq_cnt -= count;
909 spin_unlock_irq(&phba->hbalock);
910 }
911}
912
913
914
915
916
917
918
919
920
921
922
923static void
924lpfc_hba_clean_txcmplq(struct lpfc_hba *phba)
925{
926 struct lpfc_sli *psli = &phba->sli;
927 struct lpfc_sli_ring *pring;
928 LIST_HEAD(completions);
929 int i;
930
931 for (i = 0; i < psli->num_rings; i++) {
932 pring = &psli->ring[i];
933 if (phba->sli_rev >= LPFC_SLI_REV4)
934 spin_lock_irq(&pring->ring_lock);
935 else
936 spin_lock_irq(&phba->hbalock);
937
938
939
940 list_splice_init(&pring->txcmplq, &completions);
941 pring->txcmplq_cnt = 0;
942
943 if (phba->sli_rev >= LPFC_SLI_REV4)
944 spin_unlock_irq(&pring->ring_lock);
945 else
946 spin_unlock_irq(&phba->hbalock);
947
948
949 lpfc_sli_cancel_iocbs(phba, &completions, IOSTAT_LOCAL_REJECT,
950 IOERR_SLI_ABORTED);
951 lpfc_sli_abort_iocb_ring(phba, pring);
952 }
953}
954
955
956
957
958
959
960
961
962
963
964
965
966
967static int
968lpfc_hba_down_post_s3(struct lpfc_hba *phba)
969{
970 lpfc_hba_free_post_buf(phba);
971 lpfc_hba_clean_txcmplq(phba);
972 return 0;
973}
974
975
976
977
978
979
980
981
982
983
984
985
986static int
987lpfc_hba_down_post_s4(struct lpfc_hba *phba)
988{
989 struct lpfc_scsi_buf *psb, *psb_next;
990 LIST_HEAD(aborts);
991 unsigned long iflag = 0;
992 struct lpfc_sglq *sglq_entry = NULL;
993 struct lpfc_sli *psli = &phba->sli;
994 struct lpfc_sli_ring *pring;
995
996 lpfc_hba_free_post_buf(phba);
997 lpfc_hba_clean_txcmplq(phba);
998 pring = &psli->ring[LPFC_ELS_RING];
999
1000
1001
1002
1003
1004
1005
1006 spin_lock_irq(&phba->hbalock);
1007
1008
1009
1010
1011 spin_lock(&phba->sli4_hba.abts_sgl_list_lock);
1012 list_for_each_entry(sglq_entry,
1013 &phba->sli4_hba.lpfc_abts_els_sgl_list, list)
1014 sglq_entry->state = SGL_FREED;
1015
1016 spin_lock(&pring->ring_lock);
1017 list_splice_init(&phba->sli4_hba.lpfc_abts_els_sgl_list,
1018 &phba->sli4_hba.lpfc_sgl_list);
1019 spin_unlock(&pring->ring_lock);
1020 spin_unlock(&phba->sli4_hba.abts_sgl_list_lock);
1021
1022
1023
1024 spin_lock(&phba->sli4_hba.abts_scsi_buf_list_lock);
1025 list_splice_init(&phba->sli4_hba.lpfc_abts_scsi_buf_list,
1026 &aborts);
1027 spin_unlock(&phba->sli4_hba.abts_scsi_buf_list_lock);
1028 spin_unlock_irq(&phba->hbalock);
1029
1030 list_for_each_entry_safe(psb, psb_next, &aborts, list) {
1031 psb->pCmd = NULL;
1032 psb->status = IOSTAT_SUCCESS;
1033 }
1034 spin_lock_irqsave(&phba->scsi_buf_list_put_lock, iflag);
1035 list_splice(&aborts, &phba->lpfc_scsi_buf_list_put);
1036 spin_unlock_irqrestore(&phba->scsi_buf_list_put_lock, iflag);
1037
1038 lpfc_sli4_free_sp_events(phba);
1039 return 0;
1040}
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053int
1054lpfc_hba_down_post(struct lpfc_hba *phba)
1055{
1056 return (*phba->lpfc_hba_down_post)(phba);
1057}
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071static void
1072lpfc_hb_timeout(unsigned long ptr)
1073{
1074 struct lpfc_hba *phba;
1075 uint32_t tmo_posted;
1076 unsigned long iflag;
1077
1078 phba = (struct lpfc_hba *)ptr;
1079
1080
1081 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
1082 tmo_posted = phba->pport->work_port_events & WORKER_HB_TMO;
1083 if (!tmo_posted)
1084 phba->pport->work_port_events |= WORKER_HB_TMO;
1085 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1086
1087
1088 if (!tmo_posted)
1089 lpfc_worker_wake_up(phba);
1090 return;
1091}
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105static void
1106lpfc_rrq_timeout(unsigned long ptr)
1107{
1108 struct lpfc_hba *phba;
1109 unsigned long iflag;
1110
1111 phba = (struct lpfc_hba *)ptr;
1112 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
1113 if (!(phba->pport->load_flag & FC_UNLOADING))
1114 phba->hba_flag |= HBA_RRQ_ACTIVE;
1115 else
1116 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
1117 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1118
1119 if (!(phba->pport->load_flag & FC_UNLOADING))
1120 lpfc_worker_wake_up(phba);
1121}
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139static void
1140lpfc_hb_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
1141{
1142 unsigned long drvr_flag;
1143
1144 spin_lock_irqsave(&phba->hbalock, drvr_flag);
1145 phba->hb_outstanding = 0;
1146 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
1147
1148
1149 mempool_free(pmboxq, phba->mbox_mem_pool);
1150 if (!(phba->pport->fc_flag & FC_OFFLINE_MODE) &&
1151 !(phba->link_state == LPFC_HBA_ERROR) &&
1152 !(phba->pport->load_flag & FC_UNLOADING))
1153 mod_timer(&phba->hb_tmofunc,
1154 jiffies +
1155 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
1156 return;
1157}
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175void
1176lpfc_hb_timeout_handler(struct lpfc_hba *phba)
1177{
1178 struct lpfc_vport **vports;
1179 LPFC_MBOXQ_t *pmboxq;
1180 struct lpfc_dmabuf *buf_ptr;
1181 int retval, i;
1182 struct lpfc_sli *psli = &phba->sli;
1183 LIST_HEAD(completions);
1184
1185 vports = lpfc_create_vport_work_array(phba);
1186 if (vports != NULL)
1187 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
1188 lpfc_rcv_seq_check_edtov(vports[i]);
1189 lpfc_fdmi_num_disc_check(vports[i]);
1190 }
1191 lpfc_destroy_vport_work_array(phba, vports);
1192
1193 if ((phba->link_state == LPFC_HBA_ERROR) ||
1194 (phba->pport->load_flag & FC_UNLOADING) ||
1195 (phba->pport->fc_flag & FC_OFFLINE_MODE))
1196 return;
1197
1198 spin_lock_irq(&phba->pport->work_port_lock);
1199
1200 if (time_after(phba->last_completion_time +
1201 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL),
1202 jiffies)) {
1203 spin_unlock_irq(&phba->pport->work_port_lock);
1204 if (!phba->hb_outstanding)
1205 mod_timer(&phba->hb_tmofunc,
1206 jiffies +
1207 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
1208 else
1209 mod_timer(&phba->hb_tmofunc,
1210 jiffies +
1211 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
1212 return;
1213 }
1214 spin_unlock_irq(&phba->pport->work_port_lock);
1215
1216 if (phba->elsbuf_cnt &&
1217 (phba->elsbuf_cnt == phba->elsbuf_prev_cnt)) {
1218 spin_lock_irq(&phba->hbalock);
1219 list_splice_init(&phba->elsbuf, &completions);
1220 phba->elsbuf_cnt = 0;
1221 phba->elsbuf_prev_cnt = 0;
1222 spin_unlock_irq(&phba->hbalock);
1223
1224 while (!list_empty(&completions)) {
1225 list_remove_head(&completions, buf_ptr,
1226 struct lpfc_dmabuf, list);
1227 lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
1228 kfree(buf_ptr);
1229 }
1230 }
1231 phba->elsbuf_prev_cnt = phba->elsbuf_cnt;
1232
1233
1234 if (phba->cfg_enable_hba_heartbeat) {
1235 if (!phba->hb_outstanding) {
1236 if ((!(psli->sli_flag & LPFC_SLI_MBOX_ACTIVE)) &&
1237 (list_empty(&psli->mboxq))) {
1238 pmboxq = mempool_alloc(phba->mbox_mem_pool,
1239 GFP_KERNEL);
1240 if (!pmboxq) {
1241 mod_timer(&phba->hb_tmofunc,
1242 jiffies +
1243 msecs_to_jiffies(1000 *
1244 LPFC_HB_MBOX_INTERVAL));
1245 return;
1246 }
1247
1248 lpfc_heart_beat(phba, pmboxq);
1249 pmboxq->mbox_cmpl = lpfc_hb_mbox_cmpl;
1250 pmboxq->vport = phba->pport;
1251 retval = lpfc_sli_issue_mbox(phba, pmboxq,
1252 MBX_NOWAIT);
1253
1254 if (retval != MBX_BUSY &&
1255 retval != MBX_SUCCESS) {
1256 mempool_free(pmboxq,
1257 phba->mbox_mem_pool);
1258 mod_timer(&phba->hb_tmofunc,
1259 jiffies +
1260 msecs_to_jiffies(1000 *
1261 LPFC_HB_MBOX_INTERVAL));
1262 return;
1263 }
1264 phba->skipped_hb = 0;
1265 phba->hb_outstanding = 1;
1266 } else if (time_before_eq(phba->last_completion_time,
1267 phba->skipped_hb)) {
1268 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1269 "2857 Last completion time not "
1270 " updated in %d ms\n",
1271 jiffies_to_msecs(jiffies
1272 - phba->last_completion_time));
1273 } else
1274 phba->skipped_hb = jiffies;
1275
1276 mod_timer(&phba->hb_tmofunc,
1277 jiffies +
1278 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
1279 return;
1280 } else {
1281
1282
1283
1284
1285
1286 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1287 "0459 Adapter heartbeat still out"
1288 "standing:last compl time was %d ms.\n",
1289 jiffies_to_msecs(jiffies
1290 - phba->last_completion_time));
1291 mod_timer(&phba->hb_tmofunc,
1292 jiffies +
1293 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
1294 }
1295 } else {
1296 mod_timer(&phba->hb_tmofunc,
1297 jiffies +
1298 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
1299 }
1300}
1301
1302
1303
1304
1305
1306
1307
1308
1309static void
1310lpfc_offline_eratt(struct lpfc_hba *phba)
1311{
1312 struct lpfc_sli *psli = &phba->sli;
1313
1314 spin_lock_irq(&phba->hbalock);
1315 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
1316 spin_unlock_irq(&phba->hbalock);
1317 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
1318
1319 lpfc_offline(phba);
1320 lpfc_reset_barrier(phba);
1321 spin_lock_irq(&phba->hbalock);
1322 lpfc_sli_brdreset(phba);
1323 spin_unlock_irq(&phba->hbalock);
1324 lpfc_hba_down_post(phba);
1325 lpfc_sli_brdready(phba, HS_MBRDY);
1326 lpfc_unblock_mgmt_io(phba);
1327 phba->link_state = LPFC_HBA_ERROR;
1328 return;
1329}
1330
1331
1332
1333
1334
1335
1336
1337
1338void
1339lpfc_sli4_offline_eratt(struct lpfc_hba *phba)
1340{
1341 spin_lock_irq(&phba->hbalock);
1342 phba->link_state = LPFC_HBA_ERROR;
1343 spin_unlock_irq(&phba->hbalock);
1344
1345 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
1346 lpfc_offline(phba);
1347 lpfc_hba_down_post(phba);
1348 lpfc_unblock_mgmt_io(phba);
1349}
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360static void
1361lpfc_handle_deferred_eratt(struct lpfc_hba *phba)
1362{
1363 uint32_t old_host_status = phba->work_hs;
1364 struct lpfc_sli *psli = &phba->sli;
1365
1366
1367
1368
1369 if (pci_channel_offline(phba->pcidev)) {
1370 spin_lock_irq(&phba->hbalock);
1371 phba->hba_flag &= ~DEFER_ERATT;
1372 spin_unlock_irq(&phba->hbalock);
1373 return;
1374 }
1375
1376 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1377 "0479 Deferred Adapter Hardware Error "
1378 "Data: x%x x%x x%x\n",
1379 phba->work_hs,
1380 phba->work_status[0], phba->work_status[1]);
1381
1382 spin_lock_irq(&phba->hbalock);
1383 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
1384 spin_unlock_irq(&phba->hbalock);
1385
1386
1387
1388
1389
1390
1391
1392 lpfc_sli_abort_fcp_rings(phba);
1393
1394
1395
1396
1397
1398 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
1399 lpfc_offline(phba);
1400
1401
1402 while (phba->work_hs & HS_FFER1) {
1403 msleep(100);
1404 if (lpfc_readl(phba->HSregaddr, &phba->work_hs)) {
1405 phba->work_hs = UNPLUG_ERR ;
1406 break;
1407 }
1408
1409 if (phba->pport->load_flag & FC_UNLOADING) {
1410 phba->work_hs = 0;
1411 break;
1412 }
1413 }
1414
1415
1416
1417
1418
1419
1420 if ((!phba->work_hs) && (!(phba->pport->load_flag & FC_UNLOADING)))
1421 phba->work_hs = old_host_status & ~HS_FFER1;
1422
1423 spin_lock_irq(&phba->hbalock);
1424 phba->hba_flag &= ~DEFER_ERATT;
1425 spin_unlock_irq(&phba->hbalock);
1426 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
1427 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
1428}
1429
1430static void
1431lpfc_board_errevt_to_mgmt(struct lpfc_hba *phba)
1432{
1433 struct lpfc_board_event_header board_event;
1434 struct Scsi_Host *shost;
1435
1436 board_event.event_type = FC_REG_BOARD_EVENT;
1437 board_event.subcategory = LPFC_EVENT_PORTINTERR;
1438 shost = lpfc_shost_from_vport(phba->pport);
1439 fc_host_post_vendor_event(shost, fc_get_event_number(),
1440 sizeof(board_event),
1441 (char *) &board_event,
1442 LPFC_NL_VENDOR_ID);
1443}
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455static void
1456lpfc_handle_eratt_s3(struct lpfc_hba *phba)
1457{
1458 struct lpfc_vport *vport = phba->pport;
1459 struct lpfc_sli *psli = &phba->sli;
1460 uint32_t event_data;
1461 unsigned long temperature;
1462 struct temp_event temp_event_data;
1463 struct Scsi_Host *shost;
1464
1465
1466
1467
1468 if (pci_channel_offline(phba->pcidev)) {
1469 spin_lock_irq(&phba->hbalock);
1470 phba->hba_flag &= ~DEFER_ERATT;
1471 spin_unlock_irq(&phba->hbalock);
1472 return;
1473 }
1474
1475
1476 if (!phba->cfg_enable_hba_reset)
1477 return;
1478
1479
1480 lpfc_board_errevt_to_mgmt(phba);
1481
1482 if (phba->hba_flag & DEFER_ERATT)
1483 lpfc_handle_deferred_eratt(phba);
1484
1485 if ((phba->work_hs & HS_FFER6) || (phba->work_hs & HS_FFER8)) {
1486 if (phba->work_hs & HS_FFER6)
1487
1488 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1489 "1301 Re-establishing Link "
1490 "Data: x%x x%x x%x\n",
1491 phba->work_hs, phba->work_status[0],
1492 phba->work_status[1]);
1493 if (phba->work_hs & HS_FFER8)
1494
1495 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1496 "2861 Host Authentication device "
1497 "zeroization Data:x%x x%x x%x\n",
1498 phba->work_hs, phba->work_status[0],
1499 phba->work_status[1]);
1500
1501 spin_lock_irq(&phba->hbalock);
1502 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
1503 spin_unlock_irq(&phba->hbalock);
1504
1505
1506
1507
1508
1509
1510
1511 lpfc_sli_abort_fcp_rings(phba);
1512
1513
1514
1515
1516
1517 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
1518 lpfc_offline(phba);
1519 lpfc_sli_brdrestart(phba);
1520 if (lpfc_online(phba) == 0) {
1521 lpfc_unblock_mgmt_io(phba);
1522 return;
1523 }
1524 lpfc_unblock_mgmt_io(phba);
1525 } else if (phba->work_hs & HS_CRIT_TEMP) {
1526 temperature = readl(phba->MBslimaddr + TEMPERATURE_OFFSET);
1527 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1528 temp_event_data.event_code = LPFC_CRIT_TEMP;
1529 temp_event_data.data = (uint32_t)temperature;
1530
1531 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1532 "0406 Adapter maximum temperature exceeded "
1533 "(%ld), taking this port offline "
1534 "Data: x%x x%x x%x\n",
1535 temperature, phba->work_hs,
1536 phba->work_status[0], phba->work_status[1]);
1537
1538 shost = lpfc_shost_from_vport(phba->pport);
1539 fc_host_post_vendor_event(shost, fc_get_event_number(),
1540 sizeof(temp_event_data),
1541 (char *) &temp_event_data,
1542 SCSI_NL_VID_TYPE_PCI
1543 | PCI_VENDOR_ID_EMULEX);
1544
1545 spin_lock_irq(&phba->hbalock);
1546 phba->over_temp_state = HBA_OVER_TEMP;
1547 spin_unlock_irq(&phba->hbalock);
1548 lpfc_offline_eratt(phba);
1549
1550 } else {
1551
1552
1553
1554
1555 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1556 "0457 Adapter Hardware Error "
1557 "Data: x%x x%x x%x\n",
1558 phba->work_hs,
1559 phba->work_status[0], phba->work_status[1]);
1560
1561 event_data = FC_REG_DUMP_EVENT;
1562 shost = lpfc_shost_from_vport(vport);
1563 fc_host_post_vendor_event(shost, fc_get_event_number(),
1564 sizeof(event_data), (char *) &event_data,
1565 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1566
1567 lpfc_offline_eratt(phba);
1568 }
1569 return;
1570}
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583static int
1584lpfc_sli4_port_sta_fn_reset(struct lpfc_hba *phba, int mbx_action,
1585 bool en_rn_msg)
1586{
1587 int rc;
1588 uint32_t intr_mode;
1589
1590
1591
1592
1593
1594 rc = lpfc_sli4_pdev_status_reg_wait(phba);
1595 if (!rc) {
1596
1597 if (en_rn_msg)
1598 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1599 "2887 Reset Needed: Attempting Port "
1600 "Recovery...\n");
1601 lpfc_offline_prep(phba, mbx_action);
1602 lpfc_offline(phba);
1603
1604 lpfc_sli4_disable_intr(phba);
1605 lpfc_sli_brdrestart(phba);
1606
1607 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
1608 if (intr_mode == LPFC_INTR_ERROR) {
1609 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1610 "3175 Failed to enable interrupt\n");
1611 return -EIO;
1612 } else {
1613 phba->intr_mode = intr_mode;
1614 }
1615 rc = lpfc_online(phba);
1616 if (rc == 0)
1617 lpfc_unblock_mgmt_io(phba);
1618 }
1619 return rc;
1620}
1621
1622
1623
1624
1625
1626
1627
1628
1629static void
1630lpfc_handle_eratt_s4(struct lpfc_hba *phba)
1631{
1632 struct lpfc_vport *vport = phba->pport;
1633 uint32_t event_data;
1634 struct Scsi_Host *shost;
1635 uint32_t if_type;
1636 struct lpfc_register portstat_reg = {0};
1637 uint32_t reg_err1, reg_err2;
1638 uint32_t uerrlo_reg, uemasklo_reg;
1639 uint32_t pci_rd_rc1, pci_rd_rc2;
1640 bool en_rn_msg = true;
1641 struct temp_event temp_event_data;
1642 int rc;
1643
1644
1645
1646
1647 if (pci_channel_offline(phba->pcidev))
1648 return;
1649
1650 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
1651 switch (if_type) {
1652 case LPFC_SLI_INTF_IF_TYPE_0:
1653 pci_rd_rc1 = lpfc_readl(
1654 phba->sli4_hba.u.if_type0.UERRLOregaddr,
1655 &uerrlo_reg);
1656 pci_rd_rc2 = lpfc_readl(
1657 phba->sli4_hba.u.if_type0.UEMASKLOregaddr,
1658 &uemasklo_reg);
1659
1660 if (pci_rd_rc1 == -EIO && pci_rd_rc2 == -EIO)
1661 return;
1662 lpfc_sli4_offline_eratt(phba);
1663 break;
1664
1665 case LPFC_SLI_INTF_IF_TYPE_2:
1666 pci_rd_rc1 = lpfc_readl(
1667 phba->sli4_hba.u.if_type2.STATUSregaddr,
1668 &portstat_reg.word0);
1669
1670 if (pci_rd_rc1 == -EIO) {
1671 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1672 "3151 PCI bus read access failure: x%x\n",
1673 readl(phba->sli4_hba.u.if_type2.STATUSregaddr));
1674 return;
1675 }
1676 reg_err1 = readl(phba->sli4_hba.u.if_type2.ERR1regaddr);
1677 reg_err2 = readl(phba->sli4_hba.u.if_type2.ERR2regaddr);
1678 if (bf_get(lpfc_sliport_status_oti, &portstat_reg)) {
1679 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1680 "2889 Port Overtemperature event, "
1681 "taking port offline Data: x%x x%x\n",
1682 reg_err1, reg_err2);
1683
1684 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1685 temp_event_data.event_code = LPFC_CRIT_TEMP;
1686 temp_event_data.data = 0xFFFFFFFF;
1687
1688 shost = lpfc_shost_from_vport(phba->pport);
1689 fc_host_post_vendor_event(shost, fc_get_event_number(),
1690 sizeof(temp_event_data),
1691 (char *)&temp_event_data,
1692 SCSI_NL_VID_TYPE_PCI
1693 | PCI_VENDOR_ID_EMULEX);
1694
1695 spin_lock_irq(&phba->hbalock);
1696 phba->over_temp_state = HBA_OVER_TEMP;
1697 spin_unlock_irq(&phba->hbalock);
1698 lpfc_sli4_offline_eratt(phba);
1699 return;
1700 }
1701 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1702 reg_err2 == SLIPORT_ERR2_REG_FW_RESTART) {
1703 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1704 "3143 Port Down: Firmware Update "
1705 "Detected\n");
1706 en_rn_msg = false;
1707 } else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1708 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1709 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1710 "3144 Port Down: Debug Dump\n");
1711 else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1712 reg_err2 == SLIPORT_ERR2_REG_FUNC_PROVISON)
1713 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1714 "3145 Port Down: Provisioning\n");
1715
1716
1717 if (!phba->cfg_enable_hba_reset)
1718 return;
1719
1720
1721 rc = lpfc_sli4_port_sta_fn_reset(phba, LPFC_MBX_NO_WAIT,
1722 en_rn_msg);
1723 if (rc == 0) {
1724
1725 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1726 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1727 return;
1728 else
1729 break;
1730 }
1731
1732 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1733 "3152 Unrecoverable error, bring the port "
1734 "offline\n");
1735 lpfc_sli4_offline_eratt(phba);
1736 break;
1737 case LPFC_SLI_INTF_IF_TYPE_1:
1738 default:
1739 break;
1740 }
1741 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1742 "3123 Report dump event to upper layer\n");
1743
1744 lpfc_board_errevt_to_mgmt(phba);
1745
1746 event_data = FC_REG_DUMP_EVENT;
1747 shost = lpfc_shost_from_vport(vport);
1748 fc_host_post_vendor_event(shost, fc_get_event_number(),
1749 sizeof(event_data), (char *) &event_data,
1750 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1751}
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764void
1765lpfc_handle_eratt(struct lpfc_hba *phba)
1766{
1767 (*phba->lpfc_handle_eratt)(phba);
1768}
1769
1770
1771
1772
1773
1774
1775
1776
1777void
1778lpfc_handle_latt(struct lpfc_hba *phba)
1779{
1780 struct lpfc_vport *vport = phba->pport;
1781 struct lpfc_sli *psli = &phba->sli;
1782 LPFC_MBOXQ_t *pmb;
1783 volatile uint32_t control;
1784 struct lpfc_dmabuf *mp;
1785 int rc = 0;
1786
1787 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
1788 if (!pmb) {
1789 rc = 1;
1790 goto lpfc_handle_latt_err_exit;
1791 }
1792
1793 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
1794 if (!mp) {
1795 rc = 2;
1796 goto lpfc_handle_latt_free_pmb;
1797 }
1798
1799 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
1800 if (!mp->virt) {
1801 rc = 3;
1802 goto lpfc_handle_latt_free_mp;
1803 }
1804
1805
1806 lpfc_els_flush_all_cmd(phba);
1807
1808 psli->slistat.link_event++;
1809 lpfc_read_topology(phba, pmb, mp);
1810 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
1811 pmb->vport = vport;
1812
1813 phba->sli.ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
1814 rc = lpfc_sli_issue_mbox (phba, pmb, MBX_NOWAIT);
1815 if (rc == MBX_NOT_FINISHED) {
1816 rc = 4;
1817 goto lpfc_handle_latt_free_mbuf;
1818 }
1819
1820
1821 spin_lock_irq(&phba->hbalock);
1822 writel(HA_LATT, phba->HAregaddr);
1823 readl(phba->HAregaddr);
1824 spin_unlock_irq(&phba->hbalock);
1825
1826 return;
1827
1828lpfc_handle_latt_free_mbuf:
1829 phba->sli.ring[LPFC_ELS_RING].flag &= ~LPFC_STOP_IOCB_EVENT;
1830 lpfc_mbuf_free(phba, mp->virt, mp->phys);
1831lpfc_handle_latt_free_mp:
1832 kfree(mp);
1833lpfc_handle_latt_free_pmb:
1834 mempool_free(pmb, phba->mbox_mem_pool);
1835lpfc_handle_latt_err_exit:
1836
1837 spin_lock_irq(&phba->hbalock);
1838 psli->sli_flag |= LPFC_PROCESS_LA;
1839 control = readl(phba->HCregaddr);
1840 control |= HC_LAINT_ENA;
1841 writel(control, phba->HCregaddr);
1842 readl(phba->HCregaddr);
1843
1844
1845 writel(HA_LATT, phba->HAregaddr);
1846 readl(phba->HAregaddr);
1847 spin_unlock_irq(&phba->hbalock);
1848 lpfc_linkdown(phba);
1849 phba->link_state = LPFC_HBA_ERROR;
1850
1851 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
1852 "0300 LATT: Cannot issue READ_LA: Data:%d\n", rc);
1853
1854 return;
1855}
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871int
1872lpfc_parse_vpd(struct lpfc_hba *phba, uint8_t *vpd, int len)
1873{
1874 uint8_t lenlo, lenhi;
1875 int Length;
1876 int i, j;
1877 int finished = 0;
1878 int index = 0;
1879
1880 if (!vpd)
1881 return 0;
1882
1883
1884 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1885 "0455 Vital Product Data: x%x x%x x%x x%x\n",
1886 (uint32_t) vpd[0], (uint32_t) vpd[1], (uint32_t) vpd[2],
1887 (uint32_t) vpd[3]);
1888 while (!finished && (index < (len - 4))) {
1889 switch (vpd[index]) {
1890 case 0x82:
1891 case 0x91:
1892 index += 1;
1893 lenlo = vpd[index];
1894 index += 1;
1895 lenhi = vpd[index];
1896 index += 1;
1897 i = ((((unsigned short)lenhi) << 8) + lenlo);
1898 index += i;
1899 break;
1900 case 0x90:
1901 index += 1;
1902 lenlo = vpd[index];
1903 index += 1;
1904 lenhi = vpd[index];
1905 index += 1;
1906 Length = ((((unsigned short)lenhi) << 8) + lenlo);
1907 if (Length > len - index)
1908 Length = len - index;
1909 while (Length > 0) {
1910
1911 if ((vpd[index] == 'S') && (vpd[index+1] == 'N')) {
1912 index += 2;
1913 i = vpd[index];
1914 index += 1;
1915 j = 0;
1916 Length -= (3+i);
1917 while(i--) {
1918 phba->SerialNumber[j++] = vpd[index++];
1919 if (j == 31)
1920 break;
1921 }
1922 phba->SerialNumber[j] = 0;
1923 continue;
1924 }
1925 else if ((vpd[index] == 'V') && (vpd[index+1] == '1')) {
1926 phba->vpd_flag |= VPD_MODEL_DESC;
1927 index += 2;
1928 i = vpd[index];
1929 index += 1;
1930 j = 0;
1931 Length -= (3+i);
1932 while(i--) {
1933 phba->ModelDesc[j++] = vpd[index++];
1934 if (j == 255)
1935 break;
1936 }
1937 phba->ModelDesc[j] = 0;
1938 continue;
1939 }
1940 else if ((vpd[index] == 'V') && (vpd[index+1] == '2')) {
1941 phba->vpd_flag |= VPD_MODEL_NAME;
1942 index += 2;
1943 i = vpd[index];
1944 index += 1;
1945 j = 0;
1946 Length -= (3+i);
1947 while(i--) {
1948 phba->ModelName[j++] = vpd[index++];
1949 if (j == 79)
1950 break;
1951 }
1952 phba->ModelName[j] = 0;
1953 continue;
1954 }
1955 else if ((vpd[index] == 'V') && (vpd[index+1] == '3')) {
1956 phba->vpd_flag |= VPD_PROGRAM_TYPE;
1957 index += 2;
1958 i = vpd[index];
1959 index += 1;
1960 j = 0;
1961 Length -= (3+i);
1962 while(i--) {
1963 phba->ProgramType[j++] = vpd[index++];
1964 if (j == 255)
1965 break;
1966 }
1967 phba->ProgramType[j] = 0;
1968 continue;
1969 }
1970 else if ((vpd[index] == 'V') && (vpd[index+1] == '4')) {
1971 phba->vpd_flag |= VPD_PORT;
1972 index += 2;
1973 i = vpd[index];
1974 index += 1;
1975 j = 0;
1976 Length -= (3+i);
1977 while(i--) {
1978 if ((phba->sli_rev == LPFC_SLI_REV4) &&
1979 (phba->sli4_hba.pport_name_sta ==
1980 LPFC_SLI4_PPNAME_GET)) {
1981 j++;
1982 index++;
1983 } else
1984 phba->Port[j++] = vpd[index++];
1985 if (j == 19)
1986 break;
1987 }
1988 if ((phba->sli_rev != LPFC_SLI_REV4) ||
1989 (phba->sli4_hba.pport_name_sta ==
1990 LPFC_SLI4_PPNAME_NON))
1991 phba->Port[j] = 0;
1992 continue;
1993 }
1994 else {
1995 index += 2;
1996 i = vpd[index];
1997 index += 1;
1998 index += i;
1999 Length -= (3 + i);
2000 }
2001 }
2002 finished = 0;
2003 break;
2004 case 0x78:
2005 finished = 1;
2006 break;
2007 default:
2008 index ++;
2009 break;
2010 }
2011 }
2012
2013 return(1);
2014}
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028static void
2029lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
2030{
2031 lpfc_vpd_t *vp;
2032 uint16_t dev_id = phba->pcidev->device;
2033 int max_speed;
2034 int GE = 0;
2035 int oneConnect = 0;
2036 struct {
2037 char *name;
2038 char *bus;
2039 char *function;
2040 } m = {"<Unknown>", "", ""};
2041
2042 if (mdp && mdp[0] != '\0'
2043 && descp && descp[0] != '\0')
2044 return;
2045
2046 if (phba->lmt & LMT_32Gb)
2047 max_speed = 32;
2048 else if (phba->lmt & LMT_16Gb)
2049 max_speed = 16;
2050 else if (phba->lmt & LMT_10Gb)
2051 max_speed = 10;
2052 else if (phba->lmt & LMT_8Gb)
2053 max_speed = 8;
2054 else if (phba->lmt & LMT_4Gb)
2055 max_speed = 4;
2056 else if (phba->lmt & LMT_2Gb)
2057 max_speed = 2;
2058 else if (phba->lmt & LMT_1Gb)
2059 max_speed = 1;
2060 else
2061 max_speed = 0;
2062
2063 vp = &phba->vpd;
2064
2065 switch (dev_id) {
2066 case PCI_DEVICE_ID_FIREFLY:
2067 m = (typeof(m)){"LP6000", "PCI",
2068 "Obsolete, Unsupported Fibre Channel Adapter"};
2069 break;
2070 case PCI_DEVICE_ID_SUPERFLY:
2071 if (vp->rev.biuRev >= 1 && vp->rev.biuRev <= 3)
2072 m = (typeof(m)){"LP7000", "PCI", ""};
2073 else
2074 m = (typeof(m)){"LP7000E", "PCI", ""};
2075 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
2076 break;
2077 case PCI_DEVICE_ID_DRAGONFLY:
2078 m = (typeof(m)){"LP8000", "PCI",
2079 "Obsolete, Unsupported Fibre Channel Adapter"};
2080 break;
2081 case PCI_DEVICE_ID_CENTAUR:
2082 if (FC_JEDEC_ID(vp->rev.biuRev) == CENTAUR_2G_JEDEC_ID)
2083 m = (typeof(m)){"LP9002", "PCI", ""};
2084 else
2085 m = (typeof(m)){"LP9000", "PCI", ""};
2086 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
2087 break;
2088 case PCI_DEVICE_ID_RFLY:
2089 m = (typeof(m)){"LP952", "PCI",
2090 "Obsolete, Unsupported Fibre Channel Adapter"};
2091 break;
2092 case PCI_DEVICE_ID_PEGASUS:
2093 m = (typeof(m)){"LP9802", "PCI-X",
2094 "Obsolete, Unsupported Fibre Channel Adapter"};
2095 break;
2096 case PCI_DEVICE_ID_THOR:
2097 m = (typeof(m)){"LP10000", "PCI-X",
2098 "Obsolete, Unsupported Fibre Channel Adapter"};
2099 break;
2100 case PCI_DEVICE_ID_VIPER:
2101 m = (typeof(m)){"LPX1000", "PCI-X",
2102 "Obsolete, Unsupported Fibre Channel Adapter"};
2103 break;
2104 case PCI_DEVICE_ID_PFLY:
2105 m = (typeof(m)){"LP982", "PCI-X",
2106 "Obsolete, Unsupported Fibre Channel Adapter"};
2107 break;
2108 case PCI_DEVICE_ID_TFLY:
2109 m = (typeof(m)){"LP1050", "PCI-X",
2110 "Obsolete, Unsupported Fibre Channel Adapter"};
2111 break;
2112 case PCI_DEVICE_ID_HELIOS:
2113 m = (typeof(m)){"LP11000", "PCI-X2",
2114 "Obsolete, Unsupported Fibre Channel Adapter"};
2115 break;
2116 case PCI_DEVICE_ID_HELIOS_SCSP:
2117 m = (typeof(m)){"LP11000-SP", "PCI-X2",
2118 "Obsolete, Unsupported Fibre Channel Adapter"};
2119 break;
2120 case PCI_DEVICE_ID_HELIOS_DCSP:
2121 m = (typeof(m)){"LP11002-SP", "PCI-X2",
2122 "Obsolete, Unsupported Fibre Channel Adapter"};
2123 break;
2124 case PCI_DEVICE_ID_NEPTUNE:
2125 m = (typeof(m)){"LPe1000", "PCIe",
2126 "Obsolete, Unsupported Fibre Channel Adapter"};
2127 break;
2128 case PCI_DEVICE_ID_NEPTUNE_SCSP:
2129 m = (typeof(m)){"LPe1000-SP", "PCIe",
2130 "Obsolete, Unsupported Fibre Channel Adapter"};
2131 break;
2132 case PCI_DEVICE_ID_NEPTUNE_DCSP:
2133 m = (typeof(m)){"LPe1002-SP", "PCIe",
2134 "Obsolete, Unsupported Fibre Channel Adapter"};
2135 break;
2136 case PCI_DEVICE_ID_BMID:
2137 m = (typeof(m)){"LP1150", "PCI-X2", "Fibre Channel Adapter"};
2138 break;
2139 case PCI_DEVICE_ID_BSMB:
2140 m = (typeof(m)){"LP111", "PCI-X2",
2141 "Obsolete, Unsupported Fibre Channel Adapter"};
2142 break;
2143 case PCI_DEVICE_ID_ZEPHYR:
2144 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
2145 break;
2146 case PCI_DEVICE_ID_ZEPHYR_SCSP:
2147 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
2148 break;
2149 case PCI_DEVICE_ID_ZEPHYR_DCSP:
2150 m = (typeof(m)){"LP2105", "PCIe", "FCoE Adapter"};
2151 GE = 1;
2152 break;
2153 case PCI_DEVICE_ID_ZMID:
2154 m = (typeof(m)){"LPe1150", "PCIe", "Fibre Channel Adapter"};
2155 break;
2156 case PCI_DEVICE_ID_ZSMB:
2157 m = (typeof(m)){"LPe111", "PCIe", "Fibre Channel Adapter"};
2158 break;
2159 case PCI_DEVICE_ID_LP101:
2160 m = (typeof(m)){"LP101", "PCI-X",
2161 "Obsolete, Unsupported Fibre Channel Adapter"};
2162 break;
2163 case PCI_DEVICE_ID_LP10000S:
2164 m = (typeof(m)){"LP10000-S", "PCI",
2165 "Obsolete, Unsupported Fibre Channel Adapter"};
2166 break;
2167 case PCI_DEVICE_ID_LP11000S:
2168 m = (typeof(m)){"LP11000-S", "PCI-X2",
2169 "Obsolete, Unsupported Fibre Channel Adapter"};
2170 break;
2171 case PCI_DEVICE_ID_LPE11000S:
2172 m = (typeof(m)){"LPe11000-S", "PCIe",
2173 "Obsolete, Unsupported Fibre Channel Adapter"};
2174 break;
2175 case PCI_DEVICE_ID_SAT:
2176 m = (typeof(m)){"LPe12000", "PCIe", "Fibre Channel Adapter"};
2177 break;
2178 case PCI_DEVICE_ID_SAT_MID:
2179 m = (typeof(m)){"LPe1250", "PCIe", "Fibre Channel Adapter"};
2180 break;
2181 case PCI_DEVICE_ID_SAT_SMB:
2182 m = (typeof(m)){"LPe121", "PCIe", "Fibre Channel Adapter"};
2183 break;
2184 case PCI_DEVICE_ID_SAT_DCSP:
2185 m = (typeof(m)){"LPe12002-SP", "PCIe", "Fibre Channel Adapter"};
2186 break;
2187 case PCI_DEVICE_ID_SAT_SCSP:
2188 m = (typeof(m)){"LPe12000-SP", "PCIe", "Fibre Channel Adapter"};
2189 break;
2190 case PCI_DEVICE_ID_SAT_S:
2191 m = (typeof(m)){"LPe12000-S", "PCIe", "Fibre Channel Adapter"};
2192 break;
2193 case PCI_DEVICE_ID_HORNET:
2194 m = (typeof(m)){"LP21000", "PCIe",
2195 "Obsolete, Unsupported FCoE Adapter"};
2196 GE = 1;
2197 break;
2198 case PCI_DEVICE_ID_PROTEUS_VF:
2199 m = (typeof(m)){"LPev12000", "PCIe IOV",
2200 "Obsolete, Unsupported Fibre Channel Adapter"};
2201 break;
2202 case PCI_DEVICE_ID_PROTEUS_PF:
2203 m = (typeof(m)){"LPev12000", "PCIe IOV",
2204 "Obsolete, Unsupported Fibre Channel Adapter"};
2205 break;
2206 case PCI_DEVICE_ID_PROTEUS_S:
2207 m = (typeof(m)){"LPemv12002-S", "PCIe IOV",
2208 "Obsolete, Unsupported Fibre Channel Adapter"};
2209 break;
2210 case PCI_DEVICE_ID_TIGERSHARK:
2211 oneConnect = 1;
2212 m = (typeof(m)){"OCe10100", "PCIe", "FCoE"};
2213 break;
2214 case PCI_DEVICE_ID_TOMCAT:
2215 oneConnect = 1;
2216 m = (typeof(m)){"OCe11100", "PCIe", "FCoE"};
2217 break;
2218 case PCI_DEVICE_ID_FALCON:
2219 m = (typeof(m)){"LPSe12002-ML1-E", "PCIe",
2220 "EmulexSecure Fibre"};
2221 break;
2222 case PCI_DEVICE_ID_BALIUS:
2223 m = (typeof(m)){"LPVe12002", "PCIe Shared I/O",
2224 "Obsolete, Unsupported Fibre Channel Adapter"};
2225 break;
2226 case PCI_DEVICE_ID_LANCER_FC:
2227 m = (typeof(m)){"LPe16000", "PCIe", "Fibre Channel Adapter"};
2228 break;
2229 case PCI_DEVICE_ID_LANCER_FC_VF:
2230 m = (typeof(m)){"LPe16000", "PCIe",
2231 "Obsolete, Unsupported Fibre Channel Adapter"};
2232 break;
2233 case PCI_DEVICE_ID_LANCER_FCOE:
2234 oneConnect = 1;
2235 m = (typeof(m)){"OCe15100", "PCIe", "FCoE"};
2236 break;
2237 case PCI_DEVICE_ID_LANCER_FCOE_VF:
2238 oneConnect = 1;
2239 m = (typeof(m)){"OCe15100", "PCIe",
2240 "Obsolete, Unsupported FCoE"};
2241 break;
2242 case PCI_DEVICE_ID_LANCER_G6_FC:
2243 m = (typeof(m)){"LPe32000", "PCIe", "Fibre Channel Adapter"};
2244 break;
2245 case PCI_DEVICE_ID_SKYHAWK:
2246 case PCI_DEVICE_ID_SKYHAWK_VF:
2247 oneConnect = 1;
2248 m = (typeof(m)){"OCe14000", "PCIe", "FCoE"};
2249 break;
2250 default:
2251 m = (typeof(m)){"Unknown", "", ""};
2252 break;
2253 }
2254
2255 if (mdp && mdp[0] == '\0')
2256 snprintf(mdp, 79,"%s", m.name);
2257
2258
2259
2260
2261 if (descp && descp[0] == '\0') {
2262 if (oneConnect)
2263 snprintf(descp, 255,
2264 "Emulex OneConnect %s, %s Initiator %s",
2265 m.name, m.function,
2266 phba->Port);
2267 else if (max_speed == 0)
2268 snprintf(descp, 255,
2269 "Emulex %s %s %s",
2270 m.name, m.bus, m.function);
2271 else
2272 snprintf(descp, 255,
2273 "Emulex %s %d%s %s %s",
2274 m.name, max_speed, (GE) ? "GE" : "Gb",
2275 m.bus, m.function);
2276 }
2277}
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291int
2292lpfc_post_buffer(struct lpfc_hba *phba, struct lpfc_sli_ring *pring, int cnt)
2293{
2294 IOCB_t *icmd;
2295 struct lpfc_iocbq *iocb;
2296 struct lpfc_dmabuf *mp1, *mp2;
2297
2298 cnt += pring->missbufcnt;
2299
2300
2301 while (cnt > 0) {
2302
2303 iocb = lpfc_sli_get_iocbq(phba);
2304 if (iocb == NULL) {
2305 pring->missbufcnt = cnt;
2306 return cnt;
2307 }
2308 icmd = &iocb->iocb;
2309
2310
2311
2312 mp1 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2313 if (mp1)
2314 mp1->virt = lpfc_mbuf_alloc(phba, MEM_PRI, &mp1->phys);
2315 if (!mp1 || !mp1->virt) {
2316 kfree(mp1);
2317 lpfc_sli_release_iocbq(phba, iocb);
2318 pring->missbufcnt = cnt;
2319 return cnt;
2320 }
2321
2322 INIT_LIST_HEAD(&mp1->list);
2323
2324 if (cnt > 1) {
2325 mp2 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2326 if (mp2)
2327 mp2->virt = lpfc_mbuf_alloc(phba, MEM_PRI,
2328 &mp2->phys);
2329 if (!mp2 || !mp2->virt) {
2330 kfree(mp2);
2331 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2332 kfree(mp1);
2333 lpfc_sli_release_iocbq(phba, iocb);
2334 pring->missbufcnt = cnt;
2335 return cnt;
2336 }
2337
2338 INIT_LIST_HEAD(&mp2->list);
2339 } else {
2340 mp2 = NULL;
2341 }
2342
2343 icmd->un.cont64[0].addrHigh = putPaddrHigh(mp1->phys);
2344 icmd->un.cont64[0].addrLow = putPaddrLow(mp1->phys);
2345 icmd->un.cont64[0].tus.f.bdeSize = FCELSSIZE;
2346 icmd->ulpBdeCount = 1;
2347 cnt--;
2348 if (mp2) {
2349 icmd->un.cont64[1].addrHigh = putPaddrHigh(mp2->phys);
2350 icmd->un.cont64[1].addrLow = putPaddrLow(mp2->phys);
2351 icmd->un.cont64[1].tus.f.bdeSize = FCELSSIZE;
2352 cnt--;
2353 icmd->ulpBdeCount = 2;
2354 }
2355
2356 icmd->ulpCommand = CMD_QUE_RING_BUF64_CN;
2357 icmd->ulpLe = 1;
2358
2359 if (lpfc_sli_issue_iocb(phba, pring->ringno, iocb, 0) ==
2360 IOCB_ERROR) {
2361 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2362 kfree(mp1);
2363 cnt++;
2364 if (mp2) {
2365 lpfc_mbuf_free(phba, mp2->virt, mp2->phys);
2366 kfree(mp2);
2367 cnt++;
2368 }
2369 lpfc_sli_release_iocbq(phba, iocb);
2370 pring->missbufcnt = cnt;
2371 return cnt;
2372 }
2373 lpfc_sli_ringpostbuf_put(phba, pring, mp1);
2374 if (mp2)
2375 lpfc_sli_ringpostbuf_put(phba, pring, mp2);
2376 }
2377 pring->missbufcnt = 0;
2378 return 0;
2379}
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392static int
2393lpfc_post_rcv_buf(struct lpfc_hba *phba)
2394{
2395 struct lpfc_sli *psli = &phba->sli;
2396
2397
2398 lpfc_post_buffer(phba, &psli->ring[LPFC_ELS_RING], LPFC_BUF_RING0);
2399
2400
2401 return 0;
2402}
2403
2404#define S(N,V) (((V)<<(N))|((V)>>(32-(N))))
2405
2406
2407
2408
2409
2410
2411
2412
2413static void
2414lpfc_sha_init(uint32_t * HashResultPointer)
2415{
2416 HashResultPointer[0] = 0x67452301;
2417 HashResultPointer[1] = 0xEFCDAB89;
2418 HashResultPointer[2] = 0x98BADCFE;
2419 HashResultPointer[3] = 0x10325476;
2420 HashResultPointer[4] = 0xC3D2E1F0;
2421}
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433static void
2434lpfc_sha_iterate(uint32_t * HashResultPointer, uint32_t * HashWorkingPointer)
2435{
2436 int t;
2437 uint32_t TEMP;
2438 uint32_t A, B, C, D, E;
2439 t = 16;
2440 do {
2441 HashWorkingPointer[t] =
2442 S(1,
2443 HashWorkingPointer[t - 3] ^ HashWorkingPointer[t -
2444 8] ^
2445 HashWorkingPointer[t - 14] ^ HashWorkingPointer[t - 16]);
2446 } while (++t <= 79);
2447 t = 0;
2448 A = HashResultPointer[0];
2449 B = HashResultPointer[1];
2450 C = HashResultPointer[2];
2451 D = HashResultPointer[3];
2452 E = HashResultPointer[4];
2453
2454 do {
2455 if (t < 20) {
2456 TEMP = ((B & C) | ((~B) & D)) + 0x5A827999;
2457 } else if (t < 40) {
2458 TEMP = (B ^ C ^ D) + 0x6ED9EBA1;
2459 } else if (t < 60) {
2460 TEMP = ((B & C) | (B & D) | (C & D)) + 0x8F1BBCDC;
2461 } else {
2462 TEMP = (B ^ C ^ D) + 0xCA62C1D6;
2463 }
2464 TEMP += S(5, A) + E + HashWorkingPointer[t];
2465 E = D;
2466 D = C;
2467 C = S(30, B);
2468 B = A;
2469 A = TEMP;
2470 } while (++t <= 79);
2471
2472 HashResultPointer[0] += A;
2473 HashResultPointer[1] += B;
2474 HashResultPointer[2] += C;
2475 HashResultPointer[3] += D;
2476 HashResultPointer[4] += E;
2477
2478}
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490static void
2491lpfc_challenge_key(uint32_t * RandomChallenge, uint32_t * HashWorking)
2492{
2493 *HashWorking = (*RandomChallenge ^ *HashWorking);
2494}
2495
2496
2497
2498
2499
2500
2501
2502
2503void
2504lpfc_hba_init(struct lpfc_hba *phba, uint32_t *hbainit)
2505{
2506 int t;
2507 uint32_t *HashWorking;
2508 uint32_t *pwwnn = (uint32_t *) phba->wwnn;
2509
2510 HashWorking = kcalloc(80, sizeof(uint32_t), GFP_KERNEL);
2511 if (!HashWorking)
2512 return;
2513
2514 HashWorking[0] = HashWorking[78] = *pwwnn++;
2515 HashWorking[1] = HashWorking[79] = *pwwnn;
2516
2517 for (t = 0; t < 7; t++)
2518 lpfc_challenge_key(phba->RandomData + t, HashWorking + t);
2519
2520 lpfc_sha_init(hbainit);
2521 lpfc_sha_iterate(hbainit, HashWorking);
2522 kfree(HashWorking);
2523}
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534void
2535lpfc_cleanup(struct lpfc_vport *vport)
2536{
2537 struct lpfc_hba *phba = vport->phba;
2538 struct lpfc_nodelist *ndlp, *next_ndlp;
2539 int i = 0;
2540
2541 if (phba->link_state > LPFC_LINK_DOWN)
2542 lpfc_port_link_failure(vport);
2543
2544 list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
2545 if (!NLP_CHK_NODE_ACT(ndlp)) {
2546 ndlp = lpfc_enable_node(vport, ndlp,
2547 NLP_STE_UNUSED_NODE);
2548 if (!ndlp)
2549 continue;
2550 spin_lock_irq(&phba->ndlp_lock);
2551 NLP_SET_FREE_REQ(ndlp);
2552 spin_unlock_irq(&phba->ndlp_lock);
2553
2554 lpfc_nlp_put(ndlp);
2555 continue;
2556 }
2557 spin_lock_irq(&phba->ndlp_lock);
2558 if (NLP_CHK_FREE_REQ(ndlp)) {
2559
2560 spin_unlock_irq(&phba->ndlp_lock);
2561 continue;
2562 } else
2563
2564 NLP_SET_FREE_REQ(ndlp);
2565 spin_unlock_irq(&phba->ndlp_lock);
2566
2567 if (vport->port_type != LPFC_PHYSICAL_PORT &&
2568 ndlp->nlp_DID == Fabric_DID) {
2569
2570 lpfc_nlp_put(ndlp);
2571 continue;
2572 }
2573
2574
2575
2576
2577 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
2578 lpfc_nlp_put(ndlp);
2579 continue;
2580 }
2581
2582 if (ndlp->nlp_type & NLP_FABRIC)
2583 lpfc_disc_state_machine(vport, ndlp, NULL,
2584 NLP_EVT_DEVICE_RECOVERY);
2585
2586 lpfc_disc_state_machine(vport, ndlp, NULL,
2587 NLP_EVT_DEVICE_RM);
2588 }
2589
2590
2591
2592
2593
2594 while (!list_empty(&vport->fc_nodes)) {
2595 if (i++ > 3000) {
2596 lpfc_printf_vlog(vport, KERN_ERR, LOG_DISCOVERY,
2597 "0233 Nodelist not empty\n");
2598 list_for_each_entry_safe(ndlp, next_ndlp,
2599 &vport->fc_nodes, nlp_listp) {
2600 lpfc_printf_vlog(ndlp->vport, KERN_ERR,
2601 LOG_NODE,
2602 "0282 did:x%x ndlp:x%p "
2603 "usgmap:x%x refcnt:%d\n",
2604 ndlp->nlp_DID, (void *)ndlp,
2605 ndlp->nlp_usg_map,
2606 atomic_read(
2607 &ndlp->kref.refcount));
2608 }
2609 break;
2610 }
2611
2612
2613 msleep(10);
2614 }
2615 lpfc_cleanup_vports_rrqs(vport, NULL);
2616}
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626void
2627lpfc_stop_vport_timers(struct lpfc_vport *vport)
2628{
2629 del_timer_sync(&vport->els_tmofunc);
2630 del_timer_sync(&vport->delayed_disc_tmo);
2631 lpfc_can_disctmo(vport);
2632 return;
2633}
2634
2635
2636
2637
2638
2639
2640
2641
2642void
2643__lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2644{
2645
2646 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
2647
2648
2649 del_timer(&phba->fcf.redisc_wait);
2650}
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661void
2662lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2663{
2664 spin_lock_irq(&phba->hbalock);
2665 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
2666
2667 spin_unlock_irq(&phba->hbalock);
2668 return;
2669 }
2670 __lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
2671
2672 phba->fcf.fcf_flag &= ~(FCF_DEAD_DISC | FCF_ACVL_DISC);
2673 spin_unlock_irq(&phba->hbalock);
2674}
2675
2676
2677
2678
2679
2680
2681
2682
2683void
2684lpfc_stop_hba_timers(struct lpfc_hba *phba)
2685{
2686 lpfc_stop_vport_timers(phba->pport);
2687 del_timer_sync(&phba->sli.mbox_tmo);
2688 del_timer_sync(&phba->fabric_block_timer);
2689 del_timer_sync(&phba->eratt_poll);
2690 del_timer_sync(&phba->hb_tmofunc);
2691 if (phba->sli_rev == LPFC_SLI_REV4) {
2692 del_timer_sync(&phba->rrq_tmr);
2693 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
2694 }
2695 phba->hb_outstanding = 0;
2696
2697 switch (phba->pci_dev_grp) {
2698 case LPFC_PCI_DEV_LP:
2699
2700 del_timer_sync(&phba->fcp_poll_timer);
2701 break;
2702 case LPFC_PCI_DEV_OC:
2703
2704 lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
2705 break;
2706 default:
2707 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2708 "0297 Invalid device group (x%x)\n",
2709 phba->pci_dev_grp);
2710 break;
2711 }
2712 return;
2713}
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725static void
2726lpfc_block_mgmt_io(struct lpfc_hba *phba, int mbx_action)
2727{
2728 unsigned long iflag;
2729 uint8_t actcmd = MBX_HEARTBEAT;
2730 unsigned long timeout;
2731
2732 spin_lock_irqsave(&phba->hbalock, iflag);
2733 phba->sli.sli_flag |= LPFC_BLOCK_MGMT_IO;
2734 spin_unlock_irqrestore(&phba->hbalock, iflag);
2735 if (mbx_action == LPFC_MBX_NO_WAIT)
2736 return;
2737 timeout = msecs_to_jiffies(LPFC_MBOX_TMO * 1000) + jiffies;
2738 spin_lock_irqsave(&phba->hbalock, iflag);
2739 if (phba->sli.mbox_active) {
2740 actcmd = phba->sli.mbox_active->u.mb.mbxCommand;
2741
2742
2743
2744 timeout = msecs_to_jiffies(lpfc_mbox_tmo_val(phba,
2745 phba->sli.mbox_active) * 1000) + jiffies;
2746 }
2747 spin_unlock_irqrestore(&phba->hbalock, iflag);
2748
2749
2750 while (phba->sli.mbox_active) {
2751
2752 msleep(2);
2753 if (time_after(jiffies, timeout)) {
2754 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
2755 "2813 Mgmt IO is Blocked %x "
2756 "- mbox cmd %x still active\n",
2757 phba->sli.sli_flag, actcmd);
2758 break;
2759 }
2760 }
2761}
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771void
2772lpfc_sli4_node_prep(struct lpfc_hba *phba)
2773{
2774 struct lpfc_nodelist *ndlp, *next_ndlp;
2775 struct lpfc_vport **vports;
2776 int i;
2777
2778 if (phba->sli_rev != LPFC_SLI_REV4)
2779 return;
2780
2781 vports = lpfc_create_vport_work_array(phba);
2782 if (vports != NULL) {
2783 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
2784 if (vports[i]->load_flag & FC_UNLOADING)
2785 continue;
2786
2787 list_for_each_entry_safe(ndlp, next_ndlp,
2788 &vports[i]->fc_nodes,
2789 nlp_listp) {
2790 if (NLP_CHK_NODE_ACT(ndlp)) {
2791 ndlp->nlp_rpi =
2792 lpfc_sli4_alloc_rpi(phba);
2793 lpfc_printf_vlog(ndlp->vport, KERN_INFO,
2794 LOG_NODE,
2795 "0009 rpi:%x DID:%x "
2796 "flg:%x map:%x %p\n",
2797 ndlp->nlp_rpi,
2798 ndlp->nlp_DID,
2799 ndlp->nlp_flag,
2800 ndlp->nlp_usg_map,
2801 ndlp);
2802 }
2803 }
2804 }
2805 }
2806 lpfc_destroy_vport_work_array(phba, vports);
2807}
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821int
2822lpfc_online(struct lpfc_hba *phba)
2823{
2824 struct lpfc_vport *vport;
2825 struct lpfc_vport **vports;
2826 int i;
2827 bool vpis_cleared = false;
2828
2829 if (!phba)
2830 return 0;
2831 vport = phba->pport;
2832
2833 if (!(vport->fc_flag & FC_OFFLINE_MODE))
2834 return 0;
2835
2836 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
2837 "0458 Bring Adapter online\n");
2838
2839 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
2840
2841 if (!lpfc_sli_queue_setup(phba)) {
2842 lpfc_unblock_mgmt_io(phba);
2843 return 1;
2844 }
2845
2846 if (phba->sli_rev == LPFC_SLI_REV4) {
2847 if (lpfc_sli4_hba_setup(phba)) {
2848 lpfc_unblock_mgmt_io(phba);
2849 return 1;
2850 }
2851 spin_lock_irq(&phba->hbalock);
2852 if (!phba->sli4_hba.max_cfg_param.vpi_used)
2853 vpis_cleared = true;
2854 spin_unlock_irq(&phba->hbalock);
2855 } else {
2856 if (lpfc_sli_hba_setup(phba)) {
2857 lpfc_unblock_mgmt_io(phba);
2858 return 1;
2859 }
2860 }
2861
2862 vports = lpfc_create_vport_work_array(phba);
2863 if (vports != NULL) {
2864 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
2865 struct Scsi_Host *shost;
2866 shost = lpfc_shost_from_vport(vports[i]);
2867 spin_lock_irq(shost->host_lock);
2868 vports[i]->fc_flag &= ~FC_OFFLINE_MODE;
2869 if (phba->sli3_options & LPFC_SLI3_NPIV_ENABLED)
2870 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
2871 if (phba->sli_rev == LPFC_SLI_REV4) {
2872 vports[i]->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
2873 if ((vpis_cleared) &&
2874 (vports[i]->port_type !=
2875 LPFC_PHYSICAL_PORT))
2876 vports[i]->vpi = 0;
2877 }
2878 spin_unlock_irq(shost->host_lock);
2879 }
2880 }
2881 lpfc_destroy_vport_work_array(phba, vports);
2882
2883 lpfc_unblock_mgmt_io(phba);
2884 return 0;
2885}
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898void
2899lpfc_unblock_mgmt_io(struct lpfc_hba * phba)
2900{
2901 unsigned long iflag;
2902
2903 spin_lock_irqsave(&phba->hbalock, iflag);
2904 phba->sli.sli_flag &= ~LPFC_BLOCK_MGMT_IO;
2905 spin_unlock_irqrestore(&phba->hbalock, iflag);
2906}
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916void
2917lpfc_offline_prep(struct lpfc_hba *phba, int mbx_action)
2918{
2919 struct lpfc_vport *vport = phba->pport;
2920 struct lpfc_nodelist *ndlp, *next_ndlp;
2921 struct lpfc_vport **vports;
2922 struct Scsi_Host *shost;
2923 int i;
2924
2925 if (vport->fc_flag & FC_OFFLINE_MODE)
2926 return;
2927
2928 lpfc_block_mgmt_io(phba, mbx_action);
2929
2930 lpfc_linkdown(phba);
2931
2932
2933 vports = lpfc_create_vport_work_array(phba);
2934 if (vports != NULL) {
2935 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
2936 if (vports[i]->load_flag & FC_UNLOADING)
2937 continue;
2938 shost = lpfc_shost_from_vport(vports[i]);
2939 spin_lock_irq(shost->host_lock);
2940 vports[i]->vpi_state &= ~LPFC_VPI_REGISTERED;
2941 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
2942 vports[i]->fc_flag &= ~FC_VFI_REGISTERED;
2943 spin_unlock_irq(shost->host_lock);
2944
2945 shost = lpfc_shost_from_vport(vports[i]);
2946 list_for_each_entry_safe(ndlp, next_ndlp,
2947 &vports[i]->fc_nodes,
2948 nlp_listp) {
2949 if (!NLP_CHK_NODE_ACT(ndlp))
2950 continue;
2951 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE)
2952 continue;
2953 if (ndlp->nlp_type & NLP_FABRIC) {
2954 lpfc_disc_state_machine(vports[i], ndlp,
2955 NULL, NLP_EVT_DEVICE_RECOVERY);
2956 lpfc_disc_state_machine(vports[i], ndlp,
2957 NULL, NLP_EVT_DEVICE_RM);
2958 }
2959 spin_lock_irq(shost->host_lock);
2960 ndlp->nlp_flag &= ~NLP_NPR_ADISC;
2961 spin_unlock_irq(shost->host_lock);
2962
2963
2964
2965
2966
2967 if (phba->sli_rev == LPFC_SLI_REV4) {
2968 lpfc_printf_vlog(ndlp->vport,
2969 KERN_INFO, LOG_NODE,
2970 "0011 lpfc_offline: "
2971 "ndlp:x%p did %x "
2972 "usgmap:x%x rpi:%x\n",
2973 ndlp, ndlp->nlp_DID,
2974 ndlp->nlp_usg_map,
2975 ndlp->nlp_rpi);
2976
2977 lpfc_sli4_free_rpi(phba, ndlp->nlp_rpi);
2978 }
2979 lpfc_unreg_rpi(vports[i], ndlp);
2980 }
2981 }
2982 }
2983 lpfc_destroy_vport_work_array(phba, vports);
2984
2985 lpfc_sli_mbox_sys_shutdown(phba, mbx_action);
2986}
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996void
2997lpfc_offline(struct lpfc_hba *phba)
2998{
2999 struct Scsi_Host *shost;
3000 struct lpfc_vport **vports;
3001 int i;
3002
3003 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
3004 return;
3005
3006
3007 lpfc_stop_port(phba);
3008 vports = lpfc_create_vport_work_array(phba);
3009 if (vports != NULL)
3010 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
3011 lpfc_stop_vport_timers(vports[i]);
3012 lpfc_destroy_vport_work_array(phba, vports);
3013 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
3014 "0460 Bring Adapter offline\n");
3015
3016
3017 lpfc_sli_hba_down(phba);
3018 spin_lock_irq(&phba->hbalock);
3019 phba->work_ha = 0;
3020 spin_unlock_irq(&phba->hbalock);
3021 vports = lpfc_create_vport_work_array(phba);
3022 if (vports != NULL)
3023 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3024 shost = lpfc_shost_from_vport(vports[i]);
3025 spin_lock_irq(shost->host_lock);
3026 vports[i]->work_port_events = 0;
3027 vports[i]->fc_flag |= FC_OFFLINE_MODE;
3028 spin_unlock_irq(shost->host_lock);
3029 }
3030 lpfc_destroy_vport_work_array(phba, vports);
3031}
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041static void
3042lpfc_scsi_free(struct lpfc_hba *phba)
3043{
3044 struct lpfc_scsi_buf *sb, *sb_next;
3045 struct lpfc_iocbq *io, *io_next;
3046
3047 spin_lock_irq(&phba->hbalock);
3048
3049
3050
3051 spin_lock(&phba->scsi_buf_list_put_lock);
3052 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_put,
3053 list) {
3054 list_del(&sb->list);
3055 pci_pool_free(phba->lpfc_scsi_dma_buf_pool, sb->data,
3056 sb->dma_handle);
3057 kfree(sb);
3058 phba->total_scsi_bufs--;
3059 }
3060 spin_unlock(&phba->scsi_buf_list_put_lock);
3061
3062 spin_lock(&phba->scsi_buf_list_get_lock);
3063 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_get,
3064 list) {
3065 list_del(&sb->list);
3066 pci_pool_free(phba->lpfc_scsi_dma_buf_pool, sb->data,
3067 sb->dma_handle);
3068 kfree(sb);
3069 phba->total_scsi_bufs--;
3070 }
3071 spin_unlock(&phba->scsi_buf_list_get_lock);
3072
3073
3074 list_for_each_entry_safe(io, io_next, &phba->lpfc_iocb_list, list) {
3075 list_del(&io->list);
3076 kfree(io);
3077 phba->total_iocbq_bufs--;
3078 }
3079
3080 spin_unlock_irq(&phba->hbalock);
3081}
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095int
3096lpfc_sli4_xri_sgl_update(struct lpfc_hba *phba)
3097{
3098 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
3099 struct lpfc_scsi_buf *psb = NULL, *psb_next = NULL;
3100 uint16_t i, lxri, xri_cnt, els_xri_cnt, scsi_xri_cnt;
3101 LIST_HEAD(els_sgl_list);
3102 LIST_HEAD(scsi_sgl_list);
3103 int rc;
3104 struct lpfc_sli_ring *pring = &phba->sli.ring[LPFC_ELS_RING];
3105
3106
3107
3108
3109 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
3110 if (els_xri_cnt > phba->sli4_hba.els_xri_cnt) {
3111
3112 xri_cnt = els_xri_cnt - phba->sli4_hba.els_xri_cnt;
3113 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3114 "3157 ELS xri-sgl count increased from "
3115 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3116 els_xri_cnt);
3117
3118 for (i = 0; i < xri_cnt; i++) {
3119 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3120 GFP_KERNEL);
3121 if (sglq_entry == NULL) {
3122 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3123 "2562 Failure to allocate an "
3124 "ELS sgl entry:%d\n", i);
3125 rc = -ENOMEM;
3126 goto out_free_mem;
3127 }
3128 sglq_entry->buff_type = GEN_BUFF_TYPE;
3129 sglq_entry->virt = lpfc_mbuf_alloc(phba, 0,
3130 &sglq_entry->phys);
3131 if (sglq_entry->virt == NULL) {
3132 kfree(sglq_entry);
3133 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3134 "2563 Failure to allocate an "
3135 "ELS mbuf:%d\n", i);
3136 rc = -ENOMEM;
3137 goto out_free_mem;
3138 }
3139 sglq_entry->sgl = sglq_entry->virt;
3140 memset(sglq_entry->sgl, 0, LPFC_BPL_SIZE);
3141 sglq_entry->state = SGL_FREED;
3142 list_add_tail(&sglq_entry->list, &els_sgl_list);
3143 }
3144 spin_lock_irq(&phba->hbalock);
3145 spin_lock(&pring->ring_lock);
3146 list_splice_init(&els_sgl_list, &phba->sli4_hba.lpfc_sgl_list);
3147 spin_unlock(&pring->ring_lock);
3148 spin_unlock_irq(&phba->hbalock);
3149 } else if (els_xri_cnt < phba->sli4_hba.els_xri_cnt) {
3150
3151 xri_cnt = phba->sli4_hba.els_xri_cnt - els_xri_cnt;
3152 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3153 "3158 ELS xri-sgl count decreased from "
3154 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3155 els_xri_cnt);
3156 spin_lock_irq(&phba->hbalock);
3157 spin_lock(&pring->ring_lock);
3158 list_splice_init(&phba->sli4_hba.lpfc_sgl_list, &els_sgl_list);
3159 spin_unlock(&pring->ring_lock);
3160 spin_unlock_irq(&phba->hbalock);
3161
3162 for (i = 0; i < xri_cnt; i++) {
3163 list_remove_head(&els_sgl_list,
3164 sglq_entry, struct lpfc_sglq, list);
3165 if (sglq_entry) {
3166 lpfc_mbuf_free(phba, sglq_entry->virt,
3167 sglq_entry->phys);
3168 kfree(sglq_entry);
3169 }
3170 }
3171 spin_lock_irq(&phba->hbalock);
3172 spin_lock(&pring->ring_lock);
3173 list_splice_init(&els_sgl_list, &phba->sli4_hba.lpfc_sgl_list);
3174 spin_unlock(&pring->ring_lock);
3175 spin_unlock_irq(&phba->hbalock);
3176 } else
3177 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3178 "3163 ELS xri-sgl count unchanged: %d\n",
3179 els_xri_cnt);
3180 phba->sli4_hba.els_xri_cnt = els_xri_cnt;
3181
3182
3183 sglq_entry = NULL;
3184 sglq_entry_next = NULL;
3185 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
3186 &phba->sli4_hba.lpfc_sgl_list, list) {
3187 lxri = lpfc_sli4_next_xritag(phba);
3188 if (lxri == NO_XRI) {
3189 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3190 "2400 Failed to allocate xri for "
3191 "ELS sgl\n");
3192 rc = -ENOMEM;
3193 goto out_free_mem;
3194 }
3195 sglq_entry->sli4_lxritag = lxri;
3196 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3197 }
3198
3199
3200
3201
3202 phba->total_scsi_bufs = 0;
3203
3204
3205 phba->sli4_hba.scsi_xri_max = phba->sli4_hba.max_cfg_param.max_xri -
3206 els_xri_cnt;
3207
3208 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3209 "2401 Current allocated SCSI xri-sgl count:%d, "
3210 "maximum SCSI xri count:%d\n",
3211 phba->sli4_hba.scsi_xri_cnt,
3212 phba->sli4_hba.scsi_xri_max);
3213
3214 spin_lock_irq(&phba->scsi_buf_list_get_lock);
3215 spin_lock(&phba->scsi_buf_list_put_lock);
3216 list_splice_init(&phba->lpfc_scsi_buf_list_get, &scsi_sgl_list);
3217 list_splice(&phba->lpfc_scsi_buf_list_put, &scsi_sgl_list);
3218 spin_unlock(&phba->scsi_buf_list_put_lock);
3219 spin_unlock_irq(&phba->scsi_buf_list_get_lock);
3220
3221 if (phba->sli4_hba.scsi_xri_cnt > phba->sli4_hba.scsi_xri_max) {
3222
3223 scsi_xri_cnt = phba->sli4_hba.scsi_xri_cnt -
3224 phba->sli4_hba.scsi_xri_max;
3225
3226 for (i = 0; i < scsi_xri_cnt; i++) {
3227 list_remove_head(&scsi_sgl_list, psb,
3228 struct lpfc_scsi_buf, list);
3229 if (psb) {
3230 pci_pool_free(phba->lpfc_scsi_dma_buf_pool,
3231 psb->data, psb->dma_handle);
3232 kfree(psb);
3233 }
3234 }
3235 spin_lock_irq(&phba->scsi_buf_list_get_lock);
3236 phba->sli4_hba.scsi_xri_cnt -= scsi_xri_cnt;
3237 spin_unlock_irq(&phba->scsi_buf_list_get_lock);
3238 }
3239
3240
3241 psb = NULL;
3242 psb_next = NULL;
3243 list_for_each_entry_safe(psb, psb_next, &scsi_sgl_list, list) {
3244 lxri = lpfc_sli4_next_xritag(phba);
3245 if (lxri == NO_XRI) {
3246 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3247 "2560 Failed to allocate xri for "
3248 "scsi buffer\n");
3249 rc = -ENOMEM;
3250 goto out_free_mem;
3251 }
3252 psb->cur_iocbq.sli4_lxritag = lxri;
3253 psb->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3254 }
3255 spin_lock_irq(&phba->scsi_buf_list_get_lock);
3256 spin_lock(&phba->scsi_buf_list_put_lock);
3257 list_splice_init(&scsi_sgl_list, &phba->lpfc_scsi_buf_list_get);
3258 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
3259 spin_unlock(&phba->scsi_buf_list_put_lock);
3260 spin_unlock_irq(&phba->scsi_buf_list_get_lock);
3261
3262 return 0;
3263
3264out_free_mem:
3265 lpfc_free_els_sgl_list(phba);
3266 lpfc_scsi_free(phba);
3267 return rc;
3268}
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286struct lpfc_vport *
3287lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev)
3288{
3289 struct lpfc_vport *vport;
3290 struct Scsi_Host *shost;
3291 int error = 0;
3292
3293 if (dev != &phba->pcidev->dev) {
3294 shost = scsi_host_alloc(&lpfc_vport_template,
3295 sizeof(struct lpfc_vport));
3296 } else {
3297 if (phba->sli_rev == LPFC_SLI_REV4)
3298 shost = scsi_host_alloc(&lpfc_template,
3299 sizeof(struct lpfc_vport));
3300 else
3301 shost = scsi_host_alloc(&lpfc_template_s3,
3302 sizeof(struct lpfc_vport));
3303 }
3304 if (!shost)
3305 goto out;
3306
3307 vport = (struct lpfc_vport *) shost->hostdata;
3308 vport->phba = phba;
3309 vport->load_flag |= FC_LOADING;
3310 vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3311 vport->fc_rscn_flush = 0;
3312
3313 lpfc_get_vport_cfgparam(vport);
3314 shost->unique_id = instance;
3315 shost->max_id = LPFC_MAX_TARGET;
3316 shost->max_lun = vport->cfg_max_luns;
3317 shost->this_id = -1;
3318 shost->max_cmd_len = 16;
3319 shost->nr_hw_queues = phba->cfg_fcp_io_channel;
3320 if (phba->sli_rev == LPFC_SLI_REV4) {
3321 shost->dma_boundary =
3322 phba->sli4_hba.pc_sli4_params.sge_supp_len-1;
3323 shost->sg_tablesize = phba->cfg_sg_seg_cnt;
3324 }
3325
3326
3327
3328
3329
3330
3331 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3332 if (dev != &phba->pcidev->dev) {
3333 shost->transportt = lpfc_vport_transport_template;
3334 vport->port_type = LPFC_NPIV_PORT;
3335 } else {
3336 shost->transportt = lpfc_transport_template;
3337 vport->port_type = LPFC_PHYSICAL_PORT;
3338 }
3339
3340
3341 INIT_LIST_HEAD(&vport->fc_nodes);
3342 INIT_LIST_HEAD(&vport->rcv_buffer_list);
3343 spin_lock_init(&vport->work_port_lock);
3344
3345 init_timer(&vport->fc_disctmo);
3346 vport->fc_disctmo.function = lpfc_disc_timeout;
3347 vport->fc_disctmo.data = (unsigned long)vport;
3348
3349 init_timer(&vport->els_tmofunc);
3350 vport->els_tmofunc.function = lpfc_els_timeout;
3351 vport->els_tmofunc.data = (unsigned long)vport;
3352
3353 init_timer(&vport->delayed_disc_tmo);
3354 vport->delayed_disc_tmo.function = lpfc_delayed_disc_tmo;
3355 vport->delayed_disc_tmo.data = (unsigned long)vport;
3356
3357 error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
3358 if (error)
3359 goto out_put_shost;
3360
3361 spin_lock_irq(&phba->hbalock);
3362 list_add_tail(&vport->listentry, &phba->port_list);
3363 spin_unlock_irq(&phba->hbalock);
3364 return vport;
3365
3366out_put_shost:
3367 scsi_host_put(shost);
3368out:
3369 return NULL;
3370}
3371
3372
3373
3374
3375
3376
3377
3378
3379void
3380destroy_port(struct lpfc_vport *vport)
3381{
3382 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
3383 struct lpfc_hba *phba = vport->phba;
3384
3385 lpfc_debugfs_terminate(vport);
3386 fc_remove_host(shost);
3387 scsi_remove_host(shost);
3388
3389 spin_lock_irq(&phba->hbalock);
3390 list_del_init(&vport->listentry);
3391 spin_unlock_irq(&phba->hbalock);
3392
3393 lpfc_cleanup(vport);
3394 return;
3395}
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407int
3408lpfc_get_instance(void)
3409{
3410 int ret;
3411
3412 ret = idr_alloc(&lpfc_hba_index, NULL, 0, 0, GFP_KERNEL);
3413 return ret < 0 ? -1 : ret;
3414}
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431int lpfc_scan_finished(struct Scsi_Host *shost, unsigned long time)
3432{
3433 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
3434 struct lpfc_hba *phba = vport->phba;
3435 int stat = 0;
3436
3437 spin_lock_irq(shost->host_lock);
3438
3439 if (vport->load_flag & FC_UNLOADING) {
3440 stat = 1;
3441 goto finished;
3442 }
3443 if (time >= msecs_to_jiffies(30 * 1000)) {
3444 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3445 "0461 Scanning longer than 30 "
3446 "seconds. Continuing initialization\n");
3447 stat = 1;
3448 goto finished;
3449 }
3450 if (time >= msecs_to_jiffies(15 * 1000) &&
3451 phba->link_state <= LPFC_LINK_DOWN) {
3452 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3453 "0465 Link down longer than 15 "
3454 "seconds. Continuing initialization\n");
3455 stat = 1;
3456 goto finished;
3457 }
3458
3459 if (vport->port_state != LPFC_VPORT_READY)
3460 goto finished;
3461 if (vport->num_disc_nodes || vport->fc_prli_sent)
3462 goto finished;
3463 if (vport->fc_map_cnt == 0 && time < msecs_to_jiffies(2 * 1000))
3464 goto finished;
3465 if ((phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) != 0)
3466 goto finished;
3467
3468 stat = 1;
3469
3470finished:
3471 spin_unlock_irq(shost->host_lock);
3472 return stat;
3473}
3474
3475
3476
3477
3478
3479
3480
3481
3482void lpfc_host_attrib_init(struct Scsi_Host *shost)
3483{
3484 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
3485 struct lpfc_hba *phba = vport->phba;
3486
3487
3488
3489
3490 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
3491 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
3492 fc_host_supported_classes(shost) = FC_COS_CLASS3;
3493
3494 memset(fc_host_supported_fc4s(shost), 0,
3495 sizeof(fc_host_supported_fc4s(shost)));
3496 fc_host_supported_fc4s(shost)[2] = 1;
3497 fc_host_supported_fc4s(shost)[7] = 1;
3498
3499 lpfc_vport_symbolic_node_name(vport, fc_host_symbolic_name(shost),
3500 sizeof fc_host_symbolic_name(shost));
3501
3502 fc_host_supported_speeds(shost) = 0;
3503 if (phba->lmt & LMT_32Gb)
3504 fc_host_supported_speeds(shost) |= FC_PORTSPEED_32GBIT;
3505 if (phba->lmt & LMT_16Gb)
3506 fc_host_supported_speeds(shost) |= FC_PORTSPEED_16GBIT;
3507 if (phba->lmt & LMT_10Gb)
3508 fc_host_supported_speeds(shost) |= FC_PORTSPEED_10GBIT;
3509 if (phba->lmt & LMT_8Gb)
3510 fc_host_supported_speeds(shost) |= FC_PORTSPEED_8GBIT;
3511 if (phba->lmt & LMT_4Gb)
3512 fc_host_supported_speeds(shost) |= FC_PORTSPEED_4GBIT;
3513 if (phba->lmt & LMT_2Gb)
3514 fc_host_supported_speeds(shost) |= FC_PORTSPEED_2GBIT;
3515 if (phba->lmt & LMT_1Gb)
3516 fc_host_supported_speeds(shost) |= FC_PORTSPEED_1GBIT;
3517
3518 fc_host_maxframe_size(shost) =
3519 (((uint32_t) vport->fc_sparam.cmn.bbRcvSizeMsb & 0x0F) << 8) |
3520 (uint32_t) vport->fc_sparam.cmn.bbRcvSizeLsb;
3521
3522 fc_host_dev_loss_tmo(shost) = vport->cfg_devloss_tmo;
3523
3524
3525 memset(fc_host_active_fc4s(shost), 0,
3526 sizeof(fc_host_active_fc4s(shost)));
3527 fc_host_active_fc4s(shost)[2] = 1;
3528 fc_host_active_fc4s(shost)[7] = 1;
3529
3530 fc_host_max_npiv_vports(shost) = phba->max_vpi;
3531 spin_lock_irq(shost->host_lock);
3532 vport->load_flag &= ~FC_LOADING;
3533 spin_unlock_irq(shost->host_lock);
3534}
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544static void
3545lpfc_stop_port_s3(struct lpfc_hba *phba)
3546{
3547
3548 writel(0, phba->HCregaddr);
3549 readl(phba->HCregaddr);
3550
3551 writel(0xffffffff, phba->HAregaddr);
3552 readl(phba->HAregaddr);
3553
3554
3555 lpfc_stop_hba_timers(phba);
3556 phba->pport->work_port_events = 0;
3557}
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567static void
3568lpfc_stop_port_s4(struct lpfc_hba *phba)
3569{
3570
3571 lpfc_stop_hba_timers(phba);
3572 phba->pport->work_port_events = 0;
3573 phba->sli4_hba.intr_enable = 0;
3574}
3575
3576
3577
3578
3579
3580
3581
3582
3583void
3584lpfc_stop_port(struct lpfc_hba *phba)
3585{
3586 phba->lpfc_stop_port(phba);
3587}
3588
3589
3590
3591
3592
3593
3594
3595void
3596lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *phba)
3597{
3598 unsigned long fcf_redisc_wait_tmo =
3599 (jiffies + msecs_to_jiffies(LPFC_FCF_REDISCOVER_WAIT_TMO));
3600
3601 mod_timer(&phba->fcf.redisc_wait, fcf_redisc_wait_tmo);
3602 spin_lock_irq(&phba->hbalock);
3603
3604 phba->fcf.fcf_flag &= ~(FCF_AVAILABLE | FCF_SCAN_DONE);
3605
3606 phba->fcf.fcf_flag |= FCF_REDISC_PEND;
3607 spin_unlock_irq(&phba->hbalock);
3608}
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620static void
3621lpfc_sli4_fcf_redisc_wait_tmo(unsigned long ptr)
3622{
3623 struct lpfc_hba *phba = (struct lpfc_hba *)ptr;
3624
3625
3626 spin_lock_irq(&phba->hbalock);
3627 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
3628 spin_unlock_irq(&phba->hbalock);
3629 return;
3630 }
3631
3632 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
3633
3634 phba->fcf.fcf_flag |= FCF_REDISC_EVT;
3635 spin_unlock_irq(&phba->hbalock);
3636 lpfc_printf_log(phba, KERN_INFO, LOG_FIP,
3637 "2776 FCF rediscover quiescent timer expired\n");
3638
3639 lpfc_worker_wake_up(phba);
3640}
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653static uint16_t
3654lpfc_sli4_parse_latt_fault(struct lpfc_hba *phba,
3655 struct lpfc_acqe_link *acqe_link)
3656{
3657 uint16_t latt_fault;
3658
3659 switch (bf_get(lpfc_acqe_link_fault, acqe_link)) {
3660 case LPFC_ASYNC_LINK_FAULT_NONE:
3661 case LPFC_ASYNC_LINK_FAULT_LOCAL:
3662 case LPFC_ASYNC_LINK_FAULT_REMOTE:
3663 latt_fault = 0;
3664 break;
3665 default:
3666 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
3667 "0398 Invalid link fault code: x%x\n",
3668 bf_get(lpfc_acqe_link_fault, acqe_link));
3669 latt_fault = MBXERR_ERROR;
3670 break;
3671 }
3672 return latt_fault;
3673}
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685static uint8_t
3686lpfc_sli4_parse_latt_type(struct lpfc_hba *phba,
3687 struct lpfc_acqe_link *acqe_link)
3688{
3689 uint8_t att_type;
3690
3691 switch (bf_get(lpfc_acqe_link_status, acqe_link)) {
3692 case LPFC_ASYNC_LINK_STATUS_DOWN:
3693 case LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN:
3694 att_type = LPFC_ATT_LINK_DOWN;
3695 break;
3696 case LPFC_ASYNC_LINK_STATUS_UP:
3697
3698 att_type = LPFC_ATT_RESERVED;
3699 break;
3700 case LPFC_ASYNC_LINK_STATUS_LOGICAL_UP:
3701 att_type = LPFC_ATT_LINK_UP;
3702 break;
3703 default:
3704 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
3705 "0399 Invalid link attention type: x%x\n",
3706 bf_get(lpfc_acqe_link_status, acqe_link));
3707 att_type = LPFC_ATT_RESERVED;
3708 break;
3709 }
3710 return att_type;
3711}
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721uint32_t
3722lpfc_sli_port_speed_get(struct lpfc_hba *phba)
3723{
3724 uint32_t link_speed;
3725
3726 if (!lpfc_is_link_up(phba))
3727 return 0;
3728
3729 if (phba->sli_rev <= LPFC_SLI_REV3) {
3730 switch (phba->fc_linkspeed) {
3731 case LPFC_LINK_SPEED_1GHZ:
3732 link_speed = 1000;
3733 break;
3734 case LPFC_LINK_SPEED_2GHZ:
3735 link_speed = 2000;
3736 break;
3737 case LPFC_LINK_SPEED_4GHZ:
3738 link_speed = 4000;
3739 break;
3740 case LPFC_LINK_SPEED_8GHZ:
3741 link_speed = 8000;
3742 break;
3743 case LPFC_LINK_SPEED_10GHZ:
3744 link_speed = 10000;
3745 break;
3746 case LPFC_LINK_SPEED_16GHZ:
3747 link_speed = 16000;
3748 break;
3749 default:
3750 link_speed = 0;
3751 }
3752 } else {
3753 if (phba->sli4_hba.link_state.logical_speed)
3754 link_speed =
3755 phba->sli4_hba.link_state.logical_speed;
3756 else
3757 link_speed = phba->sli4_hba.link_state.speed;
3758 }
3759 return link_speed;
3760}
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773static uint32_t
3774lpfc_sli4_port_speed_parse(struct lpfc_hba *phba, uint32_t evt_code,
3775 uint8_t speed_code)
3776{
3777 uint32_t port_speed;
3778
3779 switch (evt_code) {
3780 case LPFC_TRAILER_CODE_LINK:
3781 switch (speed_code) {
3782 case LPFC_ASYNC_LINK_SPEED_ZERO:
3783 port_speed = 0;
3784 break;
3785 case LPFC_ASYNC_LINK_SPEED_10MBPS:
3786 port_speed = 10;
3787 break;
3788 case LPFC_ASYNC_LINK_SPEED_100MBPS:
3789 port_speed = 100;
3790 break;
3791 case LPFC_ASYNC_LINK_SPEED_1GBPS:
3792 port_speed = 1000;
3793 break;
3794 case LPFC_ASYNC_LINK_SPEED_10GBPS:
3795 port_speed = 10000;
3796 break;
3797 case LPFC_ASYNC_LINK_SPEED_20GBPS:
3798 port_speed = 20000;
3799 break;
3800 case LPFC_ASYNC_LINK_SPEED_25GBPS:
3801 port_speed = 25000;
3802 break;
3803 case LPFC_ASYNC_LINK_SPEED_40GBPS:
3804 port_speed = 40000;
3805 break;
3806 default:
3807 port_speed = 0;
3808 }
3809 break;
3810 case LPFC_TRAILER_CODE_FC:
3811 switch (speed_code) {
3812 case LPFC_FC_LA_SPEED_UNKNOWN:
3813 port_speed = 0;
3814 break;
3815 case LPFC_FC_LA_SPEED_1G:
3816 port_speed = 1000;
3817 break;
3818 case LPFC_FC_LA_SPEED_2G:
3819 port_speed = 2000;
3820 break;
3821 case LPFC_FC_LA_SPEED_4G:
3822 port_speed = 4000;
3823 break;
3824 case LPFC_FC_LA_SPEED_8G:
3825 port_speed = 8000;
3826 break;
3827 case LPFC_FC_LA_SPEED_10G:
3828 port_speed = 10000;
3829 break;
3830 case LPFC_FC_LA_SPEED_16G:
3831 port_speed = 16000;
3832 break;
3833 case LPFC_FC_LA_SPEED_32G:
3834 port_speed = 32000;
3835 break;
3836 default:
3837 port_speed = 0;
3838 }
3839 break;
3840 default:
3841 port_speed = 0;
3842 }
3843 return port_speed;
3844}
3845
3846
3847
3848
3849
3850
3851
3852
3853static void
3854lpfc_sli4_async_link_evt(struct lpfc_hba *phba,
3855 struct lpfc_acqe_link *acqe_link)
3856{
3857 struct lpfc_dmabuf *mp;
3858 LPFC_MBOXQ_t *pmb;
3859 MAILBOX_t *mb;
3860 struct lpfc_mbx_read_top *la;
3861 uint8_t att_type;
3862 int rc;
3863
3864 att_type = lpfc_sli4_parse_latt_type(phba, acqe_link);
3865 if (att_type != LPFC_ATT_LINK_DOWN && att_type != LPFC_ATT_LINK_UP)
3866 return;
3867 phba->fcoe_eventtag = acqe_link->event_tag;
3868 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
3869 if (!pmb) {
3870 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3871 "0395 The mboxq allocation failed\n");
3872 return;
3873 }
3874 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
3875 if (!mp) {
3876 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3877 "0396 The lpfc_dmabuf allocation failed\n");
3878 goto out_free_pmb;
3879 }
3880 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
3881 if (!mp->virt) {
3882 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3883 "0397 The mbuf allocation failed\n");
3884 goto out_free_dmabuf;
3885 }
3886
3887
3888 lpfc_els_flush_all_cmd(phba);
3889
3890
3891 phba->sli.ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
3892
3893
3894 phba->sli.slistat.link_event++;
3895
3896
3897 lpfc_read_topology(phba, pmb, mp);
3898 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
3899 pmb->vport = phba->pport;
3900
3901
3902 phba->sli4_hba.link_state.speed =
3903 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_LINK,
3904 bf_get(lpfc_acqe_link_speed, acqe_link));
3905 phba->sli4_hba.link_state.duplex =
3906 bf_get(lpfc_acqe_link_duplex, acqe_link);
3907 phba->sli4_hba.link_state.status =
3908 bf_get(lpfc_acqe_link_status, acqe_link);
3909 phba->sli4_hba.link_state.type =
3910 bf_get(lpfc_acqe_link_type, acqe_link);
3911 phba->sli4_hba.link_state.number =
3912 bf_get(lpfc_acqe_link_number, acqe_link);
3913 phba->sli4_hba.link_state.fault =
3914 bf_get(lpfc_acqe_link_fault, acqe_link);
3915 phba->sli4_hba.link_state.logical_speed =
3916 bf_get(lpfc_acqe_logical_link_speed, acqe_link) * 10;
3917
3918 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3919 "2900 Async FC/FCoE Link event - Speed:%dGBit "
3920 "duplex:x%x LA Type:x%x Port Type:%d Port Number:%d "
3921 "Logical speed:%dMbps Fault:%d\n",
3922 phba->sli4_hba.link_state.speed,
3923 phba->sli4_hba.link_state.topology,
3924 phba->sli4_hba.link_state.status,
3925 phba->sli4_hba.link_state.type,
3926 phba->sli4_hba.link_state.number,
3927 phba->sli4_hba.link_state.logical_speed,
3928 phba->sli4_hba.link_state.fault);
3929
3930
3931
3932
3933 if (!(phba->hba_flag & HBA_FCOE_MODE)) {
3934 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
3935 if (rc == MBX_NOT_FINISHED)
3936 goto out_free_dmabuf;
3937 return;
3938 }
3939
3940
3941
3942
3943
3944
3945 mb = &pmb->u.mb;
3946 mb->mbxStatus = lpfc_sli4_parse_latt_fault(phba, acqe_link);
3947
3948
3949 la = (struct lpfc_mbx_read_top *) &pmb->u.mb.un.varReadTop;
3950 la->eventTag = acqe_link->event_tag;
3951 bf_set(lpfc_mbx_read_top_att_type, la, att_type);
3952 bf_set(lpfc_mbx_read_top_link_spd, la,
3953 (bf_get(lpfc_acqe_link_speed, acqe_link)));
3954
3955
3956 bf_set(lpfc_mbx_read_top_topology, la, LPFC_TOPOLOGY_PT_PT);
3957 bf_set(lpfc_mbx_read_top_alpa_granted, la, 0);
3958 bf_set(lpfc_mbx_read_top_il, la, 0);
3959 bf_set(lpfc_mbx_read_top_pb, la, 0);
3960 bf_set(lpfc_mbx_read_top_fa, la, 0);
3961 bf_set(lpfc_mbx_read_top_mm, la, 0);
3962
3963
3964 lpfc_mbx_cmpl_read_topology(phba, pmb);
3965
3966 return;
3967
3968out_free_dmabuf:
3969 kfree(mp);
3970out_free_pmb:
3971 mempool_free(pmb, phba->mbox_mem_pool);
3972}
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983static void
3984lpfc_sli4_async_fc_evt(struct lpfc_hba *phba, struct lpfc_acqe_fc_la *acqe_fc)
3985{
3986 struct lpfc_dmabuf *mp;
3987 LPFC_MBOXQ_t *pmb;
3988 int rc;
3989
3990 if (bf_get(lpfc_trailer_type, acqe_fc) !=
3991 LPFC_FC_LA_EVENT_TYPE_FC_LINK) {
3992 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3993 "2895 Non FC link Event detected.(%d)\n",
3994 bf_get(lpfc_trailer_type, acqe_fc));
3995 return;
3996 }
3997
3998 phba->sli4_hba.link_state.speed =
3999 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
4000 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
4001 phba->sli4_hba.link_state.duplex = LPFC_ASYNC_LINK_DUPLEX_FULL;
4002 phba->sli4_hba.link_state.topology =
4003 bf_get(lpfc_acqe_fc_la_topology, acqe_fc);
4004 phba->sli4_hba.link_state.status =
4005 bf_get(lpfc_acqe_fc_la_att_type, acqe_fc);
4006 phba->sli4_hba.link_state.type =
4007 bf_get(lpfc_acqe_fc_la_port_type, acqe_fc);
4008 phba->sli4_hba.link_state.number =
4009 bf_get(lpfc_acqe_fc_la_port_number, acqe_fc);
4010 phba->sli4_hba.link_state.fault =
4011 bf_get(lpfc_acqe_link_fault, acqe_fc);
4012 phba->sli4_hba.link_state.logical_speed =
4013 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
4014 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4015 "2896 Async FC event - Speed:%dGBaud Topology:x%x "
4016 "LA Type:x%x Port Type:%d Port Number:%d Logical speed:"
4017 "%dMbps Fault:%d\n",
4018 phba->sli4_hba.link_state.speed,
4019 phba->sli4_hba.link_state.topology,
4020 phba->sli4_hba.link_state.status,
4021 phba->sli4_hba.link_state.type,
4022 phba->sli4_hba.link_state.number,
4023 phba->sli4_hba.link_state.logical_speed,
4024 phba->sli4_hba.link_state.fault);
4025 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
4026 if (!pmb) {
4027 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4028 "2897 The mboxq allocation failed\n");
4029 return;
4030 }
4031 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
4032 if (!mp) {
4033 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4034 "2898 The lpfc_dmabuf allocation failed\n");
4035 goto out_free_pmb;
4036 }
4037 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
4038 if (!mp->virt) {
4039 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4040 "2899 The mbuf allocation failed\n");
4041 goto out_free_dmabuf;
4042 }
4043
4044
4045 lpfc_els_flush_all_cmd(phba);
4046
4047
4048 phba->sli.ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
4049
4050
4051 phba->sli.slistat.link_event++;
4052
4053
4054 lpfc_read_topology(phba, pmb, mp);
4055 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
4056 pmb->vport = phba->pport;
4057
4058 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
4059 if (rc == MBX_NOT_FINISHED)
4060 goto out_free_dmabuf;
4061 return;
4062
4063out_free_dmabuf:
4064 kfree(mp);
4065out_free_pmb:
4066 mempool_free(pmb, phba->mbox_mem_pool);
4067}
4068
4069
4070
4071
4072
4073
4074
4075
4076static void
4077lpfc_sli4_async_sli_evt(struct lpfc_hba *phba, struct lpfc_acqe_sli *acqe_sli)
4078{
4079 char port_name;
4080 char message[128];
4081 uint8_t status;
4082 uint8_t evt_type;
4083 uint8_t operational = 0;
4084 struct temp_event temp_event_data;
4085 struct lpfc_acqe_misconfigured_event *misconfigured;
4086 struct Scsi_Host *shost;
4087
4088 evt_type = bf_get(lpfc_trailer_type, acqe_sli);
4089
4090 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4091 "2901 Async SLI event - Event Data1:x%08x Event Data2:"
4092 "x%08x SLI Event Type:%d\n",
4093 acqe_sli->event_data1, acqe_sli->event_data2,
4094 evt_type);
4095
4096 port_name = phba->Port[0];
4097 if (port_name == 0x00)
4098 port_name = '?';
4099
4100 switch (evt_type) {
4101 case LPFC_SLI_EVENT_TYPE_OVER_TEMP:
4102 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
4103 temp_event_data.event_code = LPFC_THRESHOLD_TEMP;
4104 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
4105
4106 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
4107 "3190 Over Temperature:%d Celsius- Port Name %c\n",
4108 acqe_sli->event_data1, port_name);
4109
4110 shost = lpfc_shost_from_vport(phba->pport);
4111 fc_host_post_vendor_event(shost, fc_get_event_number(),
4112 sizeof(temp_event_data),
4113 (char *)&temp_event_data,
4114 SCSI_NL_VID_TYPE_PCI
4115 | PCI_VENDOR_ID_EMULEX);
4116 break;
4117 case LPFC_SLI_EVENT_TYPE_NORM_TEMP:
4118 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
4119 temp_event_data.event_code = LPFC_NORMAL_TEMP;
4120 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
4121
4122 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4123 "3191 Normal Temperature:%d Celsius - Port Name %c\n",
4124 acqe_sli->event_data1, port_name);
4125
4126 shost = lpfc_shost_from_vport(phba->pport);
4127 fc_host_post_vendor_event(shost, fc_get_event_number(),
4128 sizeof(temp_event_data),
4129 (char *)&temp_event_data,
4130 SCSI_NL_VID_TYPE_PCI
4131 | PCI_VENDOR_ID_EMULEX);
4132 break;
4133 case LPFC_SLI_EVENT_TYPE_MISCONFIGURED:
4134 misconfigured = (struct lpfc_acqe_misconfigured_event *)
4135 &acqe_sli->event_data1;
4136
4137
4138 switch (phba->sli4_hba.lnk_info.lnk_no) {
4139 case LPFC_LINK_NUMBER_0:
4140 status = bf_get(lpfc_sli_misconfigured_port0_state,
4141 &misconfigured->theEvent);
4142 operational = bf_get(lpfc_sli_misconfigured_port0_op,
4143 &misconfigured->theEvent);
4144 break;
4145 case LPFC_LINK_NUMBER_1:
4146 status = bf_get(lpfc_sli_misconfigured_port1_state,
4147 &misconfigured->theEvent);
4148 operational = bf_get(lpfc_sli_misconfigured_port1_op,
4149 &misconfigured->theEvent);
4150 break;
4151 case LPFC_LINK_NUMBER_2:
4152 status = bf_get(lpfc_sli_misconfigured_port2_state,
4153 &misconfigured->theEvent);
4154 operational = bf_get(lpfc_sli_misconfigured_port2_op,
4155 &misconfigured->theEvent);
4156 break;
4157 case LPFC_LINK_NUMBER_3:
4158 status = bf_get(lpfc_sli_misconfigured_port3_state,
4159 &misconfigured->theEvent);
4160 operational = bf_get(lpfc_sli_misconfigured_port3_op,
4161 &misconfigured->theEvent);
4162 break;
4163 default:
4164 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4165 "3296 "
4166 "LPFC_SLI_EVENT_TYPE_MISCONFIGURED "
4167 "event: Invalid link %d",
4168 phba->sli4_hba.lnk_info.lnk_no);
4169 return;
4170 }
4171
4172
4173 if (phba->sli4_hba.lnk_info.optic_state == status)
4174 return;
4175
4176 switch (status) {
4177 case LPFC_SLI_EVENT_STATUS_VALID:
4178 sprintf(message, "Physical Link is functional");
4179 break;
4180 case LPFC_SLI_EVENT_STATUS_NOT_PRESENT:
4181 sprintf(message, "Optics faulted/incorrectly "
4182 "installed/not installed - Reseat optics, "
4183 "if issue not resolved, replace.");
4184 break;
4185 case LPFC_SLI_EVENT_STATUS_WRONG_TYPE:
4186 sprintf(message,
4187 "Optics of two types installed - Remove one "
4188 "optic or install matching pair of optics.");
4189 break;
4190 case LPFC_SLI_EVENT_STATUS_UNSUPPORTED:
4191 sprintf(message, "Incompatible optics - Replace with "
4192 "compatible optics for card to function.");
4193 break;
4194 case LPFC_SLI_EVENT_STATUS_UNQUALIFIED:
4195 sprintf(message, "Unqualified optics - Replace with "
4196 "Avago optics for Warranty and Technical "
4197 "Support - Link is%s operational",
4198 (operational) ? "" : " not");
4199 break;
4200 case LPFC_SLI_EVENT_STATUS_UNCERTIFIED:
4201 sprintf(message, "Uncertified optics - Replace with "
4202 "Avago-certified optics to enable link "
4203 "operation - Link is%s operational",
4204 (operational) ? "" : " not");
4205 break;
4206 default:
4207
4208 sprintf(message, "Unknown event status x%02x", status);
4209 break;
4210 }
4211 phba->sli4_hba.lnk_info.optic_state = status;
4212 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4213 "3176 Port Name %c %s\n", port_name, message);
4214 break;
4215 case LPFC_SLI_EVENT_TYPE_REMOTE_DPORT:
4216 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4217 "3192 Remote DPort Test Initiated - "
4218 "Event Data1:x%08x Event Data2: x%08x\n",
4219 acqe_sli->event_data1, acqe_sli->event_data2);
4220 break;
4221 default:
4222 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4223 "3193 Async SLI event - Event Data1:x%08x Event Data2:"
4224 "x%08x SLI Event Type:%d\n",
4225 acqe_sli->event_data1, acqe_sli->event_data2,
4226 evt_type);
4227 break;
4228 }
4229}
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241static struct lpfc_nodelist *
4242lpfc_sli4_perform_vport_cvl(struct lpfc_vport *vport)
4243{
4244 struct lpfc_nodelist *ndlp;
4245 struct Scsi_Host *shost;
4246 struct lpfc_hba *phba;
4247
4248 if (!vport)
4249 return NULL;
4250 phba = vport->phba;
4251 if (!phba)
4252 return NULL;
4253 ndlp = lpfc_findnode_did(vport, Fabric_DID);
4254 if (!ndlp) {
4255
4256 ndlp = mempool_alloc(phba->nlp_mem_pool, GFP_KERNEL);
4257 if (!ndlp)
4258 return 0;
4259 lpfc_nlp_init(vport, ndlp, Fabric_DID);
4260
4261 ndlp->nlp_type |= NLP_FABRIC;
4262
4263 lpfc_enqueue_node(vport, ndlp);
4264 } else if (!NLP_CHK_NODE_ACT(ndlp)) {
4265
4266 ndlp = lpfc_enable_node(vport, ndlp, NLP_STE_UNUSED_NODE);
4267 if (!ndlp)
4268 return 0;
4269 }
4270 if ((phba->pport->port_state < LPFC_FLOGI) &&
4271 (phba->pport->port_state != LPFC_VPORT_FAILED))
4272 return NULL;
4273
4274 if ((vport != phba->pport) && (vport->port_state < LPFC_FDISC)
4275 && (vport->port_state != LPFC_VPORT_FAILED))
4276 return NULL;
4277 shost = lpfc_shost_from_vport(vport);
4278 if (!shost)
4279 return NULL;
4280 lpfc_linkdown_port(vport);
4281 lpfc_cleanup_pending_mbox(vport);
4282 spin_lock_irq(shost->host_lock);
4283 vport->fc_flag |= FC_VPORT_CVL_RCVD;
4284 spin_unlock_irq(shost->host_lock);
4285
4286 return ndlp;
4287}
4288
4289
4290
4291
4292
4293
4294
4295
4296static void
4297lpfc_sli4_perform_all_vport_cvl(struct lpfc_hba *phba)
4298{
4299 struct lpfc_vport **vports;
4300 int i;
4301
4302 vports = lpfc_create_vport_work_array(phba);
4303 if (vports)
4304 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
4305 lpfc_sli4_perform_vport_cvl(vports[i]);
4306 lpfc_destroy_vport_work_array(phba, vports);
4307}
4308
4309
4310
4311
4312
4313
4314
4315
4316static void
4317lpfc_sli4_async_fip_evt(struct lpfc_hba *phba,
4318 struct lpfc_acqe_fip *acqe_fip)
4319{
4320 uint8_t event_type = bf_get(lpfc_trailer_type, acqe_fip);
4321 int rc;
4322 struct lpfc_vport *vport;
4323 struct lpfc_nodelist *ndlp;
4324 struct Scsi_Host *shost;
4325 int active_vlink_present;
4326 struct lpfc_vport **vports;
4327 int i;
4328
4329 phba->fc_eventTag = acqe_fip->event_tag;
4330 phba->fcoe_eventtag = acqe_fip->event_tag;
4331 switch (event_type) {
4332 case LPFC_FIP_EVENT_TYPE_NEW_FCF:
4333 case LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD:
4334 if (event_type == LPFC_FIP_EVENT_TYPE_NEW_FCF)
4335 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
4336 LOG_DISCOVERY,
4337 "2546 New FCF event, evt_tag:x%x, "
4338 "index:x%x\n",
4339 acqe_fip->event_tag,
4340 acqe_fip->index);
4341 else
4342 lpfc_printf_log(phba, KERN_WARNING, LOG_FIP |
4343 LOG_DISCOVERY,
4344 "2788 FCF param modified event, "
4345 "evt_tag:x%x, index:x%x\n",
4346 acqe_fip->event_tag,
4347 acqe_fip->index);
4348 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
4349
4350
4351
4352
4353
4354 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
4355 LOG_DISCOVERY,
4356 "2779 Read FCF (x%x) for updating "
4357 "roundrobin FCF failover bmask\n",
4358 acqe_fip->index);
4359 rc = lpfc_sli4_read_fcf_rec(phba, acqe_fip->index);
4360 }
4361
4362
4363 spin_lock_irq(&phba->hbalock);
4364 if (phba->hba_flag & FCF_TS_INPROG) {
4365 spin_unlock_irq(&phba->hbalock);
4366 break;
4367 }
4368
4369 if (phba->fcf.fcf_flag & FCF_REDISC_EVT) {
4370 spin_unlock_irq(&phba->hbalock);
4371 break;
4372 }
4373
4374
4375 if (phba->fcf.fcf_flag & FCF_SCAN_DONE) {
4376 spin_unlock_irq(&phba->hbalock);
4377 break;
4378 }
4379 spin_unlock_irq(&phba->hbalock);
4380
4381
4382 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
4383 "2770 Start FCF table scan per async FCF "
4384 "event, evt_tag:x%x, index:x%x\n",
4385 acqe_fip->event_tag, acqe_fip->index);
4386 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba,
4387 LPFC_FCOE_FCF_GET_FIRST);
4388 if (rc)
4389 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
4390 "2547 Issue FCF scan read FCF mailbox "
4391 "command failed (x%x)\n", rc);
4392 break;
4393
4394 case LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL:
4395 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4396 "2548 FCF Table full count 0x%x tag 0x%x\n",
4397 bf_get(lpfc_acqe_fip_fcf_count, acqe_fip),
4398 acqe_fip->event_tag);
4399 break;
4400
4401 case LPFC_FIP_EVENT_TYPE_FCF_DEAD:
4402 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
4403 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
4404 "2549 FCF (x%x) disconnected from network, "
4405 "tag:x%x\n", acqe_fip->index, acqe_fip->event_tag);
4406
4407
4408
4409
4410 spin_lock_irq(&phba->hbalock);
4411 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
4412 spin_unlock_irq(&phba->hbalock);
4413
4414 lpfc_sli4_fcf_rr_index_clear(phba, acqe_fip->index);
4415 break;
4416 }
4417 spin_unlock_irq(&phba->hbalock);
4418
4419
4420 if (phba->fcf.current_rec.fcf_indx != acqe_fip->index)
4421 break;
4422
4423
4424
4425
4426
4427
4428
4429 spin_lock_irq(&phba->hbalock);
4430
4431 phba->fcf.fcf_flag |= FCF_DEAD_DISC;
4432 spin_unlock_irq(&phba->hbalock);
4433
4434 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
4435 "2771 Start FCF fast failover process due to "
4436 "FCF DEAD event: evt_tag:x%x, fcf_index:x%x "
4437 "\n", acqe_fip->event_tag, acqe_fip->index);
4438 rc = lpfc_sli4_redisc_fcf_table(phba);
4439 if (rc) {
4440 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
4441 LOG_DISCOVERY,
4442 "2772 Issue FCF rediscover mabilbox "
4443 "command failed, fail through to FCF "
4444 "dead event\n");
4445 spin_lock_irq(&phba->hbalock);
4446 phba->fcf.fcf_flag &= ~FCF_DEAD_DISC;
4447 spin_unlock_irq(&phba->hbalock);
4448
4449
4450
4451
4452 lpfc_sli4_fcf_dead_failthrough(phba);
4453 } else {
4454
4455 lpfc_sli4_clear_fcf_rr_bmask(phba);
4456
4457
4458
4459
4460 lpfc_sli4_perform_all_vport_cvl(phba);
4461 }
4462 break;
4463 case LPFC_FIP_EVENT_TYPE_CVL:
4464 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
4465 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
4466 "2718 Clear Virtual Link Received for VPI 0x%x"
4467 " tag 0x%x\n", acqe_fip->index, acqe_fip->event_tag);
4468
4469 vport = lpfc_find_vport_by_vpid(phba,
4470 acqe_fip->index);
4471 ndlp = lpfc_sli4_perform_vport_cvl(vport);
4472 if (!ndlp)
4473 break;
4474 active_vlink_present = 0;
4475
4476 vports = lpfc_create_vport_work_array(phba);
4477 if (vports) {
4478 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
4479 i++) {
4480 if ((!(vports[i]->fc_flag &
4481 FC_VPORT_CVL_RCVD)) &&
4482 (vports[i]->port_state > LPFC_FDISC)) {
4483 active_vlink_present = 1;
4484 break;
4485 }
4486 }
4487 lpfc_destroy_vport_work_array(phba, vports);
4488 }
4489
4490
4491
4492
4493
4494
4495 if (!(vport->load_flag & FC_UNLOADING) &&
4496 active_vlink_present) {
4497
4498
4499
4500
4501 mod_timer(&ndlp->nlp_delayfunc,
4502 jiffies + msecs_to_jiffies(1000));
4503 shost = lpfc_shost_from_vport(vport);
4504 spin_lock_irq(shost->host_lock);
4505 ndlp->nlp_flag |= NLP_DELAY_TMO;
4506 spin_unlock_irq(shost->host_lock);
4507 ndlp->nlp_last_elscmd = ELS_CMD_FDISC;
4508 vport->port_state = LPFC_FDISC;
4509 } else {
4510
4511
4512
4513
4514
4515
4516
4517 spin_lock_irq(&phba->hbalock);
4518 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
4519 spin_unlock_irq(&phba->hbalock);
4520 break;
4521 }
4522
4523 phba->fcf.fcf_flag |= FCF_ACVL_DISC;
4524 spin_unlock_irq(&phba->hbalock);
4525 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
4526 LOG_DISCOVERY,
4527 "2773 Start FCF failover per CVL, "
4528 "evt_tag:x%x\n", acqe_fip->event_tag);
4529 rc = lpfc_sli4_redisc_fcf_table(phba);
4530 if (rc) {
4531 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
4532 LOG_DISCOVERY,
4533 "2774 Issue FCF rediscover "
4534 "mabilbox command failed, "
4535 "through to CVL event\n");
4536 spin_lock_irq(&phba->hbalock);
4537 phba->fcf.fcf_flag &= ~FCF_ACVL_DISC;
4538 spin_unlock_irq(&phba->hbalock);
4539
4540
4541
4542
4543 lpfc_retry_pport_discovery(phba);
4544 } else
4545
4546
4547
4548
4549 lpfc_sli4_clear_fcf_rr_bmask(phba);
4550 }
4551 break;
4552 default:
4553 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4554 "0288 Unknown FCoE event type 0x%x event tag "
4555 "0x%x\n", event_type, acqe_fip->event_tag);
4556 break;
4557 }
4558}
4559
4560
4561
4562
4563
4564
4565
4566
4567static void
4568lpfc_sli4_async_dcbx_evt(struct lpfc_hba *phba,
4569 struct lpfc_acqe_dcbx *acqe_dcbx)
4570{
4571 phba->fc_eventTag = acqe_dcbx->event_tag;
4572 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4573 "0290 The SLI4 DCBX asynchronous event is not "
4574 "handled yet\n");
4575}
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586static void
4587lpfc_sli4_async_grp5_evt(struct lpfc_hba *phba,
4588 struct lpfc_acqe_grp5 *acqe_grp5)
4589{
4590 uint16_t prev_ll_spd;
4591
4592 phba->fc_eventTag = acqe_grp5->event_tag;
4593 phba->fcoe_eventtag = acqe_grp5->event_tag;
4594 prev_ll_spd = phba->sli4_hba.link_state.logical_speed;
4595 phba->sli4_hba.link_state.logical_speed =
4596 (bf_get(lpfc_acqe_grp5_llink_spd, acqe_grp5)) * 10;
4597 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4598 "2789 GRP5 Async Event: Updating logical link speed "
4599 "from %dMbps to %dMbps\n", prev_ll_spd,
4600 phba->sli4_hba.link_state.logical_speed);
4601}
4602
4603
4604
4605
4606
4607
4608
4609
4610void lpfc_sli4_async_event_proc(struct lpfc_hba *phba)
4611{
4612 struct lpfc_cq_event *cq_event;
4613
4614
4615 spin_lock_irq(&phba->hbalock);
4616 phba->hba_flag &= ~ASYNC_EVENT;
4617 spin_unlock_irq(&phba->hbalock);
4618
4619 while (!list_empty(&phba->sli4_hba.sp_asynce_work_queue)) {
4620
4621 spin_lock_irq(&phba->hbalock);
4622 list_remove_head(&phba->sli4_hba.sp_asynce_work_queue,
4623 cq_event, struct lpfc_cq_event, list);
4624 spin_unlock_irq(&phba->hbalock);
4625
4626 switch (bf_get(lpfc_trailer_code, &cq_event->cqe.mcqe_cmpl)) {
4627 case LPFC_TRAILER_CODE_LINK:
4628 lpfc_sli4_async_link_evt(phba,
4629 &cq_event->cqe.acqe_link);
4630 break;
4631 case LPFC_TRAILER_CODE_FCOE:
4632 lpfc_sli4_async_fip_evt(phba, &cq_event->cqe.acqe_fip);
4633 break;
4634 case LPFC_TRAILER_CODE_DCBX:
4635 lpfc_sli4_async_dcbx_evt(phba,
4636 &cq_event->cqe.acqe_dcbx);
4637 break;
4638 case LPFC_TRAILER_CODE_GRP5:
4639 lpfc_sli4_async_grp5_evt(phba,
4640 &cq_event->cqe.acqe_grp5);
4641 break;
4642 case LPFC_TRAILER_CODE_FC:
4643 lpfc_sli4_async_fc_evt(phba, &cq_event->cqe.acqe_fc);
4644 break;
4645 case LPFC_TRAILER_CODE_SLI:
4646 lpfc_sli4_async_sli_evt(phba, &cq_event->cqe.acqe_sli);
4647 break;
4648 default:
4649 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4650 "1804 Invalid asynchrous event code: "
4651 "x%x\n", bf_get(lpfc_trailer_code,
4652 &cq_event->cqe.mcqe_cmpl));
4653 break;
4654 }
4655
4656 lpfc_sli4_cq_event_release(phba, cq_event);
4657 }
4658}
4659
4660
4661
4662
4663
4664
4665
4666
4667void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *phba)
4668{
4669 int rc;
4670
4671 spin_lock_irq(&phba->hbalock);
4672
4673 phba->fcf.fcf_flag &= ~FCF_REDISC_EVT;
4674
4675 phba->fcf.failover_rec.flag = 0;
4676
4677 phba->fcf.fcf_flag |= FCF_REDISC_FOV;
4678 spin_unlock_irq(&phba->hbalock);
4679
4680
4681 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
4682 "2777 Start post-quiescent FCF table scan\n");
4683 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST);
4684 if (rc)
4685 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
4686 "2747 Issue FCF scan read FCF mailbox "
4687 "command failed 0x%x\n", rc);
4688}
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700int
4701lpfc_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
4702{
4703 int rc;
4704
4705
4706 phba->pci_dev_grp = dev_grp;
4707
4708
4709 if (dev_grp == LPFC_PCI_DEV_OC)
4710 phba->sli_rev = LPFC_SLI_REV4;
4711
4712
4713 rc = lpfc_init_api_table_setup(phba, dev_grp);
4714 if (rc)
4715 return -ENODEV;
4716
4717 rc = lpfc_scsi_api_table_setup(phba, dev_grp);
4718 if (rc)
4719 return -ENODEV;
4720
4721 rc = lpfc_sli_api_table_setup(phba, dev_grp);
4722 if (rc)
4723 return -ENODEV;
4724
4725 rc = lpfc_mbox_api_table_setup(phba, dev_grp);
4726 if (rc)
4727 return -ENODEV;
4728
4729 return 0;
4730}
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode)
4741{
4742 switch (intr_mode) {
4743 case 0:
4744 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
4745 "0470 Enable INTx interrupt mode.\n");
4746 break;
4747 case 1:
4748 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
4749 "0481 Enabled MSI interrupt mode.\n");
4750 break;
4751 case 2:
4752 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
4753 "0480 Enabled MSI-X interrupt mode.\n");
4754 break;
4755 default:
4756 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4757 "0482 Illegal interrupt mode.\n");
4758 break;
4759 }
4760 return;
4761}
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774static int
4775lpfc_enable_pci_dev(struct lpfc_hba *phba)
4776{
4777 struct pci_dev *pdev;
4778 int bars = 0;
4779
4780
4781 if (!phba->pcidev)
4782 goto out_error;
4783 else
4784 pdev = phba->pcidev;
4785
4786 bars = pci_select_bars(pdev, IORESOURCE_MEM);
4787
4788 if (pci_enable_device_mem(pdev))
4789 goto out_error;
4790
4791 if (pci_request_selected_regions(pdev, bars, LPFC_DRIVER_NAME))
4792 goto out_disable_device;
4793
4794 pci_set_master(pdev);
4795 pci_try_set_mwi(pdev);
4796 pci_save_state(pdev);
4797
4798
4799 if (pci_is_pcie(pdev))
4800 pdev->needs_freset = 1;
4801
4802 return 0;
4803
4804out_disable_device:
4805 pci_disable_device(pdev);
4806out_error:
4807 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4808 "1401 Failed to enable pci device, bars:x%x\n", bars);
4809 return -ENODEV;
4810}
4811
4812
4813
4814
4815
4816
4817
4818
4819static void
4820lpfc_disable_pci_dev(struct lpfc_hba *phba)
4821{
4822 struct pci_dev *pdev;
4823 int bars;
4824
4825
4826 if (!phba->pcidev)
4827 return;
4828 else
4829 pdev = phba->pcidev;
4830
4831 bars = pci_select_bars(pdev, IORESOURCE_MEM);
4832
4833 pci_release_selected_regions(pdev, bars);
4834 pci_disable_device(pdev);
4835
4836 return;
4837}
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848void
4849lpfc_reset_hba(struct lpfc_hba *phba)
4850{
4851
4852 if (!phba->cfg_enable_hba_reset) {
4853 phba->link_state = LPFC_HBA_ERROR;
4854 return;
4855 }
4856 if (phba->sli.sli_flag & LPFC_SLI_ACTIVE)
4857 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
4858 else
4859 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
4860 lpfc_offline(phba);
4861 lpfc_sli_brdrestart(phba);
4862 lpfc_online(phba);
4863 lpfc_unblock_mgmt_io(phba);
4864}
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876uint16_t
4877lpfc_sli_sriov_nr_virtfn_get(struct lpfc_hba *phba)
4878{
4879 struct pci_dev *pdev = phba->pcidev;
4880 uint16_t nr_virtfn;
4881 int pos;
4882
4883 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
4884 if (pos == 0)
4885 return 0;
4886
4887 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
4888 return nr_virtfn;
4889}
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902int
4903lpfc_sli_probe_sriov_nr_virtfn(struct lpfc_hba *phba, int nr_vfn)
4904{
4905 struct pci_dev *pdev = phba->pcidev;
4906 uint16_t max_nr_vfn;
4907 int rc;
4908
4909 max_nr_vfn = lpfc_sli_sriov_nr_virtfn_get(phba);
4910 if (nr_vfn > max_nr_vfn) {
4911 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4912 "3057 Requested vfs (%d) greater than "
4913 "supported vfs (%d)", nr_vfn, max_nr_vfn);
4914 return -EINVAL;
4915 }
4916
4917 rc = pci_enable_sriov(pdev, nr_vfn);
4918 if (rc) {
4919 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
4920 "2806 Failed to enable sriov on this device "
4921 "with vfn number nr_vf:%d, rc:%d\n",
4922 nr_vfn, rc);
4923 } else
4924 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
4925 "2807 Successful enable sriov on this device "
4926 "with vfn number nr_vf:%d\n", nr_vfn);
4927 return rc;
4928}
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941static int
4942lpfc_sli_driver_resource_setup(struct lpfc_hba *phba)
4943{
4944 struct lpfc_sli *psli;
4945 int rc;
4946
4947
4948
4949
4950
4951
4952 init_timer(&phba->hb_tmofunc);
4953 phba->hb_tmofunc.function = lpfc_hb_timeout;
4954 phba->hb_tmofunc.data = (unsigned long)phba;
4955
4956 psli = &phba->sli;
4957
4958 init_timer(&psli->mbox_tmo);
4959 psli->mbox_tmo.function = lpfc_mbox_timeout;
4960 psli->mbox_tmo.data = (unsigned long) phba;
4961
4962 init_timer(&phba->fcp_poll_timer);
4963 phba->fcp_poll_timer.function = lpfc_poll_timeout;
4964 phba->fcp_poll_timer.data = (unsigned long) phba;
4965
4966 init_timer(&phba->fabric_block_timer);
4967 phba->fabric_block_timer.function = lpfc_fabric_block_timeout;
4968 phba->fabric_block_timer.data = (unsigned long) phba;
4969
4970 init_timer(&phba->eratt_poll);
4971 phba->eratt_poll.function = lpfc_poll_eratt;
4972 phba->eratt_poll.data = (unsigned long) phba;
4973
4974
4975 phba->work_ha_mask = (HA_ERATT | HA_MBATT | HA_LATT);
4976 phba->work_ha_mask |= (HA_RXMASK << (LPFC_ELS_RING * 4));
4977
4978
4979 lpfc_get_cfgparam(phba);
4980 if (phba->pcidev->device == PCI_DEVICE_ID_HORNET) {
4981 phba->menlo_flag |= HBA_MENLO_SUPPORT;
4982
4983 if (phba->cfg_sg_seg_cnt < LPFC_DEFAULT_MENLO_SG_SEG_CNT)
4984 phba->cfg_sg_seg_cnt = LPFC_DEFAULT_MENLO_SG_SEG_CNT;
4985 }
4986
4987 if (!phba->sli.ring)
4988 phba->sli.ring = kzalloc(LPFC_SLI3_MAX_RING *
4989 sizeof(struct lpfc_sli_ring), GFP_KERNEL);
4990 if (!phba->sli.ring)
4991 return -ENOMEM;
4992
4993
4994
4995
4996
4997
4998
4999 lpfc_vport_template.sg_tablesize = phba->cfg_sg_seg_cnt;
5000 lpfc_template_s3.sg_tablesize = phba->cfg_sg_seg_cnt;
5001
5002
5003 if (phba->cfg_enable_bg) {
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
5014 sizeof(struct fcp_rsp) +
5015 (LPFC_MAX_SG_SEG_CNT * sizeof(struct ulp_bde64));
5016
5017 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SEG_CNT_DIF)
5018 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SEG_CNT_DIF;
5019
5020
5021 phba->cfg_total_seg_cnt = LPFC_MAX_SG_SEG_CNT;
5022 } else {
5023
5024
5025
5026
5027
5028 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
5029 sizeof(struct fcp_rsp) +
5030 ((phba->cfg_sg_seg_cnt + 2) * sizeof(struct ulp_bde64));
5031
5032
5033 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
5034 }
5035
5036 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
5037 "9088 sg_tablesize:%d dmabuf_size:%d total_bde:%d\n",
5038 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
5039 phba->cfg_total_seg_cnt);
5040
5041 phba->max_vpi = LPFC_MAX_VPI;
5042
5043 phba->max_vports = 0;
5044
5045
5046
5047
5048 lpfc_sli_setup(phba);
5049 lpfc_sli_queue_setup(phba);
5050
5051
5052 if (lpfc_mem_alloc(phba, BPL_ALIGN_SZ))
5053 return -ENOMEM;
5054
5055
5056
5057
5058
5059 if (phba->cfg_sriov_nr_virtfn > 0) {
5060 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
5061 phba->cfg_sriov_nr_virtfn);
5062 if (rc) {
5063 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
5064 "2808 Requested number of SR-IOV "
5065 "virtual functions (%d) is not "
5066 "supported\n",
5067 phba->cfg_sriov_nr_virtfn);
5068 phba->cfg_sriov_nr_virtfn = 0;
5069 }
5070 }
5071
5072 return 0;
5073}
5074
5075
5076
5077
5078
5079
5080
5081
5082static void
5083lpfc_sli_driver_resource_unset(struct lpfc_hba *phba)
5084{
5085
5086 lpfc_mem_free_all(phba);
5087
5088 return;
5089}
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102static int
5103lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
5104{
5105 struct lpfc_vector_map_info *cpup;
5106 struct lpfc_sli *psli;
5107 LPFC_MBOXQ_t *mboxq;
5108 int rc, i, hbq_count, max_buf_size;
5109 uint8_t pn_page[LPFC_MAX_SUPPORTED_PAGES] = {0};
5110 struct lpfc_mqe *mqe;
5111 int longs;
5112 int fof_vectors = 0;
5113
5114
5115 lpfc_get_cfgparam(phba);
5116
5117
5118 rc = lpfc_sli4_post_status_check(phba);
5119 if (rc)
5120 return -ENODEV;
5121
5122
5123
5124
5125
5126
5127 init_timer(&phba->hb_tmofunc);
5128 phba->hb_tmofunc.function = lpfc_hb_timeout;
5129 phba->hb_tmofunc.data = (unsigned long)phba;
5130 init_timer(&phba->rrq_tmr);
5131 phba->rrq_tmr.function = lpfc_rrq_timeout;
5132 phba->rrq_tmr.data = (unsigned long)phba;
5133
5134 psli = &phba->sli;
5135
5136 init_timer(&psli->mbox_tmo);
5137 psli->mbox_tmo.function = lpfc_mbox_timeout;
5138 psli->mbox_tmo.data = (unsigned long) phba;
5139
5140 init_timer(&phba->fabric_block_timer);
5141 phba->fabric_block_timer.function = lpfc_fabric_block_timeout;
5142 phba->fabric_block_timer.data = (unsigned long) phba;
5143
5144 init_timer(&phba->eratt_poll);
5145 phba->eratt_poll.function = lpfc_poll_eratt;
5146 phba->eratt_poll.data = (unsigned long) phba;
5147
5148 init_timer(&phba->fcf.redisc_wait);
5149 phba->fcf.redisc_wait.function = lpfc_sli4_fcf_redisc_wait_tmo;
5150 phba->fcf.redisc_wait.data = (unsigned long)phba;
5151
5152
5153
5154
5155
5156 memset((uint8_t *)&phba->mbox_ext_buf_ctx, 0,
5157 sizeof(struct lpfc_mbox_ext_buf_ctx));
5158 INIT_LIST_HEAD(&phba->mbox_ext_buf_ctx.ext_dmabuf_list);
5159
5160 phba->max_vpi = LPFC_MAX_VPI;
5161
5162
5163 phba->max_vports = 0;
5164
5165
5166 phba->valid_vlan = 0;
5167 phba->fc_map[0] = LPFC_FCOE_FCF_MAP0;
5168 phba->fc_map[1] = LPFC_FCOE_FCF_MAP1;
5169 phba->fc_map[2] = LPFC_FCOE_FCF_MAP2;
5170
5171
5172
5173
5174
5175 if (!phba->sli.ring)
5176 phba->sli.ring = kzalloc(
5177 (LPFC_SLI3_MAX_RING + phba->cfg_fcp_io_channel) *
5178 sizeof(struct lpfc_sli_ring), GFP_KERNEL);
5179 if (!phba->sli.ring)
5180 return -ENOMEM;
5181
5182
5183
5184
5185
5186
5187 max_buf_size = (2 * SLI4_PAGE_SIZE);
5188 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SGL_SEG_CNT - 2)
5189 phba->cfg_sg_seg_cnt = LPFC_MAX_SGL_SEG_CNT - 2;
5190
5191
5192
5193
5194
5195
5196 if (phba->cfg_enable_bg) {
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
5207 sizeof(struct fcp_rsp) + max_buf_size;
5208
5209
5210 phba->cfg_total_seg_cnt = LPFC_MAX_SGL_SEG_CNT;
5211
5212 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SLI4_SEG_CNT_DIF)
5213 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SLI4_SEG_CNT_DIF;
5214 } else {
5215
5216
5217
5218
5219
5220 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
5221 sizeof(struct fcp_rsp) +
5222 ((phba->cfg_sg_seg_cnt + 2) * sizeof(struct sli4_sge));
5223
5224
5225 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
5226
5227
5228
5229
5230 }
5231
5232
5233 lpfc_vport_template.sg_tablesize = phba->cfg_sg_seg_cnt;
5234 lpfc_template.sg_tablesize = phba->cfg_sg_seg_cnt;
5235
5236 if (phba->cfg_sg_dma_buf_size <= LPFC_MIN_SG_SLI4_BUF_SZ)
5237 phba->cfg_sg_dma_buf_size = LPFC_MIN_SG_SLI4_BUF_SZ;
5238 else
5239 phba->cfg_sg_dma_buf_size =
5240 SLI4_PAGE_ALIGN(phba->cfg_sg_dma_buf_size);
5241
5242 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
5243 "9087 sg_tablesize:%d dmabuf_size:%d total_sge:%d\n",
5244 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
5245 phba->cfg_total_seg_cnt);
5246
5247
5248 hbq_count = lpfc_sli_hbq_count();
5249 for (i = 0; i < hbq_count; ++i)
5250 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
5251 INIT_LIST_HEAD(&phba->rb_pend_list);
5252 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_sli4_rb_alloc;
5253 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_sli4_rb_free;
5254
5255
5256
5257
5258
5259 spin_lock_init(&phba->sli4_hba.abts_scsi_buf_list_lock);
5260 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_scsi_buf_list);
5261
5262 spin_lock_init(&phba->sli4_hba.abts_sgl_list_lock);
5263
5264
5265
5266
5267
5268
5269 INIT_LIST_HEAD(&phba->sli4_hba.sp_cqe_event_pool);
5270
5271 INIT_LIST_HEAD(&phba->sli4_hba.sp_queue_event);
5272
5273 INIT_LIST_HEAD(&phba->sli4_hba.sp_asynce_work_queue);
5274
5275 INIT_LIST_HEAD(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue);
5276
5277 INIT_LIST_HEAD(&phba->sli4_hba.sp_els_xri_aborted_work_queue);
5278
5279 INIT_LIST_HEAD(&phba->sli4_hba.sp_unsol_work_queue);
5280
5281
5282 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_blk_list);
5283 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_xri_blk_list);
5284 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_vfi_blk_list);
5285 INIT_LIST_HEAD(&phba->lpfc_vpi_blk_list);
5286
5287
5288 phba->sli4_hba.lnk_info.optic_state = 0xff;
5289
5290
5291 lpfc_sli_setup(phba);
5292 lpfc_sli_queue_setup(phba);
5293
5294
5295 rc = lpfc_mem_alloc(phba, SGL_ALIGN_SZ);
5296 if (rc)
5297 return -ENOMEM;
5298
5299
5300 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
5301 LPFC_SLI_INTF_IF_TYPE_2) {
5302 rc = lpfc_pci_function_reset(phba);
5303 if (unlikely(rc))
5304 return -ENODEV;
5305 phba->temp_sensor_support = 1;
5306 }
5307
5308
5309 rc = lpfc_create_bootstrap_mbox(phba);
5310 if (unlikely(rc))
5311 goto out_free_mem;
5312
5313
5314 rc = lpfc_setup_endian_order(phba);
5315 if (unlikely(rc))
5316 goto out_free_bsmbx;
5317
5318
5319 rc = lpfc_sli4_read_config(phba);
5320 if (unlikely(rc))
5321 goto out_free_bsmbx;
5322 rc = lpfc_mem_alloc_active_rrq_pool_s4(phba);
5323 if (unlikely(rc))
5324 goto out_free_bsmbx;
5325
5326
5327 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
5328 LPFC_SLI_INTF_IF_TYPE_0) {
5329 rc = lpfc_pci_function_reset(phba);
5330 if (unlikely(rc))
5331 goto out_free_bsmbx;
5332 }
5333
5334 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
5335 GFP_KERNEL);
5336 if (!mboxq) {
5337 rc = -ENOMEM;
5338 goto out_free_bsmbx;
5339 }
5340
5341
5342 lpfc_supported_pages(mboxq);
5343 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
5344 if (!rc) {
5345 mqe = &mboxq->u.mqe;
5346 memcpy(&pn_page[0], ((uint8_t *)&mqe->un.supp_pages.word3),
5347 LPFC_MAX_SUPPORTED_PAGES);
5348 for (i = 0; i < LPFC_MAX_SUPPORTED_PAGES; i++) {
5349 switch (pn_page[i]) {
5350 case LPFC_SLI4_PARAMETERS:
5351 phba->sli4_hba.pc_sli4_params.supported = 1;
5352 break;
5353 default:
5354 break;
5355 }
5356 }
5357
5358 if (phba->sli4_hba.pc_sli4_params.supported)
5359 rc = lpfc_pc_sli4_params_get(phba, mboxq);
5360 if (rc) {
5361 mempool_free(mboxq, phba->mbox_mem_pool);
5362 rc = -EIO;
5363 goto out_free_bsmbx;
5364 }
5365 }
5366
5367
5368
5369
5370
5371 rc = lpfc_get_sli4_parameters(phba, mboxq);
5372 if (rc) {
5373 if (phba->sli4_hba.extents_in_use &&
5374 phba->sli4_hba.rpi_hdrs_in_use) {
5375 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5376 "2999 Unsupported SLI4 Parameters "
5377 "Extents and RPI headers enabled.\n");
5378 goto out_free_bsmbx;
5379 }
5380 }
5381 mempool_free(mboxq, phba->mbox_mem_pool);
5382
5383
5384 lpfc_sli4_oas_verify(phba);
5385 if (phba->cfg_fof)
5386 fof_vectors = 1;
5387
5388
5389 rc = lpfc_sli4_queue_verify(phba);
5390 if (rc)
5391 goto out_free_bsmbx;
5392
5393
5394 rc = lpfc_sli4_cq_event_pool_create(phba);
5395 if (rc)
5396 goto out_free_bsmbx;
5397
5398
5399 lpfc_init_sgl_list(phba);
5400
5401
5402 rc = lpfc_init_active_sgl_array(phba);
5403 if (rc) {
5404 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5405 "1430 Failed to initialize sgl list.\n");
5406 goto out_destroy_cq_event_pool;
5407 }
5408 rc = lpfc_sli4_init_rpi_hdrs(phba);
5409 if (rc) {
5410 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5411 "1432 Failed to initialize rpi headers.\n");
5412 goto out_free_active_sgl;
5413 }
5414
5415
5416 longs = (LPFC_SLI4_FCF_TBL_INDX_MAX + BITS_PER_LONG - 1)/BITS_PER_LONG;
5417 phba->fcf.fcf_rr_bmask = kzalloc(longs * sizeof(unsigned long),
5418 GFP_KERNEL);
5419 if (!phba->fcf.fcf_rr_bmask) {
5420 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5421 "2759 Failed allocate memory for FCF round "
5422 "robin failover bmask\n");
5423 rc = -ENOMEM;
5424 goto out_remove_rpi_hdrs;
5425 }
5426
5427 phba->sli4_hba.fcp_eq_hdl =
5428 kzalloc((sizeof(struct lpfc_fcp_eq_hdl) *
5429 (fof_vectors + phba->cfg_fcp_io_channel)),
5430 GFP_KERNEL);
5431 if (!phba->sli4_hba.fcp_eq_hdl) {
5432 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5433 "2572 Failed allocate memory for "
5434 "fast-path per-EQ handle array\n");
5435 rc = -ENOMEM;
5436 goto out_free_fcf_rr_bmask;
5437 }
5438
5439 phba->sli4_hba.msix_entries = kzalloc((sizeof(struct msix_entry) *
5440 (fof_vectors +
5441 phba->cfg_fcp_io_channel)), GFP_KERNEL);
5442 if (!phba->sli4_hba.msix_entries) {
5443 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5444 "2573 Failed allocate memory for msi-x "
5445 "interrupt vector entries\n");
5446 rc = -ENOMEM;
5447 goto out_free_fcp_eq_hdl;
5448 }
5449
5450 phba->sli4_hba.cpu_map = kzalloc((sizeof(struct lpfc_vector_map_info) *
5451 phba->sli4_hba.num_present_cpu),
5452 GFP_KERNEL);
5453 if (!phba->sli4_hba.cpu_map) {
5454 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5455 "3327 Failed allocate memory for msi-x "
5456 "interrupt vector mapping\n");
5457 rc = -ENOMEM;
5458 goto out_free_msix;
5459 }
5460 if (lpfc_used_cpu == NULL) {
5461 lpfc_used_cpu = kzalloc((sizeof(uint16_t) * lpfc_present_cpu),
5462 GFP_KERNEL);
5463 if (!lpfc_used_cpu) {
5464 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5465 "3335 Failed allocate memory for msi-x "
5466 "interrupt vector mapping\n");
5467 kfree(phba->sli4_hba.cpu_map);
5468 rc = -ENOMEM;
5469 goto out_free_msix;
5470 }
5471 for (i = 0; i < lpfc_present_cpu; i++)
5472 lpfc_used_cpu[i] = LPFC_VECTOR_MAP_EMPTY;
5473 }
5474
5475
5476 cpup = phba->sli4_hba.cpu_map;
5477 rc = 0;
5478 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
5479 cpup->channel_id = rc;
5480 rc++;
5481 if (rc >= phba->cfg_fcp_io_channel)
5482 rc = 0;
5483 }
5484
5485
5486
5487
5488
5489 if (phba->cfg_sriov_nr_virtfn > 0) {
5490 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
5491 phba->cfg_sriov_nr_virtfn);
5492 if (rc) {
5493 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
5494 "3020 Requested number of SR-IOV "
5495 "virtual functions (%d) is not "
5496 "supported\n",
5497 phba->cfg_sriov_nr_virtfn);
5498 phba->cfg_sriov_nr_virtfn = 0;
5499 }
5500 }
5501
5502 return 0;
5503
5504out_free_msix:
5505 kfree(phba->sli4_hba.msix_entries);
5506out_free_fcp_eq_hdl:
5507 kfree(phba->sli4_hba.fcp_eq_hdl);
5508out_free_fcf_rr_bmask:
5509 kfree(phba->fcf.fcf_rr_bmask);
5510out_remove_rpi_hdrs:
5511 lpfc_sli4_remove_rpi_hdrs(phba);
5512out_free_active_sgl:
5513 lpfc_free_active_sgl(phba);
5514out_destroy_cq_event_pool:
5515 lpfc_sli4_cq_event_pool_destroy(phba);
5516out_free_bsmbx:
5517 lpfc_destroy_bootstrap_mbox(phba);
5518out_free_mem:
5519 lpfc_mem_free(phba);
5520 return rc;
5521}
5522
5523
5524
5525
5526
5527
5528
5529
5530static void
5531lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
5532{
5533 struct lpfc_fcf_conn_entry *conn_entry, *next_conn_entry;
5534
5535
5536 kfree(phba->sli4_hba.cpu_map);
5537 phba->sli4_hba.num_present_cpu = 0;
5538 phba->sli4_hba.num_online_cpu = 0;
5539 phba->sli4_hba.curr_disp_cpu = 0;
5540
5541
5542 kfree(phba->sli4_hba.msix_entries);
5543
5544
5545 kfree(phba->sli4_hba.fcp_eq_hdl);
5546
5547
5548 lpfc_sli4_remove_rpi_hdrs(phba);
5549 lpfc_sli4_remove_rpis(phba);
5550
5551
5552 kfree(phba->fcf.fcf_rr_bmask);
5553
5554
5555 lpfc_free_active_sgl(phba);
5556 lpfc_free_els_sgl_list(phba);
5557
5558
5559 lpfc_sli4_cq_event_release_all(phba);
5560 lpfc_sli4_cq_event_pool_destroy(phba);
5561
5562
5563 lpfc_sli4_dealloc_resource_identifiers(phba);
5564
5565
5566 lpfc_destroy_bootstrap_mbox(phba);
5567
5568
5569 lpfc_mem_free_all(phba);
5570
5571
5572 list_for_each_entry_safe(conn_entry, next_conn_entry,
5573 &phba->fcf_conn_rec_list, list) {
5574 list_del_init(&conn_entry->list);
5575 kfree(conn_entry);
5576 }
5577
5578 return;
5579}
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591int
5592lpfc_init_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
5593{
5594 phba->lpfc_hba_init_link = lpfc_hba_init_link;
5595 phba->lpfc_hba_down_link = lpfc_hba_down_link;
5596 phba->lpfc_selective_reset = lpfc_selective_reset;
5597 switch (dev_grp) {
5598 case LPFC_PCI_DEV_LP:
5599 phba->lpfc_hba_down_post = lpfc_hba_down_post_s3;
5600 phba->lpfc_handle_eratt = lpfc_handle_eratt_s3;
5601 phba->lpfc_stop_port = lpfc_stop_port_s3;
5602 break;
5603 case LPFC_PCI_DEV_OC:
5604 phba->lpfc_hba_down_post = lpfc_hba_down_post_s4;
5605 phba->lpfc_handle_eratt = lpfc_handle_eratt_s4;
5606 phba->lpfc_stop_port = lpfc_stop_port_s4;
5607 break;
5608 default:
5609 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5610 "1431 Invalid HBA PCI-device group: 0x%x\n",
5611 dev_grp);
5612 return -ENODEV;
5613 break;
5614 }
5615 return 0;
5616}
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629static int
5630lpfc_setup_driver_resource_phase1(struct lpfc_hba *phba)
5631{
5632
5633
5634
5635 atomic_set(&phba->fast_event_count, 0);
5636 spin_lock_init(&phba->hbalock);
5637
5638
5639 spin_lock_init(&phba->ndlp_lock);
5640
5641 INIT_LIST_HEAD(&phba->port_list);
5642 INIT_LIST_HEAD(&phba->work_list);
5643 init_waitqueue_head(&phba->wait_4_mlo_m_q);
5644
5645
5646 init_waitqueue_head(&phba->work_waitq);
5647
5648
5649 spin_lock_init(&phba->scsi_buf_list_get_lock);
5650 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_get);
5651 spin_lock_init(&phba->scsi_buf_list_put_lock);
5652 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
5653
5654
5655 INIT_LIST_HEAD(&phba->fabric_iocb_list);
5656
5657
5658 INIT_LIST_HEAD(&phba->elsbuf);
5659
5660
5661 INIT_LIST_HEAD(&phba->fcf_conn_rec_list);
5662
5663
5664 spin_lock_init(&phba->devicelock);
5665 INIT_LIST_HEAD(&phba->luns);
5666
5667 return 0;
5668}
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681static int
5682lpfc_setup_driver_resource_phase2(struct lpfc_hba *phba)
5683{
5684 int error;
5685
5686
5687 phba->worker_thread = kthread_run(lpfc_do_work, phba,
5688 "lpfc_worker_%d", phba->brd_no);
5689 if (IS_ERR(phba->worker_thread)) {
5690 error = PTR_ERR(phba->worker_thread);
5691 return error;
5692 }
5693
5694 return 0;
5695}
5696
5697
5698
5699
5700
5701
5702
5703
5704
5705static void
5706lpfc_unset_driver_resource_phase2(struct lpfc_hba *phba)
5707{
5708
5709 kthread_stop(phba->worker_thread);
5710}
5711
5712
5713
5714
5715
5716
5717
5718static void
5719lpfc_free_iocb_list(struct lpfc_hba *phba)
5720{
5721 struct lpfc_iocbq *iocbq_entry = NULL, *iocbq_next = NULL;
5722
5723 spin_lock_irq(&phba->hbalock);
5724 list_for_each_entry_safe(iocbq_entry, iocbq_next,
5725 &phba->lpfc_iocb_list, list) {
5726 list_del(&iocbq_entry->list);
5727 kfree(iocbq_entry);
5728 phba->total_iocbq_bufs--;
5729 }
5730 spin_unlock_irq(&phba->hbalock);
5731
5732 return;
5733}
5734
5735
5736
5737
5738
5739
5740
5741
5742
5743
5744
5745
5746static int
5747lpfc_init_iocb_list(struct lpfc_hba *phba, int iocb_count)
5748{
5749 struct lpfc_iocbq *iocbq_entry = NULL;
5750 uint16_t iotag;
5751 int i;
5752
5753
5754 INIT_LIST_HEAD(&phba->lpfc_iocb_list);
5755 for (i = 0; i < iocb_count; i++) {
5756 iocbq_entry = kzalloc(sizeof(struct lpfc_iocbq), GFP_KERNEL);
5757 if (iocbq_entry == NULL) {
5758 printk(KERN_ERR "%s: only allocated %d iocbs of "
5759 "expected %d count. Unloading driver.\n",
5760 __func__, i, LPFC_IOCB_LIST_CNT);
5761 goto out_free_iocbq;
5762 }
5763
5764 iotag = lpfc_sli_next_iotag(phba, iocbq_entry);
5765 if (iotag == 0) {
5766 kfree(iocbq_entry);
5767 printk(KERN_ERR "%s: failed to allocate IOTAG. "
5768 "Unloading driver.\n", __func__);
5769 goto out_free_iocbq;
5770 }
5771 iocbq_entry->sli4_lxritag = NO_XRI;
5772 iocbq_entry->sli4_xritag = NO_XRI;
5773
5774 spin_lock_irq(&phba->hbalock);
5775 list_add(&iocbq_entry->list, &phba->lpfc_iocb_list);
5776 phba->total_iocbq_bufs++;
5777 spin_unlock_irq(&phba->hbalock);
5778 }
5779
5780 return 0;
5781
5782out_free_iocbq:
5783 lpfc_free_iocb_list(phba);
5784
5785 return -ENOMEM;
5786}
5787
5788
5789
5790
5791
5792
5793
5794
5795void
5796lpfc_free_sgl_list(struct lpfc_hba *phba, struct list_head *sglq_list)
5797{
5798 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
5799
5800 list_for_each_entry_safe(sglq_entry, sglq_next, sglq_list, list) {
5801 list_del(&sglq_entry->list);
5802 lpfc_mbuf_free(phba, sglq_entry->virt, sglq_entry->phys);
5803 kfree(sglq_entry);
5804 }
5805}
5806
5807
5808
5809
5810
5811
5812
5813static void
5814lpfc_free_els_sgl_list(struct lpfc_hba *phba)
5815{
5816 LIST_HEAD(sglq_list);
5817 struct lpfc_sli_ring *pring = &phba->sli.ring[LPFC_ELS_RING];
5818
5819
5820 spin_lock_irq(&phba->hbalock);
5821 spin_lock(&pring->ring_lock);
5822 list_splice_init(&phba->sli4_hba.lpfc_sgl_list, &sglq_list);
5823 spin_unlock(&pring->ring_lock);
5824 spin_unlock_irq(&phba->hbalock);
5825
5826
5827 lpfc_free_sgl_list(phba, &sglq_list);
5828}
5829
5830
5831
5832
5833
5834
5835
5836
5837static int
5838lpfc_init_active_sgl_array(struct lpfc_hba *phba)
5839{
5840 int size;
5841 size = sizeof(struct lpfc_sglq *);
5842 size *= phba->sli4_hba.max_cfg_param.max_xri;
5843
5844 phba->sli4_hba.lpfc_sglq_active_list =
5845 kzalloc(size, GFP_KERNEL);
5846 if (!phba->sli4_hba.lpfc_sglq_active_list)
5847 return -ENOMEM;
5848 return 0;
5849}
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859static void
5860lpfc_free_active_sgl(struct lpfc_hba *phba)
5861{
5862 kfree(phba->sli4_hba.lpfc_sglq_active_list);
5863}
5864
5865
5866
5867
5868
5869
5870
5871
5872
5873static void
5874lpfc_init_sgl_list(struct lpfc_hba *phba)
5875{
5876
5877 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_sgl_list);
5878 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_els_sgl_list);
5879
5880
5881 phba->sli4_hba.els_xri_cnt = 0;
5882
5883
5884 phba->sli4_hba.scsi_xri_cnt = 0;
5885}
5886
5887
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901int
5902lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *phba)
5903{
5904 int rc = 0;
5905 struct lpfc_rpi_hdr *rpi_hdr;
5906
5907 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_hdr_list);
5908 if (!phba->sli4_hba.rpi_hdrs_in_use)
5909 return rc;
5910 if (phba->sli4_hba.extents_in_use)
5911 return -EIO;
5912
5913 rpi_hdr = lpfc_sli4_create_rpi_hdr(phba);
5914 if (!rpi_hdr) {
5915 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
5916 "0391 Error during rpi post operation\n");
5917 lpfc_sli4_remove_rpis(phba);
5918 rc = -ENODEV;
5919 }
5920
5921 return rc;
5922}
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937struct lpfc_rpi_hdr *
5938lpfc_sli4_create_rpi_hdr(struct lpfc_hba *phba)
5939{
5940 uint16_t rpi_limit, curr_rpi_range;
5941 struct lpfc_dmabuf *dmabuf;
5942 struct lpfc_rpi_hdr *rpi_hdr;
5943 uint32_t rpi_count;
5944
5945
5946
5947
5948
5949
5950 if (!phba->sli4_hba.rpi_hdrs_in_use)
5951 return NULL;
5952 if (phba->sli4_hba.extents_in_use)
5953 return NULL;
5954
5955
5956 rpi_limit = phba->sli4_hba.max_cfg_param.rpi_base +
5957 phba->sli4_hba.max_cfg_param.max_rpi - 1;
5958
5959 spin_lock_irq(&phba->hbalock);
5960
5961
5962
5963
5964
5965 curr_rpi_range = phba->sli4_hba.next_rpi;
5966 spin_unlock_irq(&phba->hbalock);
5967
5968
5969
5970
5971
5972
5973 if ((curr_rpi_range + (LPFC_RPI_HDR_COUNT - 1)) > rpi_limit)
5974 rpi_count = rpi_limit - curr_rpi_range;
5975 else
5976 rpi_count = LPFC_RPI_HDR_COUNT;
5977
5978 if (!rpi_count)
5979 return NULL;
5980
5981
5982
5983
5984 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
5985 if (!dmabuf)
5986 return NULL;
5987
5988 dmabuf->virt = dma_zalloc_coherent(&phba->pcidev->dev,
5989 LPFC_HDR_TEMPLATE_SIZE,
5990 &dmabuf->phys, GFP_KERNEL);
5991 if (!dmabuf->virt) {
5992 rpi_hdr = NULL;
5993 goto err_free_dmabuf;
5994 }
5995
5996 if (!IS_ALIGNED(dmabuf->phys, LPFC_HDR_TEMPLATE_SIZE)) {
5997 rpi_hdr = NULL;
5998 goto err_free_coherent;
5999 }
6000
6001
6002 rpi_hdr = kzalloc(sizeof(struct lpfc_rpi_hdr), GFP_KERNEL);
6003 if (!rpi_hdr)
6004 goto err_free_coherent;
6005
6006 rpi_hdr->dmabuf = dmabuf;
6007 rpi_hdr->len = LPFC_HDR_TEMPLATE_SIZE;
6008 rpi_hdr->page_count = 1;
6009 spin_lock_irq(&phba->hbalock);
6010
6011
6012 rpi_hdr->start_rpi = curr_rpi_range;
6013 list_add_tail(&rpi_hdr->list, &phba->sli4_hba.lpfc_rpi_hdr_list);
6014
6015
6016
6017
6018
6019 phba->sli4_hba.next_rpi += rpi_count;
6020 spin_unlock_irq(&phba->hbalock);
6021 return rpi_hdr;
6022
6023 err_free_coherent:
6024 dma_free_coherent(&phba->pcidev->dev, LPFC_HDR_TEMPLATE_SIZE,
6025 dmabuf->virt, dmabuf->phys);
6026 err_free_dmabuf:
6027 kfree(dmabuf);
6028 return NULL;
6029}
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040void
6041lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *phba)
6042{
6043 struct lpfc_rpi_hdr *rpi_hdr, *next_rpi_hdr;
6044
6045 if (!phba->sli4_hba.rpi_hdrs_in_use)
6046 goto exit;
6047
6048 list_for_each_entry_safe(rpi_hdr, next_rpi_hdr,
6049 &phba->sli4_hba.lpfc_rpi_hdr_list, list) {
6050 list_del(&rpi_hdr->list);
6051 dma_free_coherent(&phba->pcidev->dev, rpi_hdr->len,
6052 rpi_hdr->dmabuf->virt, rpi_hdr->dmabuf->phys);
6053 kfree(rpi_hdr->dmabuf);
6054 kfree(rpi_hdr);
6055 }
6056 exit:
6057
6058 phba->sli4_hba.next_rpi = 0;
6059}
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073static struct lpfc_hba *
6074lpfc_hba_alloc(struct pci_dev *pdev)
6075{
6076 struct lpfc_hba *phba;
6077
6078
6079 phba = kzalloc(sizeof(struct lpfc_hba), GFP_KERNEL);
6080 if (!phba) {
6081 dev_err(&pdev->dev, "failed to allocate hba struct\n");
6082 return NULL;
6083 }
6084
6085
6086 phba->pcidev = pdev;
6087
6088
6089 phba->brd_no = lpfc_get_instance();
6090 if (phba->brd_no < 0) {
6091 kfree(phba);
6092 return NULL;
6093 }
6094
6095 spin_lock_init(&phba->ct_ev_lock);
6096 INIT_LIST_HEAD(&phba->ct_ev_waiters);
6097
6098 return phba;
6099}
6100
6101
6102
6103
6104
6105
6106
6107
6108static void
6109lpfc_hba_free(struct lpfc_hba *phba)
6110{
6111
6112 idr_remove(&lpfc_hba_index, phba->brd_no);
6113
6114
6115 kfree(phba->sli.ring);
6116 phba->sli.ring = NULL;
6117
6118 kfree(phba);
6119 return;
6120}
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133static int
6134lpfc_create_shost(struct lpfc_hba *phba)
6135{
6136 struct lpfc_vport *vport;
6137 struct Scsi_Host *shost;
6138
6139
6140 phba->fc_edtov = FF_DEF_EDTOV;
6141 phba->fc_ratov = FF_DEF_RATOV;
6142 phba->fc_altov = FF_DEF_ALTOV;
6143 phba->fc_arbtov = FF_DEF_ARBTOV;
6144
6145 atomic_set(&phba->sdev_cnt, 0);
6146 vport = lpfc_create_port(phba, phba->brd_no, &phba->pcidev->dev);
6147 if (!vport)
6148 return -ENODEV;
6149
6150 shost = lpfc_shost_from_vport(vport);
6151 phba->pport = vport;
6152 lpfc_debugfs_initialize(vport);
6153
6154 pci_set_drvdata(phba->pcidev, shost);
6155
6156
6157
6158
6159
6160 vport->load_flag |= FC_ALLOW_FDMI;
6161 if (phba->cfg_fdmi_on > LPFC_FDMI_NO_SUPPORT) {
6162
6163
6164 vport->fdmi_hba_mask = LPFC_FDMI2_HBA_ATTR;
6165 if (phba->cfg_fdmi_on == LPFC_FDMI_SMART_SAN)
6166 vport->fdmi_port_mask = LPFC_FDMI2_SMART_ATTR;
6167 else
6168 vport->fdmi_port_mask = LPFC_FDMI2_PORT_ATTR;
6169 }
6170 return 0;
6171}
6172
6173
6174
6175
6176
6177
6178
6179
6180static void
6181lpfc_destroy_shost(struct lpfc_hba *phba)
6182{
6183 struct lpfc_vport *vport = phba->pport;
6184
6185
6186 destroy_port(vport);
6187
6188 return;
6189}
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199static void
6200lpfc_setup_bg(struct lpfc_hba *phba, struct Scsi_Host *shost)
6201{
6202 uint32_t old_mask;
6203 uint32_t old_guard;
6204
6205 int pagecnt = 10;
6206 if (lpfc_prot_mask && lpfc_prot_guard) {
6207 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6208 "1478 Registering BlockGuard with the "
6209 "SCSI layer\n");
6210
6211 old_mask = lpfc_prot_mask;
6212 old_guard = lpfc_prot_guard;
6213
6214
6215 lpfc_prot_mask &= (SHOST_DIF_TYPE1_PROTECTION |
6216 SHOST_DIX_TYPE0_PROTECTION |
6217 SHOST_DIX_TYPE1_PROTECTION);
6218 lpfc_prot_guard &= (SHOST_DIX_GUARD_IP | SHOST_DIX_GUARD_CRC);
6219
6220
6221 if (lpfc_prot_mask == SHOST_DIX_TYPE1_PROTECTION)
6222 lpfc_prot_mask |= SHOST_DIF_TYPE1_PROTECTION;
6223
6224 if (lpfc_prot_mask && lpfc_prot_guard) {
6225 if ((old_mask != lpfc_prot_mask) ||
6226 (old_guard != lpfc_prot_guard))
6227 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6228 "1475 Registering BlockGuard with the "
6229 "SCSI layer: mask %d guard %d\n",
6230 lpfc_prot_mask, lpfc_prot_guard);
6231
6232 scsi_host_set_prot(shost, lpfc_prot_mask);
6233 scsi_host_set_guard(shost, lpfc_prot_guard);
6234 } else
6235 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6236 "1479 Not Registering BlockGuard with the SCSI "
6237 "layer, Bad protection parameters: %d %d\n",
6238 old_mask, old_guard);
6239 }
6240
6241 if (!_dump_buf_data) {
6242 while (pagecnt) {
6243 spin_lock_init(&_dump_buf_lock);
6244 _dump_buf_data =
6245 (char *) __get_free_pages(GFP_KERNEL, pagecnt);
6246 if (_dump_buf_data) {
6247 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
6248 "9043 BLKGRD: allocated %d pages for "
6249 "_dump_buf_data at 0x%p\n",
6250 (1 << pagecnt), _dump_buf_data);
6251 _dump_buf_data_order = pagecnt;
6252 memset(_dump_buf_data, 0,
6253 ((1 << PAGE_SHIFT) << pagecnt));
6254 break;
6255 } else
6256 --pagecnt;
6257 }
6258 if (!_dump_buf_data_order)
6259 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
6260 "9044 BLKGRD: ERROR unable to allocate "
6261 "memory for hexdump\n");
6262 } else
6263 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
6264 "9045 BLKGRD: already allocated _dump_buf_data=0x%p"
6265 "\n", _dump_buf_data);
6266 if (!_dump_buf_dif) {
6267 while (pagecnt) {
6268 _dump_buf_dif =
6269 (char *) __get_free_pages(GFP_KERNEL, pagecnt);
6270 if (_dump_buf_dif) {
6271 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
6272 "9046 BLKGRD: allocated %d pages for "
6273 "_dump_buf_dif at 0x%p\n",
6274 (1 << pagecnt), _dump_buf_dif);
6275 _dump_buf_dif_order = pagecnt;
6276 memset(_dump_buf_dif, 0,
6277 ((1 << PAGE_SHIFT) << pagecnt));
6278 break;
6279 } else
6280 --pagecnt;
6281 }
6282 if (!_dump_buf_dif_order)
6283 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
6284 "9047 BLKGRD: ERROR unable to allocate "
6285 "memory for hexdump\n");
6286 } else
6287 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
6288 "9048 BLKGRD: already allocated _dump_buf_dif=0x%p\n",
6289 _dump_buf_dif);
6290}
6291
6292
6293
6294
6295
6296
6297
6298
6299static void
6300lpfc_post_init_setup(struct lpfc_hba *phba)
6301{
6302 struct Scsi_Host *shost;
6303 struct lpfc_adapter_event_header adapter_event;
6304
6305
6306 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
6307
6308
6309
6310
6311
6312 shost = pci_get_drvdata(phba->pcidev);
6313 shost->can_queue = phba->cfg_hba_queue_depth - 10;
6314 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED)
6315 lpfc_setup_bg(phba, shost);
6316
6317 lpfc_host_attrib_init(shost);
6318
6319 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
6320 spin_lock_irq(shost->host_lock);
6321 lpfc_poll_start_timer(phba);
6322 spin_unlock_irq(shost->host_lock);
6323 }
6324
6325 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6326 "0428 Perform SCSI scan\n");
6327
6328 adapter_event.event_type = FC_REG_ADAPTER_EVENT;
6329 adapter_event.subcategory = LPFC_EVENT_ARRIVAL;
6330 fc_host_post_vendor_event(shost, fc_get_event_number(),
6331 sizeof(adapter_event),
6332 (char *) &adapter_event,
6333 LPFC_NL_VENDOR_ID);
6334 return;
6335}
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348static int
6349lpfc_sli_pci_mem_setup(struct lpfc_hba *phba)
6350{
6351 struct pci_dev *pdev;
6352 unsigned long bar0map_len, bar2map_len;
6353 int i, hbq_count;
6354 void *ptr;
6355 int error = -ENODEV;
6356
6357
6358 if (!phba->pcidev)
6359 return error;
6360 else
6361 pdev = phba->pcidev;
6362
6363
6364 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0
6365 || pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(64)) != 0) {
6366 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0
6367 || pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(32)) != 0) {
6368 return error;
6369 }
6370 }
6371
6372
6373
6374
6375 phba->pci_bar0_map = pci_resource_start(pdev, 0);
6376 bar0map_len = pci_resource_len(pdev, 0);
6377
6378 phba->pci_bar2_map = pci_resource_start(pdev, 2);
6379 bar2map_len = pci_resource_len(pdev, 2);
6380
6381
6382 phba->slim_memmap_p = ioremap(phba->pci_bar0_map, bar0map_len);
6383 if (!phba->slim_memmap_p) {
6384 dev_printk(KERN_ERR, &pdev->dev,
6385 "ioremap failed for SLIM memory.\n");
6386 goto out;
6387 }
6388
6389
6390 phba->ctrl_regs_memmap_p = ioremap(phba->pci_bar2_map, bar2map_len);
6391 if (!phba->ctrl_regs_memmap_p) {
6392 dev_printk(KERN_ERR, &pdev->dev,
6393 "ioremap failed for HBA control registers.\n");
6394 goto out_iounmap_slim;
6395 }
6396
6397
6398 phba->slim2p.virt = dma_zalloc_coherent(&pdev->dev, SLI2_SLIM_SIZE,
6399 &phba->slim2p.phys, GFP_KERNEL);
6400 if (!phba->slim2p.virt)
6401 goto out_iounmap;
6402
6403 phba->mbox = phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, mbx);
6404 phba->mbox_ext = (phba->slim2p.virt +
6405 offsetof(struct lpfc_sli2_slim, mbx_ext_words));
6406 phba->pcb = (phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, pcb));
6407 phba->IOCBs = (phba->slim2p.virt +
6408 offsetof(struct lpfc_sli2_slim, IOCBs));
6409
6410 phba->hbqslimp.virt = dma_alloc_coherent(&pdev->dev,
6411 lpfc_sli_hbq_size(),
6412 &phba->hbqslimp.phys,
6413 GFP_KERNEL);
6414 if (!phba->hbqslimp.virt)
6415 goto out_free_slim;
6416
6417 hbq_count = lpfc_sli_hbq_count();
6418 ptr = phba->hbqslimp.virt;
6419 for (i = 0; i < hbq_count; ++i) {
6420 phba->hbqs[i].hbq_virt = ptr;
6421 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
6422 ptr += (lpfc_hbq_defs[i]->entry_count *
6423 sizeof(struct lpfc_hbq_entry));
6424 }
6425 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_els_hbq_alloc;
6426 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_els_hbq_free;
6427
6428 memset(phba->hbqslimp.virt, 0, lpfc_sli_hbq_size());
6429
6430 INIT_LIST_HEAD(&phba->rb_pend_list);
6431
6432 phba->MBslimaddr = phba->slim_memmap_p;
6433 phba->HAregaddr = phba->ctrl_regs_memmap_p + HA_REG_OFFSET;
6434 phba->CAregaddr = phba->ctrl_regs_memmap_p + CA_REG_OFFSET;
6435 phba->HSregaddr = phba->ctrl_regs_memmap_p + HS_REG_OFFSET;
6436 phba->HCregaddr = phba->ctrl_regs_memmap_p + HC_REG_OFFSET;
6437
6438 return 0;
6439
6440out_free_slim:
6441 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
6442 phba->slim2p.virt, phba->slim2p.phys);
6443out_iounmap:
6444 iounmap(phba->ctrl_regs_memmap_p);
6445out_iounmap_slim:
6446 iounmap(phba->slim_memmap_p);
6447out:
6448 return error;
6449}
6450
6451
6452
6453
6454
6455
6456
6457
6458static void
6459lpfc_sli_pci_mem_unset(struct lpfc_hba *phba)
6460{
6461 struct pci_dev *pdev;
6462
6463
6464 if (!phba->pcidev)
6465 return;
6466 else
6467 pdev = phba->pcidev;
6468
6469
6470 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
6471 phba->hbqslimp.virt, phba->hbqslimp.phys);
6472 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
6473 phba->slim2p.virt, phba->slim2p.phys);
6474
6475
6476 iounmap(phba->ctrl_regs_memmap_p);
6477 iounmap(phba->slim_memmap_p);
6478
6479 return;
6480}
6481
6482
6483
6484
6485
6486
6487
6488
6489
6490
6491int
6492lpfc_sli4_post_status_check(struct lpfc_hba *phba)
6493{
6494 struct lpfc_register portsmphr_reg, uerrlo_reg, uerrhi_reg;
6495 struct lpfc_register reg_data;
6496 int i, port_error = 0;
6497 uint32_t if_type;
6498
6499 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
6500 memset(®_data, 0, sizeof(reg_data));
6501 if (!phba->sli4_hba.PSMPHRregaddr)
6502 return -ENODEV;
6503
6504
6505 for (i = 0; i < 3000; i++) {
6506 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
6507 &portsmphr_reg.word0) ||
6508 (bf_get(lpfc_port_smphr_perr, &portsmphr_reg))) {
6509
6510 port_error = -ENODEV;
6511 break;
6512 }
6513 if (LPFC_POST_STAGE_PORT_READY ==
6514 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg))
6515 break;
6516 msleep(10);
6517 }
6518
6519
6520
6521
6522
6523 if (port_error) {
6524 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6525 "1408 Port Failed POST - portsmphr=0x%x, "
6526 "perr=x%x, sfi=x%x, nip=x%x, ipc=x%x, scr1=x%x, "
6527 "scr2=x%x, hscratch=x%x, pstatus=x%x\n",
6528 portsmphr_reg.word0,
6529 bf_get(lpfc_port_smphr_perr, &portsmphr_reg),
6530 bf_get(lpfc_port_smphr_sfi, &portsmphr_reg),
6531 bf_get(lpfc_port_smphr_nip, &portsmphr_reg),
6532 bf_get(lpfc_port_smphr_ipc, &portsmphr_reg),
6533 bf_get(lpfc_port_smphr_scr1, &portsmphr_reg),
6534 bf_get(lpfc_port_smphr_scr2, &portsmphr_reg),
6535 bf_get(lpfc_port_smphr_host_scratch, &portsmphr_reg),
6536 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg));
6537 } else {
6538 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6539 "2534 Device Info: SLIFamily=0x%x, "
6540 "SLIRev=0x%x, IFType=0x%x, SLIHint_1=0x%x, "
6541 "SLIHint_2=0x%x, FT=0x%x\n",
6542 bf_get(lpfc_sli_intf_sli_family,
6543 &phba->sli4_hba.sli_intf),
6544 bf_get(lpfc_sli_intf_slirev,
6545 &phba->sli4_hba.sli_intf),
6546 bf_get(lpfc_sli_intf_if_type,
6547 &phba->sli4_hba.sli_intf),
6548 bf_get(lpfc_sli_intf_sli_hint1,
6549 &phba->sli4_hba.sli_intf),
6550 bf_get(lpfc_sli_intf_sli_hint2,
6551 &phba->sli4_hba.sli_intf),
6552 bf_get(lpfc_sli_intf_func_type,
6553 &phba->sli4_hba.sli_intf));
6554
6555
6556
6557
6558
6559 if_type = bf_get(lpfc_sli_intf_if_type,
6560 &phba->sli4_hba.sli_intf);
6561 switch (if_type) {
6562 case LPFC_SLI_INTF_IF_TYPE_0:
6563 phba->sli4_hba.ue_mask_lo =
6564 readl(phba->sli4_hba.u.if_type0.UEMASKLOregaddr);
6565 phba->sli4_hba.ue_mask_hi =
6566 readl(phba->sli4_hba.u.if_type0.UEMASKHIregaddr);
6567 uerrlo_reg.word0 =
6568 readl(phba->sli4_hba.u.if_type0.UERRLOregaddr);
6569 uerrhi_reg.word0 =
6570 readl(phba->sli4_hba.u.if_type0.UERRHIregaddr);
6571 if ((~phba->sli4_hba.ue_mask_lo & uerrlo_reg.word0) ||
6572 (~phba->sli4_hba.ue_mask_hi & uerrhi_reg.word0)) {
6573 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6574 "1422 Unrecoverable Error "
6575 "Detected during POST "
6576 "uerr_lo_reg=0x%x, "
6577 "uerr_hi_reg=0x%x, "
6578 "ue_mask_lo_reg=0x%x, "
6579 "ue_mask_hi_reg=0x%x\n",
6580 uerrlo_reg.word0,
6581 uerrhi_reg.word0,
6582 phba->sli4_hba.ue_mask_lo,
6583 phba->sli4_hba.ue_mask_hi);
6584 port_error = -ENODEV;
6585 }
6586 break;
6587 case LPFC_SLI_INTF_IF_TYPE_2:
6588
6589 if (lpfc_readl(phba->sli4_hba.u.if_type2.STATUSregaddr,
6590 ®_data.word0) ||
6591 (bf_get(lpfc_sliport_status_err, ®_data) &&
6592 !bf_get(lpfc_sliport_status_rn, ®_data))) {
6593 phba->work_status[0] =
6594 readl(phba->sli4_hba.u.if_type2.
6595 ERR1regaddr);
6596 phba->work_status[1] =
6597 readl(phba->sli4_hba.u.if_type2.
6598 ERR2regaddr);
6599 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6600 "2888 Unrecoverable port error "
6601 "following POST: port status reg "
6602 "0x%x, port_smphr reg 0x%x, "
6603 "error 1=0x%x, error 2=0x%x\n",
6604 reg_data.word0,
6605 portsmphr_reg.word0,
6606 phba->work_status[0],
6607 phba->work_status[1]);
6608 port_error = -ENODEV;
6609 }
6610 break;
6611 case LPFC_SLI_INTF_IF_TYPE_1:
6612 default:
6613 break;
6614 }
6615 }
6616 return port_error;
6617}
6618
6619
6620
6621
6622
6623
6624
6625
6626
6627static void
6628lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
6629{
6630 switch (if_type) {
6631 case LPFC_SLI_INTF_IF_TYPE_0:
6632 phba->sli4_hba.u.if_type0.UERRLOregaddr =
6633 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_LO;
6634 phba->sli4_hba.u.if_type0.UERRHIregaddr =
6635 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_HI;
6636 phba->sli4_hba.u.if_type0.UEMASKLOregaddr =
6637 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_LO;
6638 phba->sli4_hba.u.if_type0.UEMASKHIregaddr =
6639 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_HI;
6640 phba->sli4_hba.SLIINTFregaddr =
6641 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
6642 break;
6643 case LPFC_SLI_INTF_IF_TYPE_2:
6644 phba->sli4_hba.u.if_type2.ERR1regaddr =
6645 phba->sli4_hba.conf_regs_memmap_p +
6646 LPFC_CTL_PORT_ER1_OFFSET;
6647 phba->sli4_hba.u.if_type2.ERR2regaddr =
6648 phba->sli4_hba.conf_regs_memmap_p +
6649 LPFC_CTL_PORT_ER2_OFFSET;
6650 phba->sli4_hba.u.if_type2.CTRLregaddr =
6651 phba->sli4_hba.conf_regs_memmap_p +
6652 LPFC_CTL_PORT_CTL_OFFSET;
6653 phba->sli4_hba.u.if_type2.STATUSregaddr =
6654 phba->sli4_hba.conf_regs_memmap_p +
6655 LPFC_CTL_PORT_STA_OFFSET;
6656 phba->sli4_hba.SLIINTFregaddr =
6657 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
6658 phba->sli4_hba.PSMPHRregaddr =
6659 phba->sli4_hba.conf_regs_memmap_p +
6660 LPFC_CTL_PORT_SEM_OFFSET;
6661 phba->sli4_hba.RQDBregaddr =
6662 phba->sli4_hba.conf_regs_memmap_p +
6663 LPFC_ULP0_RQ_DOORBELL;
6664 phba->sli4_hba.WQDBregaddr =
6665 phba->sli4_hba.conf_regs_memmap_p +
6666 LPFC_ULP0_WQ_DOORBELL;
6667 phba->sli4_hba.EQCQDBregaddr =
6668 phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL;
6669 phba->sli4_hba.MQDBregaddr =
6670 phba->sli4_hba.conf_regs_memmap_p + LPFC_MQ_DOORBELL;
6671 phba->sli4_hba.BMBXregaddr =
6672 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
6673 break;
6674 case LPFC_SLI_INTF_IF_TYPE_1:
6675 default:
6676 dev_printk(KERN_ERR, &phba->pcidev->dev,
6677 "FATAL - unsupported SLI4 interface type - %d\n",
6678 if_type);
6679 break;
6680 }
6681}
6682
6683
6684
6685
6686
6687
6688
6689
6690static void
6691lpfc_sli4_bar1_register_memmap(struct lpfc_hba *phba)
6692{
6693 phba->sli4_hba.PSMPHRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
6694 LPFC_SLIPORT_IF0_SMPHR;
6695 phba->sli4_hba.ISRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
6696 LPFC_HST_ISR0;
6697 phba->sli4_hba.IMRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
6698 LPFC_HST_IMR0;
6699 phba->sli4_hba.ISCRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
6700 LPFC_HST_ISCR0;
6701}
6702
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712
6713static int
6714lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf)
6715{
6716 if (vf > LPFC_VIR_FUNC_MAX)
6717 return -ENODEV;
6718
6719 phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
6720 vf * LPFC_VFR_PAGE_SIZE +
6721 LPFC_ULP0_RQ_DOORBELL);
6722 phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
6723 vf * LPFC_VFR_PAGE_SIZE +
6724 LPFC_ULP0_WQ_DOORBELL);
6725 phba->sli4_hba.EQCQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
6726 vf * LPFC_VFR_PAGE_SIZE + LPFC_EQCQ_DOORBELL);
6727 phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
6728 vf * LPFC_VFR_PAGE_SIZE + LPFC_MQ_DOORBELL);
6729 phba->sli4_hba.BMBXregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
6730 vf * LPFC_VFR_PAGE_SIZE + LPFC_BMBX);
6731 return 0;
6732}
6733
6734
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748
6749static int
6750lpfc_create_bootstrap_mbox(struct lpfc_hba *phba)
6751{
6752 uint32_t bmbx_size;
6753 struct lpfc_dmabuf *dmabuf;
6754 struct dma_address *dma_address;
6755 uint32_t pa_addr;
6756 uint64_t phys_addr;
6757
6758 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
6759 if (!dmabuf)
6760 return -ENOMEM;
6761
6762
6763
6764
6765
6766 bmbx_size = sizeof(struct lpfc_bmbx_create) + (LPFC_ALIGN_16_BYTE - 1);
6767 dmabuf->virt = dma_zalloc_coherent(&phba->pcidev->dev, bmbx_size,
6768 &dmabuf->phys, GFP_KERNEL);
6769 if (!dmabuf->virt) {
6770 kfree(dmabuf);
6771 return -ENOMEM;
6772 }
6773
6774
6775
6776
6777
6778
6779
6780
6781 phba->sli4_hba.bmbx.dmabuf = dmabuf;
6782 phba->sli4_hba.bmbx.bmbx_size = bmbx_size;
6783
6784 phba->sli4_hba.bmbx.avirt = PTR_ALIGN(dmabuf->virt,
6785 LPFC_ALIGN_16_BYTE);
6786 phba->sli4_hba.bmbx.aphys = ALIGN(dmabuf->phys,
6787 LPFC_ALIGN_16_BYTE);
6788
6789
6790
6791
6792
6793
6794
6795
6796
6797 dma_address = &phba->sli4_hba.bmbx.dma_address;
6798 phys_addr = (uint64_t)phba->sli4_hba.bmbx.aphys;
6799 pa_addr = (uint32_t) ((phys_addr >> 34) & 0x3fffffff);
6800 dma_address->addr_hi = (uint32_t) ((pa_addr << 2) |
6801 LPFC_BMBX_BIT1_ADDR_HI);
6802
6803 pa_addr = (uint32_t) ((phba->sli4_hba.bmbx.aphys >> 4) & 0x3fffffff);
6804 dma_address->addr_lo = (uint32_t) ((pa_addr << 2) |
6805 LPFC_BMBX_BIT1_ADDR_LO);
6806 return 0;
6807}
6808
6809
6810
6811
6812
6813
6814
6815
6816
6817
6818
6819
6820static void
6821lpfc_destroy_bootstrap_mbox(struct lpfc_hba *phba)
6822{
6823 dma_free_coherent(&phba->pcidev->dev,
6824 phba->sli4_hba.bmbx.bmbx_size,
6825 phba->sli4_hba.bmbx.dmabuf->virt,
6826 phba->sli4_hba.bmbx.dmabuf->phys);
6827
6828 kfree(phba->sli4_hba.bmbx.dmabuf);
6829 memset(&phba->sli4_hba.bmbx, 0, sizeof(struct lpfc_bmbx));
6830}
6831
6832
6833
6834
6835
6836
6837
6838
6839
6840
6841
6842
6843
6844
6845
6846int
6847lpfc_sli4_read_config(struct lpfc_hba *phba)
6848{
6849 LPFC_MBOXQ_t *pmb;
6850 struct lpfc_mbx_read_config *rd_config;
6851 union lpfc_sli4_cfg_shdr *shdr;
6852 uint32_t shdr_status, shdr_add_status;
6853 struct lpfc_mbx_get_func_cfg *get_func_cfg;
6854 struct lpfc_rsrc_desc_fcfcoe *desc;
6855 char *pdesc_0;
6856 int length, i, rc = 0, rc2;
6857
6858 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
6859 if (!pmb) {
6860 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6861 "2011 Unable to allocate memory for issuing "
6862 "SLI_CONFIG_SPECIAL mailbox command\n");
6863 return -ENOMEM;
6864 }
6865
6866 lpfc_read_config(phba, pmb);
6867
6868 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
6869 if (rc != MBX_SUCCESS) {
6870 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6871 "2012 Mailbox failed , mbxCmd x%x "
6872 "READ_CONFIG, mbxStatus x%x\n",
6873 bf_get(lpfc_mqe_command, &pmb->u.mqe),
6874 bf_get(lpfc_mqe_status, &pmb->u.mqe));
6875 rc = -EIO;
6876 } else {
6877 rd_config = &pmb->u.mqe.un.rd_config;
6878 if (bf_get(lpfc_mbx_rd_conf_lnk_ldv, rd_config)) {
6879 phba->sli4_hba.lnk_info.lnk_dv = LPFC_LNK_DAT_VAL;
6880 phba->sli4_hba.lnk_info.lnk_tp =
6881 bf_get(lpfc_mbx_rd_conf_lnk_type, rd_config);
6882 phba->sli4_hba.lnk_info.lnk_no =
6883 bf_get(lpfc_mbx_rd_conf_lnk_numb, rd_config);
6884 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6885 "3081 lnk_type:%d, lnk_numb:%d\n",
6886 phba->sli4_hba.lnk_info.lnk_tp,
6887 phba->sli4_hba.lnk_info.lnk_no);
6888 } else
6889 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
6890 "3082 Mailbox (x%x) returned ldv:x0\n",
6891 bf_get(lpfc_mqe_command, &pmb->u.mqe));
6892 phba->sli4_hba.extents_in_use =
6893 bf_get(lpfc_mbx_rd_conf_extnts_inuse, rd_config);
6894 phba->sli4_hba.max_cfg_param.max_xri =
6895 bf_get(lpfc_mbx_rd_conf_xri_count, rd_config);
6896 phba->sli4_hba.max_cfg_param.xri_base =
6897 bf_get(lpfc_mbx_rd_conf_xri_base, rd_config);
6898 phba->sli4_hba.max_cfg_param.max_vpi =
6899 bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config);
6900 phba->sli4_hba.max_cfg_param.vpi_base =
6901 bf_get(lpfc_mbx_rd_conf_vpi_base, rd_config);
6902 phba->sli4_hba.max_cfg_param.max_rpi =
6903 bf_get(lpfc_mbx_rd_conf_rpi_count, rd_config);
6904 phba->sli4_hba.max_cfg_param.rpi_base =
6905 bf_get(lpfc_mbx_rd_conf_rpi_base, rd_config);
6906 phba->sli4_hba.max_cfg_param.max_vfi =
6907 bf_get(lpfc_mbx_rd_conf_vfi_count, rd_config);
6908 phba->sli4_hba.max_cfg_param.vfi_base =
6909 bf_get(lpfc_mbx_rd_conf_vfi_base, rd_config);
6910 phba->sli4_hba.max_cfg_param.max_fcfi =
6911 bf_get(lpfc_mbx_rd_conf_fcfi_count, rd_config);
6912 phba->sli4_hba.max_cfg_param.max_eq =
6913 bf_get(lpfc_mbx_rd_conf_eq_count, rd_config);
6914 phba->sli4_hba.max_cfg_param.max_rq =
6915 bf_get(lpfc_mbx_rd_conf_rq_count, rd_config);
6916 phba->sli4_hba.max_cfg_param.max_wq =
6917 bf_get(lpfc_mbx_rd_conf_wq_count, rd_config);
6918 phba->sli4_hba.max_cfg_param.max_cq =
6919 bf_get(lpfc_mbx_rd_conf_cq_count, rd_config);
6920 phba->lmt = bf_get(lpfc_mbx_rd_conf_lmt, rd_config);
6921 phba->sli4_hba.next_xri = phba->sli4_hba.max_cfg_param.xri_base;
6922 phba->vpi_base = phba->sli4_hba.max_cfg_param.vpi_base;
6923 phba->vfi_base = phba->sli4_hba.max_cfg_param.vfi_base;
6924 phba->max_vpi = (phba->sli4_hba.max_cfg_param.max_vpi > 0) ?
6925 (phba->sli4_hba.max_cfg_param.max_vpi - 1) : 0;
6926 phba->max_vports = phba->max_vpi;
6927 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6928 "2003 cfg params Extents? %d "
6929 "XRI(B:%d M:%d), "
6930 "VPI(B:%d M:%d) "
6931 "VFI(B:%d M:%d) "
6932 "RPI(B:%d M:%d) "
6933 "FCFI(Count:%d)\n",
6934 phba->sli4_hba.extents_in_use,
6935 phba->sli4_hba.max_cfg_param.xri_base,
6936 phba->sli4_hba.max_cfg_param.max_xri,
6937 phba->sli4_hba.max_cfg_param.vpi_base,
6938 phba->sli4_hba.max_cfg_param.max_vpi,
6939 phba->sli4_hba.max_cfg_param.vfi_base,
6940 phba->sli4_hba.max_cfg_param.max_vfi,
6941 phba->sli4_hba.max_cfg_param.rpi_base,
6942 phba->sli4_hba.max_cfg_param.max_rpi,
6943 phba->sli4_hba.max_cfg_param.max_fcfi);
6944 }
6945
6946 if (rc)
6947 goto read_cfg_out;
6948
6949
6950 length = phba->sli4_hba.max_cfg_param.max_xri -
6951 lpfc_sli4_get_els_iocb_cnt(phba);
6952 if (phba->cfg_hba_queue_depth > length) {
6953 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6954 "3361 HBA queue depth changed from %d to %d\n",
6955 phba->cfg_hba_queue_depth, length);
6956 phba->cfg_hba_queue_depth = length;
6957 }
6958
6959 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
6960 LPFC_SLI_INTF_IF_TYPE_2)
6961 goto read_cfg_out;
6962
6963
6964 length = (sizeof(struct lpfc_mbx_get_func_cfg) -
6965 sizeof(struct lpfc_sli4_cfg_mhdr));
6966 lpfc_sli4_config(phba, pmb, LPFC_MBOX_SUBSYSTEM_COMMON,
6967 LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG,
6968 length, LPFC_SLI4_MBX_EMBED);
6969
6970 rc2 = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
6971 shdr = (union lpfc_sli4_cfg_shdr *)
6972 &pmb->u.mqe.un.sli4_config.header.cfg_shdr;
6973 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
6974 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
6975 if (rc2 || shdr_status || shdr_add_status) {
6976 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6977 "3026 Mailbox failed , mbxCmd x%x "
6978 "GET_FUNCTION_CONFIG, mbxStatus x%x\n",
6979 bf_get(lpfc_mqe_command, &pmb->u.mqe),
6980 bf_get(lpfc_mqe_status, &pmb->u.mqe));
6981 goto read_cfg_out;
6982 }
6983
6984
6985 get_func_cfg = &pmb->u.mqe.un.get_func_cfg;
6986
6987 pdesc_0 = (char *)&get_func_cfg->func_cfg.desc[0];
6988 desc = (struct lpfc_rsrc_desc_fcfcoe *)pdesc_0;
6989 length = bf_get(lpfc_rsrc_desc_fcfcoe_length, desc);
6990 if (length == LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD)
6991 length = LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH;
6992 else if (length != LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH)
6993 goto read_cfg_out;
6994
6995 for (i = 0; i < LPFC_RSRC_DESC_MAX_NUM; i++) {
6996 desc = (struct lpfc_rsrc_desc_fcfcoe *)(pdesc_0 + length * i);
6997 if (LPFC_RSRC_DESC_TYPE_FCFCOE ==
6998 bf_get(lpfc_rsrc_desc_fcfcoe_type, desc)) {
6999 phba->sli4_hba.iov.pf_number =
7000 bf_get(lpfc_rsrc_desc_fcfcoe_pfnum, desc);
7001 phba->sli4_hba.iov.vf_number =
7002 bf_get(lpfc_rsrc_desc_fcfcoe_vfnum, desc);
7003 break;
7004 }
7005 }
7006
7007 if (i < LPFC_RSRC_DESC_MAX_NUM)
7008 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
7009 "3027 GET_FUNCTION_CONFIG: pf_number:%d, "
7010 "vf_number:%d\n", phba->sli4_hba.iov.pf_number,
7011 phba->sli4_hba.iov.vf_number);
7012 else
7013 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
7014 "3028 GET_FUNCTION_CONFIG: failed to find "
7015 "Resrouce Descriptor:x%x\n",
7016 LPFC_RSRC_DESC_TYPE_FCFCOE);
7017
7018read_cfg_out:
7019 mempool_free(pmb, phba->mbox_mem_pool);
7020 return rc;
7021}
7022
7023
7024
7025
7026
7027
7028
7029
7030
7031
7032
7033
7034
7035
7036static int
7037lpfc_setup_endian_order(struct lpfc_hba *phba)
7038{
7039 LPFC_MBOXQ_t *mboxq;
7040 uint32_t if_type, rc = 0;
7041 uint32_t endian_mb_data[2] = {HOST_ENDIAN_LOW_WORD0,
7042 HOST_ENDIAN_HIGH_WORD1};
7043
7044 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
7045 switch (if_type) {
7046 case LPFC_SLI_INTF_IF_TYPE_0:
7047 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
7048 GFP_KERNEL);
7049 if (!mboxq) {
7050 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7051 "0492 Unable to allocate memory for "
7052 "issuing SLI_CONFIG_SPECIAL mailbox "
7053 "command\n");
7054 return -ENOMEM;
7055 }
7056
7057
7058
7059
7060
7061 memset(mboxq, 0, sizeof(LPFC_MBOXQ_t));
7062 memcpy(&mboxq->u.mqe, &endian_mb_data, sizeof(endian_mb_data));
7063 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
7064 if (rc != MBX_SUCCESS) {
7065 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7066 "0493 SLI_CONFIG_SPECIAL mailbox "
7067 "failed with status x%x\n",
7068 rc);
7069 rc = -EIO;
7070 }
7071 mempool_free(mboxq, phba->mbox_mem_pool);
7072 break;
7073 case LPFC_SLI_INTF_IF_TYPE_2:
7074 case LPFC_SLI_INTF_IF_TYPE_1:
7075 default:
7076 break;
7077 }
7078 return rc;
7079}
7080
7081
7082
7083
7084
7085
7086
7087
7088
7089
7090
7091
7092
7093
7094static int
7095lpfc_sli4_queue_verify(struct lpfc_hba *phba)
7096{
7097 int cfg_fcp_io_channel;
7098 uint32_t cpu;
7099 uint32_t i = 0;
7100 int fof_vectors = phba->cfg_fof ? 1 : 0;
7101
7102
7103
7104
7105
7106
7107
7108 cfg_fcp_io_channel = phba->cfg_fcp_io_channel;
7109
7110
7111 for_each_present_cpu(cpu) {
7112 if (cpu_online(cpu))
7113 i++;
7114 }
7115 phba->sli4_hba.num_online_cpu = i;
7116 phba->sli4_hba.num_present_cpu = lpfc_present_cpu;
7117 phba->sli4_hba.curr_disp_cpu = 0;
7118
7119 if (i < cfg_fcp_io_channel) {
7120 lpfc_printf_log(phba,
7121 KERN_ERR, LOG_INIT,
7122 "3188 Reducing IO channels to match number of "
7123 "online CPUs: from %d to %d\n",
7124 cfg_fcp_io_channel, i);
7125 cfg_fcp_io_channel = i;
7126 }
7127
7128 if (cfg_fcp_io_channel + fof_vectors >
7129 phba->sli4_hba.max_cfg_param.max_eq) {
7130 if (phba->sli4_hba.max_cfg_param.max_eq <
7131 LPFC_FCP_IO_CHAN_MIN) {
7132 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7133 "2574 Not enough EQs (%d) from the "
7134 "pci function for supporting FCP "
7135 "EQs (%d)\n",
7136 phba->sli4_hba.max_cfg_param.max_eq,
7137 phba->cfg_fcp_io_channel);
7138 goto out_error;
7139 }
7140 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7141 "2575 Reducing IO channels to match number of "
7142 "available EQs: from %d to %d\n",
7143 cfg_fcp_io_channel,
7144 phba->sli4_hba.max_cfg_param.max_eq);
7145 cfg_fcp_io_channel = phba->sli4_hba.max_cfg_param.max_eq -
7146 fof_vectors;
7147 }
7148
7149
7150 phba->cfg_fcp_io_channel = cfg_fcp_io_channel;
7151
7152
7153 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
7154 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
7155
7156
7157 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
7158 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
7159
7160 return 0;
7161out_error:
7162 return -ENOMEM;
7163}
7164
7165
7166
7167
7168
7169
7170
7171
7172
7173
7174
7175
7176
7177
7178
7179int
7180lpfc_sli4_queue_create(struct lpfc_hba *phba)
7181{
7182 struct lpfc_queue *qdesc;
7183 int idx;
7184
7185
7186
7187
7188 if (!phba->cfg_fcp_io_channel)
7189 return -ERANGE;
7190
7191 phba->sli4_hba.mq_esize = LPFC_MQE_SIZE;
7192 phba->sli4_hba.mq_ecount = LPFC_MQE_DEF_COUNT;
7193 phba->sli4_hba.wq_esize = LPFC_WQE_SIZE;
7194 phba->sli4_hba.wq_ecount = LPFC_WQE_DEF_COUNT;
7195 phba->sli4_hba.rq_esize = LPFC_RQE_SIZE;
7196 phba->sli4_hba.rq_ecount = LPFC_RQE_DEF_COUNT;
7197
7198 phba->sli4_hba.hba_eq = kzalloc((sizeof(struct lpfc_queue *) *
7199 phba->cfg_fcp_io_channel), GFP_KERNEL);
7200 if (!phba->sli4_hba.hba_eq) {
7201 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7202 "2576 Failed allocate memory for "
7203 "fast-path EQ record array\n");
7204 goto out_error;
7205 }
7206
7207 phba->sli4_hba.fcp_cq = kzalloc((sizeof(struct lpfc_queue *) *
7208 phba->cfg_fcp_io_channel), GFP_KERNEL);
7209 if (!phba->sli4_hba.fcp_cq) {
7210 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7211 "2577 Failed allocate memory for fast-path "
7212 "CQ record array\n");
7213 goto out_error;
7214 }
7215
7216 phba->sli4_hba.fcp_wq = kzalloc((sizeof(struct lpfc_queue *) *
7217 phba->cfg_fcp_io_channel), GFP_KERNEL);
7218 if (!phba->sli4_hba.fcp_wq) {
7219 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7220 "2578 Failed allocate memory for fast-path "
7221 "WQ record array\n");
7222 goto out_error;
7223 }
7224
7225
7226
7227
7228
7229
7230 phba->sli4_hba.fcp_cq_map = kzalloc((sizeof(uint16_t) *
7231 phba->cfg_fcp_io_channel), GFP_KERNEL);
7232 if (!phba->sli4_hba.fcp_cq_map) {
7233 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7234 "2545 Failed allocate memory for fast-path "
7235 "CQ map\n");
7236 goto out_error;
7237 }
7238
7239
7240
7241
7242
7243 for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++) {
7244
7245
7246 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.eq_esize,
7247 phba->sli4_hba.eq_ecount);
7248 if (!qdesc) {
7249 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7250 "0497 Failed allocate EQ (%d)\n", idx);
7251 goto out_error;
7252 }
7253 phba->sli4_hba.hba_eq[idx] = qdesc;
7254
7255
7256 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
7257 phba->sli4_hba.cq_ecount);
7258 if (!qdesc) {
7259 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7260 "0499 Failed allocate fast-path FCP "
7261 "CQ (%d)\n", idx);
7262 goto out_error;
7263 }
7264 phba->sli4_hba.fcp_cq[idx] = qdesc;
7265
7266
7267 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.wq_esize,
7268 phba->sli4_hba.wq_ecount);
7269 if (!qdesc) {
7270 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7271 "0503 Failed allocate fast-path FCP "
7272 "WQ (%d)\n", idx);
7273 goto out_error;
7274 }
7275 phba->sli4_hba.fcp_wq[idx] = qdesc;
7276 }
7277
7278
7279
7280
7281
7282
7283
7284 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
7285 phba->sli4_hba.cq_ecount);
7286 if (!qdesc) {
7287 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7288 "0500 Failed allocate slow-path mailbox CQ\n");
7289 goto out_error;
7290 }
7291 phba->sli4_hba.mbx_cq = qdesc;
7292
7293
7294 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
7295 phba->sli4_hba.cq_ecount);
7296 if (!qdesc) {
7297 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7298 "0501 Failed allocate slow-path ELS CQ\n");
7299 goto out_error;
7300 }
7301 phba->sli4_hba.els_cq = qdesc;
7302
7303
7304
7305
7306
7307
7308
7309
7310 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.mq_esize,
7311 phba->sli4_hba.mq_ecount);
7312 if (!qdesc) {
7313 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7314 "0505 Failed allocate slow-path MQ\n");
7315 goto out_error;
7316 }
7317 phba->sli4_hba.mbx_wq = qdesc;
7318
7319
7320
7321
7322
7323
7324 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.wq_esize,
7325 phba->sli4_hba.wq_ecount);
7326 if (!qdesc) {
7327 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7328 "0504 Failed allocate slow-path ELS WQ\n");
7329 goto out_error;
7330 }
7331 phba->sli4_hba.els_wq = qdesc;
7332
7333
7334
7335
7336
7337
7338 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.rq_esize,
7339 phba->sli4_hba.rq_ecount);
7340 if (!qdesc) {
7341 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7342 "0506 Failed allocate receive HRQ\n");
7343 goto out_error;
7344 }
7345 phba->sli4_hba.hdr_rq = qdesc;
7346
7347
7348 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.rq_esize,
7349 phba->sli4_hba.rq_ecount);
7350 if (!qdesc) {
7351 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7352 "0507 Failed allocate receive DRQ\n");
7353 goto out_error;
7354 }
7355 phba->sli4_hba.dat_rq = qdesc;
7356
7357
7358 if (phba->cfg_fof)
7359 lpfc_fof_queue_create(phba);
7360 return 0;
7361
7362out_error:
7363 lpfc_sli4_queue_destroy(phba);
7364 return -ENOMEM;
7365}
7366
7367
7368
7369
7370
7371
7372
7373
7374
7375
7376
7377
7378
7379void
7380lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
7381{
7382 int idx;
7383
7384 if (phba->cfg_fof)
7385 lpfc_fof_queue_destroy(phba);
7386
7387 if (phba->sli4_hba.hba_eq != NULL) {
7388
7389 for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++) {
7390 if (phba->sli4_hba.hba_eq[idx] != NULL) {
7391 lpfc_sli4_queue_free(
7392 phba->sli4_hba.hba_eq[idx]);
7393 phba->sli4_hba.hba_eq[idx] = NULL;
7394 }
7395 }
7396 kfree(phba->sli4_hba.hba_eq);
7397 phba->sli4_hba.hba_eq = NULL;
7398 }
7399
7400 if (phba->sli4_hba.fcp_cq != NULL) {
7401
7402 for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++) {
7403 if (phba->sli4_hba.fcp_cq[idx] != NULL) {
7404 lpfc_sli4_queue_free(
7405 phba->sli4_hba.fcp_cq[idx]);
7406 phba->sli4_hba.fcp_cq[idx] = NULL;
7407 }
7408 }
7409 kfree(phba->sli4_hba.fcp_cq);
7410 phba->sli4_hba.fcp_cq = NULL;
7411 }
7412
7413 if (phba->sli4_hba.fcp_wq != NULL) {
7414
7415 for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++) {
7416 if (phba->sli4_hba.fcp_wq[idx] != NULL) {
7417 lpfc_sli4_queue_free(
7418 phba->sli4_hba.fcp_wq[idx]);
7419 phba->sli4_hba.fcp_wq[idx] = NULL;
7420 }
7421 }
7422 kfree(phba->sli4_hba.fcp_wq);
7423 phba->sli4_hba.fcp_wq = NULL;
7424 }
7425
7426
7427 if (phba->sli4_hba.fcp_cq_map != NULL) {
7428 kfree(phba->sli4_hba.fcp_cq_map);
7429 phba->sli4_hba.fcp_cq_map = NULL;
7430 }
7431
7432
7433 if (phba->sli4_hba.mbx_wq != NULL) {
7434 lpfc_sli4_queue_free(phba->sli4_hba.mbx_wq);
7435 phba->sli4_hba.mbx_wq = NULL;
7436 }
7437
7438
7439 if (phba->sli4_hba.els_wq != NULL) {
7440 lpfc_sli4_queue_free(phba->sli4_hba.els_wq);
7441 phba->sli4_hba.els_wq = NULL;
7442 }
7443
7444
7445 if (phba->sli4_hba.hdr_rq != NULL) {
7446 lpfc_sli4_queue_free(phba->sli4_hba.hdr_rq);
7447 phba->sli4_hba.hdr_rq = NULL;
7448 }
7449 if (phba->sli4_hba.dat_rq != NULL) {
7450 lpfc_sli4_queue_free(phba->sli4_hba.dat_rq);
7451 phba->sli4_hba.dat_rq = NULL;
7452 }
7453
7454
7455 if (phba->sli4_hba.els_cq != NULL) {
7456 lpfc_sli4_queue_free(phba->sli4_hba.els_cq);
7457 phba->sli4_hba.els_cq = NULL;
7458 }
7459
7460
7461 if (phba->sli4_hba.mbx_cq != NULL) {
7462 lpfc_sli4_queue_free(phba->sli4_hba.mbx_cq);
7463 phba->sli4_hba.mbx_cq = NULL;
7464 }
7465
7466 return;
7467}
7468
7469
7470
7471
7472
7473
7474
7475
7476
7477
7478
7479
7480
7481int
7482lpfc_sli4_queue_setup(struct lpfc_hba *phba)
7483{
7484 struct lpfc_sli *psli = &phba->sli;
7485 struct lpfc_sli_ring *pring;
7486 int rc = -ENOMEM;
7487 int fcp_eqidx, fcp_cqidx, fcp_wqidx;
7488 int fcp_cq_index = 0;
7489 uint32_t shdr_status, shdr_add_status;
7490 union lpfc_sli4_cfg_shdr *shdr;
7491 LPFC_MBOXQ_t *mboxq;
7492 uint32_t length;
7493
7494
7495 mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
7496 if (!mboxq) {
7497 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7498 "3249 Unable to allocate memory for "
7499 "QUERY_FW_CFG mailbox command\n");
7500 return -ENOMEM;
7501 }
7502 length = (sizeof(struct lpfc_mbx_query_fw_config) -
7503 sizeof(struct lpfc_sli4_cfg_mhdr));
7504 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
7505 LPFC_MBOX_OPCODE_QUERY_FW_CFG,
7506 length, LPFC_SLI4_MBX_EMBED);
7507
7508 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
7509
7510 shdr = (union lpfc_sli4_cfg_shdr *)
7511 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
7512 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
7513 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
7514 if (shdr_status || shdr_add_status || rc) {
7515 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7516 "3250 QUERY_FW_CFG mailbox failed with status "
7517 "x%x add_status x%x, mbx status x%x\n",
7518 shdr_status, shdr_add_status, rc);
7519 if (rc != MBX_TIMEOUT)
7520 mempool_free(mboxq, phba->mbox_mem_pool);
7521 rc = -ENXIO;
7522 goto out_error;
7523 }
7524
7525 phba->sli4_hba.fw_func_mode =
7526 mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode;
7527 phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode;
7528 phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode;
7529 phba->sli4_hba.physical_port =
7530 mboxq->u.mqe.un.query_fw_cfg.rsp.physical_port;
7531 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7532 "3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, "
7533 "ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode,
7534 phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode);
7535
7536 if (rc != MBX_TIMEOUT)
7537 mempool_free(mboxq, phba->mbox_mem_pool);
7538
7539
7540
7541
7542
7543
7544 if (phba->cfg_fcp_io_channel && !phba->sli4_hba.hba_eq) {
7545 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7546 "3147 Fast-path EQs not allocated\n");
7547 rc = -ENOMEM;
7548 goto out_error;
7549 }
7550 for (fcp_eqidx = 0; fcp_eqidx < phba->cfg_fcp_io_channel; fcp_eqidx++) {
7551 if (!phba->sli4_hba.hba_eq[fcp_eqidx]) {
7552 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7553 "0522 Fast-path EQ (%d) not "
7554 "allocated\n", fcp_eqidx);
7555 rc = -ENOMEM;
7556 goto out_destroy_hba_eq;
7557 }
7558 rc = lpfc_eq_create(phba, phba->sli4_hba.hba_eq[fcp_eqidx],
7559 (phba->cfg_fcp_imax / phba->cfg_fcp_io_channel));
7560 if (rc) {
7561 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7562 "0523 Failed setup of fast-path EQ "
7563 "(%d), rc = 0x%x\n", fcp_eqidx,
7564 (uint32_t)rc);
7565 goto out_destroy_hba_eq;
7566 }
7567 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7568 "2584 HBA EQ setup: "
7569 "queue[%d]-id=%d\n", fcp_eqidx,
7570 phba->sli4_hba.hba_eq[fcp_eqidx]->queue_id);
7571 }
7572
7573
7574 if (!phba->sli4_hba.fcp_cq) {
7575 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7576 "3148 Fast-path FCP CQ array not "
7577 "allocated\n");
7578 rc = -ENOMEM;
7579 goto out_destroy_hba_eq;
7580 }
7581
7582 for (fcp_cqidx = 0; fcp_cqidx < phba->cfg_fcp_io_channel; fcp_cqidx++) {
7583 if (!phba->sli4_hba.fcp_cq[fcp_cqidx]) {
7584 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7585 "0526 Fast-path FCP CQ (%d) not "
7586 "allocated\n", fcp_cqidx);
7587 rc = -ENOMEM;
7588 goto out_destroy_fcp_cq;
7589 }
7590 rc = lpfc_cq_create(phba, phba->sli4_hba.fcp_cq[fcp_cqidx],
7591 phba->sli4_hba.hba_eq[fcp_cqidx], LPFC_WCQ, LPFC_FCP);
7592 if (rc) {
7593 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7594 "0527 Failed setup of fast-path FCP "
7595 "CQ (%d), rc = 0x%x\n", fcp_cqidx,
7596 (uint32_t)rc);
7597 goto out_destroy_fcp_cq;
7598 }
7599
7600
7601 phba->sli4_hba.fcp_cq_map[fcp_cqidx] =
7602 phba->sli4_hba.fcp_cq[fcp_cqidx]->queue_id;
7603
7604 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7605 "2588 FCP CQ setup: cq[%d]-id=%d, "
7606 "parent seq[%d]-id=%d\n",
7607 fcp_cqidx,
7608 phba->sli4_hba.fcp_cq[fcp_cqidx]->queue_id,
7609 fcp_cqidx,
7610 phba->sli4_hba.hba_eq[fcp_cqidx]->queue_id);
7611 }
7612
7613
7614 if (!phba->sli4_hba.fcp_wq) {
7615 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7616 "3149 Fast-path FCP WQ array not "
7617 "allocated\n");
7618 rc = -ENOMEM;
7619 goto out_destroy_fcp_cq;
7620 }
7621
7622 for (fcp_wqidx = 0; fcp_wqidx < phba->cfg_fcp_io_channel; fcp_wqidx++) {
7623 if (!phba->sli4_hba.fcp_wq[fcp_wqidx]) {
7624 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7625 "0534 Fast-path FCP WQ (%d) not "
7626 "allocated\n", fcp_wqidx);
7627 rc = -ENOMEM;
7628 goto out_destroy_fcp_wq;
7629 }
7630 rc = lpfc_wq_create(phba, phba->sli4_hba.fcp_wq[fcp_wqidx],
7631 phba->sli4_hba.fcp_cq[fcp_wqidx],
7632 LPFC_FCP);
7633 if (rc) {
7634 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7635 "0535 Failed setup of fast-path FCP "
7636 "WQ (%d), rc = 0x%x\n", fcp_wqidx,
7637 (uint32_t)rc);
7638 goto out_destroy_fcp_wq;
7639 }
7640
7641
7642 pring = &psli->ring[MAX_SLI3_CONFIGURED_RINGS + fcp_wqidx];
7643 pring->sli.sli4.wqp = (void *)phba->sli4_hba.fcp_wq[fcp_wqidx];
7644 phba->sli4_hba.fcp_cq[fcp_wqidx]->pring = pring;
7645
7646 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7647 "2591 FCP WQ setup: wq[%d]-id=%d, "
7648 "parent cq[%d]-id=%d\n",
7649 fcp_wqidx,
7650 phba->sli4_hba.fcp_wq[fcp_wqidx]->queue_id,
7651 fcp_cq_index,
7652 phba->sli4_hba.fcp_cq[fcp_wqidx]->queue_id);
7653 }
7654
7655
7656
7657
7658
7659 if (!phba->sli4_hba.mbx_cq) {
7660 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7661 "0528 Mailbox CQ not allocated\n");
7662 rc = -ENOMEM;
7663 goto out_destroy_fcp_wq;
7664 }
7665 rc = lpfc_cq_create(phba, phba->sli4_hba.mbx_cq,
7666 phba->sli4_hba.hba_eq[0], LPFC_MCQ, LPFC_MBOX);
7667 if (rc) {
7668 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7669 "0529 Failed setup of slow-path mailbox CQ: "
7670 "rc = 0x%x\n", (uint32_t)rc);
7671 goto out_destroy_fcp_wq;
7672 }
7673 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7674 "2585 MBX CQ setup: cq-id=%d, parent eq-id=%d\n",
7675 phba->sli4_hba.mbx_cq->queue_id,
7676 phba->sli4_hba.hba_eq[0]->queue_id);
7677
7678
7679 if (!phba->sli4_hba.els_cq) {
7680 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7681 "0530 ELS CQ not allocated\n");
7682 rc = -ENOMEM;
7683 goto out_destroy_mbx_cq;
7684 }
7685 rc = lpfc_cq_create(phba, phba->sli4_hba.els_cq,
7686 phba->sli4_hba.hba_eq[0], LPFC_WCQ, LPFC_ELS);
7687 if (rc) {
7688 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7689 "0531 Failed setup of slow-path ELS CQ: "
7690 "rc = 0x%x\n", (uint32_t)rc);
7691 goto out_destroy_mbx_cq;
7692 }
7693 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7694 "2586 ELS CQ setup: cq-id=%d, parent eq-id=%d\n",
7695 phba->sli4_hba.els_cq->queue_id,
7696 phba->sli4_hba.hba_eq[0]->queue_id);
7697
7698
7699
7700
7701
7702
7703 if (!phba->sli4_hba.mbx_wq) {
7704 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7705 "0538 Slow-path MQ not allocated\n");
7706 rc = -ENOMEM;
7707 goto out_destroy_els_cq;
7708 }
7709 rc = lpfc_mq_create(phba, phba->sli4_hba.mbx_wq,
7710 phba->sli4_hba.mbx_cq, LPFC_MBOX);
7711 if (rc) {
7712 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7713 "0539 Failed setup of slow-path MQ: "
7714 "rc = 0x%x\n", rc);
7715 goto out_destroy_els_cq;
7716 }
7717 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7718 "2589 MBX MQ setup: wq-id=%d, parent cq-id=%d\n",
7719 phba->sli4_hba.mbx_wq->queue_id,
7720 phba->sli4_hba.mbx_cq->queue_id);
7721
7722
7723 if (!phba->sli4_hba.els_wq) {
7724 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7725 "0536 Slow-path ELS WQ not allocated\n");
7726 rc = -ENOMEM;
7727 goto out_destroy_mbx_wq;
7728 }
7729 rc = lpfc_wq_create(phba, phba->sli4_hba.els_wq,
7730 phba->sli4_hba.els_cq, LPFC_ELS);
7731 if (rc) {
7732 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7733 "0537 Failed setup of slow-path ELS WQ: "
7734 "rc = 0x%x\n", (uint32_t)rc);
7735 goto out_destroy_mbx_wq;
7736 }
7737
7738
7739 pring = &psli->ring[LPFC_ELS_RING];
7740 pring->sli.sli4.wqp = (void *)phba->sli4_hba.els_wq;
7741 phba->sli4_hba.els_cq->pring = pring;
7742
7743 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7744 "2590 ELS WQ setup: wq-id=%d, parent cq-id=%d\n",
7745 phba->sli4_hba.els_wq->queue_id,
7746 phba->sli4_hba.els_cq->queue_id);
7747
7748
7749
7750
7751 if (!phba->sli4_hba.hdr_rq || !phba->sli4_hba.dat_rq) {
7752 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7753 "0540 Receive Queue not allocated\n");
7754 rc = -ENOMEM;
7755 goto out_destroy_els_wq;
7756 }
7757
7758 lpfc_rq_adjust_repost(phba, phba->sli4_hba.hdr_rq, LPFC_ELS_HBQ);
7759 lpfc_rq_adjust_repost(phba, phba->sli4_hba.dat_rq, LPFC_ELS_HBQ);
7760
7761 rc = lpfc_rq_create(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq,
7762 phba->sli4_hba.els_cq, LPFC_USOL);
7763 if (rc) {
7764 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7765 "0541 Failed setup of Receive Queue: "
7766 "rc = 0x%x\n", (uint32_t)rc);
7767 goto out_destroy_fcp_wq;
7768 }
7769
7770 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7771 "2592 USL RQ setup: hdr-rq-id=%d, dat-rq-id=%d "
7772 "parent cq-id=%d\n",
7773 phba->sli4_hba.hdr_rq->queue_id,
7774 phba->sli4_hba.dat_rq->queue_id,
7775 phba->sli4_hba.els_cq->queue_id);
7776
7777 if (phba->cfg_fof) {
7778 rc = lpfc_fof_queue_setup(phba);
7779 if (rc) {
7780 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7781 "0549 Failed setup of FOF Queues: "
7782 "rc = 0x%x\n", rc);
7783 goto out_destroy_els_rq;
7784 }
7785 }
7786
7787
7788
7789
7790
7791 for (fcp_eqidx = 0; fcp_eqidx < phba->cfg_fcp_io_channel;
7792 fcp_eqidx += LPFC_MAX_EQ_DELAY)
7793 lpfc_modify_fcp_eq_delay(phba, fcp_eqidx);
7794 return 0;
7795
7796out_destroy_els_rq:
7797 lpfc_rq_destroy(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq);
7798out_destroy_els_wq:
7799 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
7800out_destroy_mbx_wq:
7801 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
7802out_destroy_els_cq:
7803 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
7804out_destroy_mbx_cq:
7805 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
7806out_destroy_fcp_wq:
7807 for (--fcp_wqidx; fcp_wqidx >= 0; fcp_wqidx--)
7808 lpfc_wq_destroy(phba, phba->sli4_hba.fcp_wq[fcp_wqidx]);
7809out_destroy_fcp_cq:
7810 for (--fcp_cqidx; fcp_cqidx >= 0; fcp_cqidx--)
7811 lpfc_cq_destroy(phba, phba->sli4_hba.fcp_cq[fcp_cqidx]);
7812out_destroy_hba_eq:
7813 for (--fcp_eqidx; fcp_eqidx >= 0; fcp_eqidx--)
7814 lpfc_eq_destroy(phba, phba->sli4_hba.hba_eq[fcp_eqidx]);
7815out_error:
7816 return rc;
7817}
7818
7819
7820
7821
7822
7823
7824
7825
7826
7827
7828
7829
7830
7831void
7832lpfc_sli4_queue_unset(struct lpfc_hba *phba)
7833{
7834 int fcp_qidx;
7835
7836
7837 if (phba->cfg_fof)
7838 lpfc_fof_queue_destroy(phba);
7839
7840 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
7841
7842 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
7843
7844 lpfc_rq_destroy(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq);
7845
7846 if (phba->sli4_hba.fcp_wq) {
7847 for (fcp_qidx = 0; fcp_qidx < phba->cfg_fcp_io_channel;
7848 fcp_qidx++)
7849 lpfc_wq_destroy(phba, phba->sli4_hba.fcp_wq[fcp_qidx]);
7850 }
7851
7852 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
7853
7854 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
7855
7856 if (phba->sli4_hba.fcp_cq) {
7857 for (fcp_qidx = 0; fcp_qidx < phba->cfg_fcp_io_channel;
7858 fcp_qidx++)
7859 lpfc_cq_destroy(phba, phba->sli4_hba.fcp_cq[fcp_qidx]);
7860 }
7861
7862 if (phba->sli4_hba.hba_eq) {
7863 for (fcp_qidx = 0; fcp_qidx < phba->cfg_fcp_io_channel;
7864 fcp_qidx++)
7865 lpfc_eq_destroy(phba, phba->sli4_hba.hba_eq[fcp_qidx]);
7866 }
7867}
7868
7869
7870
7871
7872
7873
7874
7875
7876
7877
7878
7879
7880
7881
7882
7883
7884
7885static int
7886lpfc_sli4_cq_event_pool_create(struct lpfc_hba *phba)
7887{
7888 struct lpfc_cq_event *cq_event;
7889 int i;
7890
7891 for (i = 0; i < (4 * phba->sli4_hba.cq_ecount); i++) {
7892 cq_event = kmalloc(sizeof(struct lpfc_cq_event), GFP_KERNEL);
7893 if (!cq_event)
7894 goto out_pool_create_fail;
7895 list_add_tail(&cq_event->list,
7896 &phba->sli4_hba.sp_cqe_event_pool);
7897 }
7898 return 0;
7899
7900out_pool_create_fail:
7901 lpfc_sli4_cq_event_pool_destroy(phba);
7902 return -ENOMEM;
7903}
7904
7905
7906
7907
7908
7909
7910
7911
7912
7913
7914
7915static void
7916lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *phba)
7917{
7918 struct lpfc_cq_event *cq_event, *next_cq_event;
7919
7920 list_for_each_entry_safe(cq_event, next_cq_event,
7921 &phba->sli4_hba.sp_cqe_event_pool, list) {
7922 list_del(&cq_event->list);
7923 kfree(cq_event);
7924 }
7925}
7926
7927
7928
7929
7930
7931
7932
7933
7934
7935
7936
7937struct lpfc_cq_event *
7938__lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
7939{
7940 struct lpfc_cq_event *cq_event = NULL;
7941
7942 list_remove_head(&phba->sli4_hba.sp_cqe_event_pool, cq_event,
7943 struct lpfc_cq_event, list);
7944 return cq_event;
7945}
7946
7947
7948
7949
7950
7951
7952
7953
7954
7955
7956
7957struct lpfc_cq_event *
7958lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
7959{
7960 struct lpfc_cq_event *cq_event;
7961 unsigned long iflags;
7962
7963 spin_lock_irqsave(&phba->hbalock, iflags);
7964 cq_event = __lpfc_sli4_cq_event_alloc(phba);
7965 spin_unlock_irqrestore(&phba->hbalock, iflags);
7966 return cq_event;
7967}
7968
7969
7970
7971
7972
7973
7974
7975
7976
7977void
7978__lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
7979 struct lpfc_cq_event *cq_event)
7980{
7981 list_add_tail(&cq_event->list, &phba->sli4_hba.sp_cqe_event_pool);
7982}
7983
7984
7985
7986
7987
7988
7989
7990
7991
7992void
7993lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
7994 struct lpfc_cq_event *cq_event)
7995{
7996 unsigned long iflags;
7997 spin_lock_irqsave(&phba->hbalock, iflags);
7998 __lpfc_sli4_cq_event_release(phba, cq_event);
7999 spin_unlock_irqrestore(&phba->hbalock, iflags);
8000}
8001
8002
8003
8004
8005
8006
8007
8008
8009static void
8010lpfc_sli4_cq_event_release_all(struct lpfc_hba *phba)
8011{
8012 LIST_HEAD(cqelist);
8013 struct lpfc_cq_event *cqe;
8014 unsigned long iflags;
8015
8016
8017 spin_lock_irqsave(&phba->hbalock, iflags);
8018
8019 list_splice_init(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue,
8020 &cqelist);
8021
8022 list_splice_init(&phba->sli4_hba.sp_els_xri_aborted_work_queue,
8023 &cqelist);
8024
8025 list_splice_init(&phba->sli4_hba.sp_asynce_work_queue,
8026 &cqelist);
8027 spin_unlock_irqrestore(&phba->hbalock, iflags);
8028
8029 while (!list_empty(&cqelist)) {
8030 list_remove_head(&cqelist, cqe, struct lpfc_cq_event, list);
8031 lpfc_sli4_cq_event_release(phba, cqe);
8032 }
8033}
8034
8035
8036
8037
8038
8039
8040
8041
8042
8043
8044
8045
8046
8047int
8048lpfc_pci_function_reset(struct lpfc_hba *phba)
8049{
8050 LPFC_MBOXQ_t *mboxq;
8051 uint32_t rc = 0, if_type;
8052 uint32_t shdr_status, shdr_add_status;
8053 uint32_t rdy_chk;
8054 uint32_t port_reset = 0;
8055 union lpfc_sli4_cfg_shdr *shdr;
8056 struct lpfc_register reg_data;
8057 uint16_t devid;
8058
8059 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
8060 switch (if_type) {
8061 case LPFC_SLI_INTF_IF_TYPE_0:
8062 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
8063 GFP_KERNEL);
8064 if (!mboxq) {
8065 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8066 "0494 Unable to allocate memory for "
8067 "issuing SLI_FUNCTION_RESET mailbox "
8068 "command\n");
8069 return -ENOMEM;
8070 }
8071
8072
8073 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
8074 LPFC_MBOX_OPCODE_FUNCTION_RESET, 0,
8075 LPFC_SLI4_MBX_EMBED);
8076 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
8077 shdr = (union lpfc_sli4_cfg_shdr *)
8078 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
8079 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
8080 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status,
8081 &shdr->response);
8082 if (rc != MBX_TIMEOUT)
8083 mempool_free(mboxq, phba->mbox_mem_pool);
8084 if (shdr_status || shdr_add_status || rc) {
8085 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8086 "0495 SLI_FUNCTION_RESET mailbox "
8087 "failed with status x%x add_status x%x,"
8088 " mbx status x%x\n",
8089 shdr_status, shdr_add_status, rc);
8090 rc = -ENXIO;
8091 }
8092 break;
8093 case LPFC_SLI_INTF_IF_TYPE_2:
8094wait:
8095
8096
8097
8098
8099
8100 for (rdy_chk = 0; rdy_chk < 1500; rdy_chk++) {
8101 if (lpfc_readl(phba->sli4_hba.u.if_type2.
8102 STATUSregaddr, ®_data.word0)) {
8103 rc = -ENODEV;
8104 goto out;
8105 }
8106 if (bf_get(lpfc_sliport_status_rdy, ®_data))
8107 break;
8108 msleep(20);
8109 }
8110
8111 if (!bf_get(lpfc_sliport_status_rdy, ®_data)) {
8112 phba->work_status[0] = readl(
8113 phba->sli4_hba.u.if_type2.ERR1regaddr);
8114 phba->work_status[1] = readl(
8115 phba->sli4_hba.u.if_type2.ERR2regaddr);
8116 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8117 "2890 Port not ready, port status reg "
8118 "0x%x error 1=0x%x, error 2=0x%x\n",
8119 reg_data.word0,
8120 phba->work_status[0],
8121 phba->work_status[1]);
8122 rc = -ENODEV;
8123 goto out;
8124 }
8125
8126 if (!port_reset) {
8127
8128
8129
8130 reg_data.word0 = 0;
8131 bf_set(lpfc_sliport_ctrl_end, ®_data,
8132 LPFC_SLIPORT_LITTLE_ENDIAN);
8133 bf_set(lpfc_sliport_ctrl_ip, ®_data,
8134 LPFC_SLIPORT_INIT_PORT);
8135 writel(reg_data.word0, phba->sli4_hba.u.if_type2.
8136 CTRLregaddr);
8137
8138 pci_read_config_word(phba->pcidev,
8139 PCI_DEVICE_ID, &devid);
8140
8141 port_reset = 1;
8142 msleep(20);
8143 goto wait;
8144 } else if (bf_get(lpfc_sliport_status_rn, ®_data)) {
8145 rc = -ENODEV;
8146 goto out;
8147 }
8148 break;
8149
8150 case LPFC_SLI_INTF_IF_TYPE_1:
8151 default:
8152 break;
8153 }
8154
8155out:
8156
8157 if (rc) {
8158 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8159 "3317 HBA not functional: IP Reset Failed "
8160 "try: echo fw_reset > board_mode\n");
8161 rc = -ENODEV;
8162 }
8163
8164 return rc;
8165}
8166
8167
8168
8169
8170
8171
8172
8173
8174
8175
8176
8177
8178static int
8179lpfc_sli4_pci_mem_setup(struct lpfc_hba *phba)
8180{
8181 struct pci_dev *pdev;
8182 unsigned long bar0map_len, bar1map_len, bar2map_len;
8183 int error = -ENODEV;
8184 uint32_t if_type;
8185
8186
8187 if (!phba->pcidev)
8188 return error;
8189 else
8190 pdev = phba->pcidev;
8191
8192
8193 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0
8194 || pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(64)) != 0) {
8195 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0
8196 || pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(32)) != 0) {
8197 return error;
8198 }
8199 }
8200
8201
8202
8203
8204
8205 if (pci_read_config_dword(pdev, LPFC_SLI_INTF,
8206 &phba->sli4_hba.sli_intf.word0)) {
8207 return error;
8208 }
8209
8210
8211 if (bf_get(lpfc_sli_intf_valid, &phba->sli4_hba.sli_intf) !=
8212 LPFC_SLI_INTF_VALID) {
8213 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8214 "2894 SLI_INTF reg contents invalid "
8215 "sli_intf reg 0x%x\n",
8216 phba->sli4_hba.sli_intf.word0);
8217 return error;
8218 }
8219
8220 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
8221
8222
8223
8224
8225
8226
8227 if (pci_resource_start(pdev, PCI_64BIT_BAR0)) {
8228 phba->pci_bar0_map = pci_resource_start(pdev, PCI_64BIT_BAR0);
8229 bar0map_len = pci_resource_len(pdev, PCI_64BIT_BAR0);
8230
8231
8232
8233
8234
8235 phba->sli4_hba.conf_regs_memmap_p =
8236 ioremap(phba->pci_bar0_map, bar0map_len);
8237 if (!phba->sli4_hba.conf_regs_memmap_p) {
8238 dev_printk(KERN_ERR, &pdev->dev,
8239 "ioremap failed for SLI4 PCI config "
8240 "registers.\n");
8241 goto out;
8242 }
8243 phba->pci_bar0_memmap_p = phba->sli4_hba.conf_regs_memmap_p;
8244
8245 lpfc_sli4_bar0_register_memmap(phba, if_type);
8246 } else {
8247 phba->pci_bar0_map = pci_resource_start(pdev, 1);
8248 bar0map_len = pci_resource_len(pdev, 1);
8249 if (if_type == LPFC_SLI_INTF_IF_TYPE_2) {
8250 dev_printk(KERN_ERR, &pdev->dev,
8251 "FATAL - No BAR0 mapping for SLI4, if_type 2\n");
8252 goto out;
8253 }
8254 phba->sli4_hba.conf_regs_memmap_p =
8255 ioremap(phba->pci_bar0_map, bar0map_len);
8256 if (!phba->sli4_hba.conf_regs_memmap_p) {
8257 dev_printk(KERN_ERR, &pdev->dev,
8258 "ioremap failed for SLI4 PCI config "
8259 "registers.\n");
8260 goto out;
8261 }
8262 lpfc_sli4_bar0_register_memmap(phba, if_type);
8263 }
8264
8265 if ((if_type == LPFC_SLI_INTF_IF_TYPE_0) &&
8266 (pci_resource_start(pdev, PCI_64BIT_BAR2))) {
8267
8268
8269
8270
8271 phba->pci_bar1_map = pci_resource_start(pdev, PCI_64BIT_BAR2);
8272 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
8273 phba->sli4_hba.ctrl_regs_memmap_p =
8274 ioremap(phba->pci_bar1_map, bar1map_len);
8275 if (!phba->sli4_hba.ctrl_regs_memmap_p) {
8276 dev_printk(KERN_ERR, &pdev->dev,
8277 "ioremap failed for SLI4 HBA control registers.\n");
8278 goto out_iounmap_conf;
8279 }
8280 phba->pci_bar2_memmap_p = phba->sli4_hba.ctrl_regs_memmap_p;
8281 lpfc_sli4_bar1_register_memmap(phba);
8282 }
8283
8284 if ((if_type == LPFC_SLI_INTF_IF_TYPE_0) &&
8285 (pci_resource_start(pdev, PCI_64BIT_BAR4))) {
8286
8287
8288
8289
8290 phba->pci_bar2_map = pci_resource_start(pdev, PCI_64BIT_BAR4);
8291 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
8292 phba->sli4_hba.drbl_regs_memmap_p =
8293 ioremap(phba->pci_bar2_map, bar2map_len);
8294 if (!phba->sli4_hba.drbl_regs_memmap_p) {
8295 dev_printk(KERN_ERR, &pdev->dev,
8296 "ioremap failed for SLI4 HBA doorbell registers.\n");
8297 goto out_iounmap_ctrl;
8298 }
8299 phba->pci_bar4_memmap_p = phba->sli4_hba.drbl_regs_memmap_p;
8300 error = lpfc_sli4_bar2_register_memmap(phba, LPFC_VF0);
8301 if (error)
8302 goto out_iounmap_all;
8303 }
8304
8305 return 0;
8306
8307out_iounmap_all:
8308 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
8309out_iounmap_ctrl:
8310 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
8311out_iounmap_conf:
8312 iounmap(phba->sli4_hba.conf_regs_memmap_p);
8313out:
8314 return error;
8315}
8316
8317
8318
8319
8320
8321
8322
8323
8324static void
8325lpfc_sli4_pci_mem_unset(struct lpfc_hba *phba)
8326{
8327 uint32_t if_type;
8328 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
8329
8330 switch (if_type) {
8331 case LPFC_SLI_INTF_IF_TYPE_0:
8332 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
8333 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
8334 iounmap(phba->sli4_hba.conf_regs_memmap_p);
8335 break;
8336 case LPFC_SLI_INTF_IF_TYPE_2:
8337 iounmap(phba->sli4_hba.conf_regs_memmap_p);
8338 break;
8339 case LPFC_SLI_INTF_IF_TYPE_1:
8340 default:
8341 dev_printk(KERN_ERR, &phba->pcidev->dev,
8342 "FATAL - unsupported SLI4 interface type - %d\n",
8343 if_type);
8344 break;
8345 }
8346}
8347
8348
8349
8350
8351
8352
8353
8354
8355
8356
8357
8358
8359
8360
8361
8362
8363
8364
8365
8366
8367
8368static int
8369lpfc_sli_enable_msix(struct lpfc_hba *phba)
8370{
8371 int rc, i;
8372 LPFC_MBOXQ_t *pmb;
8373
8374
8375 for (i = 0; i < LPFC_MSIX_VECTORS; i++)
8376 phba->msix_entries[i].entry = i;
8377
8378
8379 rc = pci_enable_msix_exact(phba->pcidev, phba->msix_entries,
8380 LPFC_MSIX_VECTORS);
8381 if (rc) {
8382 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8383 "0420 PCI enable MSI-X failed (%d)\n", rc);
8384 goto vec_fail_out;
8385 }
8386 for (i = 0; i < LPFC_MSIX_VECTORS; i++)
8387 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8388 "0477 MSI-X entry[%d]: vector=x%x "
8389 "message=%d\n", i,
8390 phba->msix_entries[i].vector,
8391 phba->msix_entries[i].entry);
8392
8393
8394
8395
8396
8397 rc = request_irq(phba->msix_entries[0].vector,
8398 &lpfc_sli_sp_intr_handler, 0,
8399 LPFC_SP_DRIVER_HANDLER_NAME, phba);
8400 if (rc) {
8401 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8402 "0421 MSI-X slow-path request_irq failed "
8403 "(%d)\n", rc);
8404 goto msi_fail_out;
8405 }
8406
8407
8408 rc = request_irq(phba->msix_entries[1].vector,
8409 &lpfc_sli_fp_intr_handler, 0,
8410 LPFC_FP_DRIVER_HANDLER_NAME, phba);
8411
8412 if (rc) {
8413 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8414 "0429 MSI-X fast-path request_irq failed "
8415 "(%d)\n", rc);
8416 goto irq_fail_out;
8417 }
8418
8419
8420
8421
8422 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
8423
8424 if (!pmb) {
8425 rc = -ENOMEM;
8426 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8427 "0474 Unable to allocate memory for issuing "
8428 "MBOX_CONFIG_MSI command\n");
8429 goto mem_fail_out;
8430 }
8431 rc = lpfc_config_msi(phba, pmb);
8432 if (rc)
8433 goto mbx_fail_out;
8434 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
8435 if (rc != MBX_SUCCESS) {
8436 lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX,
8437 "0351 Config MSI mailbox command failed, "
8438 "mbxCmd x%x, mbxStatus x%x\n",
8439 pmb->u.mb.mbxCommand, pmb->u.mb.mbxStatus);
8440 goto mbx_fail_out;
8441 }
8442
8443
8444 mempool_free(pmb, phba->mbox_mem_pool);
8445 return rc;
8446
8447mbx_fail_out:
8448
8449 mempool_free(pmb, phba->mbox_mem_pool);
8450
8451mem_fail_out:
8452
8453 free_irq(phba->msix_entries[1].vector, phba);
8454
8455irq_fail_out:
8456
8457 free_irq(phba->msix_entries[0].vector, phba);
8458
8459msi_fail_out:
8460
8461 pci_disable_msix(phba->pcidev);
8462
8463vec_fail_out:
8464 return rc;
8465}
8466
8467
8468
8469
8470
8471
8472
8473
8474static void
8475lpfc_sli_disable_msix(struct lpfc_hba *phba)
8476{
8477 int i;
8478
8479
8480 for (i = 0; i < LPFC_MSIX_VECTORS; i++)
8481 free_irq(phba->msix_entries[i].vector, phba);
8482
8483 pci_disable_msix(phba->pcidev);
8484
8485 return;
8486}
8487
8488
8489
8490
8491
8492
8493
8494
8495
8496
8497
8498
8499
8500
8501
8502static int
8503lpfc_sli_enable_msi(struct lpfc_hba *phba)
8504{
8505 int rc;
8506
8507 rc = pci_enable_msi(phba->pcidev);
8508 if (!rc)
8509 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8510 "0462 PCI enable MSI mode success.\n");
8511 else {
8512 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8513 "0471 PCI enable MSI mode failed (%d)\n", rc);
8514 return rc;
8515 }
8516
8517 rc = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
8518 0, LPFC_DRIVER_NAME, phba);
8519 if (rc) {
8520 pci_disable_msi(phba->pcidev);
8521 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8522 "0478 MSI request_irq failed (%d)\n", rc);
8523 }
8524 return rc;
8525}
8526
8527
8528
8529
8530
8531
8532
8533
8534
8535
8536
8537static void
8538lpfc_sli_disable_msi(struct lpfc_hba *phba)
8539{
8540 free_irq(phba->pcidev->irq, phba);
8541 pci_disable_msi(phba->pcidev);
8542 return;
8543}
8544
8545
8546
8547
8548
8549
8550
8551
8552
8553
8554
8555
8556
8557
8558
8559
8560
8561static uint32_t
8562lpfc_sli_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
8563{
8564 uint32_t intr_mode = LPFC_INTR_ERROR;
8565 int retval;
8566
8567 if (cfg_mode == 2) {
8568
8569 retval = lpfc_sli_config_port(phba, LPFC_SLI_REV3);
8570 if (!retval) {
8571
8572 retval = lpfc_sli_enable_msix(phba);
8573 if (!retval) {
8574
8575 phba->intr_type = MSIX;
8576 intr_mode = 2;
8577 }
8578 }
8579 }
8580
8581
8582 if (cfg_mode >= 1 && phba->intr_type == NONE) {
8583 retval = lpfc_sli_enable_msi(phba);
8584 if (!retval) {
8585
8586 phba->intr_type = MSI;
8587 intr_mode = 1;
8588 }
8589 }
8590
8591
8592 if (phba->intr_type == NONE) {
8593 retval = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
8594 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
8595 if (!retval) {
8596
8597 phba->intr_type = INTx;
8598 intr_mode = 0;
8599 }
8600 }
8601 return intr_mode;
8602}
8603
8604
8605
8606
8607
8608
8609
8610
8611
8612
8613static void
8614lpfc_sli_disable_intr(struct lpfc_hba *phba)
8615{
8616
8617 if (phba->intr_type == MSIX)
8618 lpfc_sli_disable_msix(phba);
8619 else if (phba->intr_type == MSI)
8620 lpfc_sli_disable_msi(phba);
8621 else if (phba->intr_type == INTx)
8622 free_irq(phba->pcidev->irq, phba);
8623
8624
8625 phba->intr_type = NONE;
8626 phba->sli.slistat.sli_intr = 0;
8627
8628 return;
8629}
8630
8631
8632
8633
8634
8635
8636
8637static int
8638lpfc_find_next_cpu(struct lpfc_hba *phba, uint32_t phys_id)
8639{
8640 struct lpfc_vector_map_info *cpup;
8641 int cpu;
8642
8643 cpup = phba->sli4_hba.cpu_map;
8644 for (cpu = 0; cpu < phba->sli4_hba.num_present_cpu; cpu++) {
8645
8646 if (cpu_online(cpu)) {
8647 if ((cpup->irq == LPFC_VECTOR_MAP_EMPTY) &&
8648 (lpfc_used_cpu[cpu] == LPFC_VECTOR_MAP_EMPTY) &&
8649 (cpup->phys_id == phys_id)) {
8650 return cpu;
8651 }
8652 }
8653 cpup++;
8654 }
8655
8656
8657
8658
8659
8660
8661
8662 for (cpu = 0; cpu < phba->sli4_hba.num_present_cpu; cpu++) {
8663 if (lpfc_used_cpu[cpu] == phys_id)
8664 lpfc_used_cpu[cpu] = LPFC_VECTOR_MAP_EMPTY;
8665 }
8666
8667 cpup = phba->sli4_hba.cpu_map;
8668 for (cpu = 0; cpu < phba->sli4_hba.num_present_cpu; cpu++) {
8669
8670 if (cpu_online(cpu)) {
8671 if ((cpup->irq == LPFC_VECTOR_MAP_EMPTY) &&
8672 (cpup->phys_id == phys_id)) {
8673 return cpu;
8674 }
8675 }
8676 cpup++;
8677 }
8678 return LPFC_VECTOR_MAP_EMPTY;
8679}
8680
8681
8682
8683
8684
8685
8686
8687
8688
8689
8690
8691static int
8692lpfc_sli4_set_affinity(struct lpfc_hba *phba, int vectors)
8693{
8694 int i, idx, saved_chann, used_chann, cpu, phys_id;
8695 int max_phys_id, min_phys_id;
8696 int num_io_channel, first_cpu, chan;
8697 struct lpfc_vector_map_info *cpup;
8698#ifdef CONFIG_X86
8699 struct cpuinfo_x86 *cpuinfo;
8700#endif
8701 uint8_t chann[LPFC_FCP_IO_CHAN_MAX+1];
8702
8703
8704 if (!phba->cfg_fcp_cpu_map)
8705 return 1;
8706
8707
8708 memset(phba->sli4_hba.cpu_map, 0xff,
8709 (sizeof(struct lpfc_vector_map_info) *
8710 phba->sli4_hba.num_present_cpu));
8711
8712 max_phys_id = 0;
8713 min_phys_id = 0xff;
8714 phys_id = 0;
8715 num_io_channel = 0;
8716 first_cpu = LPFC_VECTOR_MAP_EMPTY;
8717
8718
8719 cpup = phba->sli4_hba.cpu_map;
8720 for (cpu = 0; cpu < phba->sli4_hba.num_present_cpu; cpu++) {
8721#ifdef CONFIG_X86
8722 cpuinfo = &cpu_data(cpu);
8723 cpup->phys_id = cpuinfo->phys_proc_id;
8724 cpup->core_id = cpuinfo->cpu_core_id;
8725#else
8726
8727 cpup->phys_id = 0;
8728 cpup->core_id = 0;
8729#endif
8730
8731 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8732 "3328 CPU physid %d coreid %d\n",
8733 cpup->phys_id, cpup->core_id);
8734
8735 if (cpup->phys_id > max_phys_id)
8736 max_phys_id = cpup->phys_id;
8737 if (cpup->phys_id < min_phys_id)
8738 min_phys_id = cpup->phys_id;
8739 cpup++;
8740 }
8741
8742 phys_id = min_phys_id;
8743
8744 for (idx = 0; idx < vectors; idx++) {
8745 cpup = phba->sli4_hba.cpu_map;
8746 cpu = lpfc_find_next_cpu(phba, phys_id);
8747 if (cpu == LPFC_VECTOR_MAP_EMPTY) {
8748
8749
8750 for (i = 1; i < max_phys_id; i++) {
8751 phys_id++;
8752 if (phys_id > max_phys_id)
8753 phys_id = min_phys_id;
8754 cpu = lpfc_find_next_cpu(phba, phys_id);
8755 if (cpu == LPFC_VECTOR_MAP_EMPTY)
8756 continue;
8757 goto found;
8758 }
8759
8760
8761 phba->cfg_fcp_io_sched = LPFC_FCP_SCHED_ROUND_ROBIN;
8762 chan = 0;
8763 cpup = phba->sli4_hba.cpu_map;
8764 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
8765 cpup->channel_id = chan;
8766 cpup++;
8767 chan++;
8768 if (chan >= phba->cfg_fcp_io_channel)
8769 chan = 0;
8770 }
8771
8772 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8773 "3329 Cannot set affinity:"
8774 "Error mapping vector %d (%d)\n",
8775 idx, vectors);
8776 return 0;
8777 }
8778found:
8779 cpup += cpu;
8780 if (phba->cfg_fcp_cpu_map == LPFC_DRIVER_CPU_MAP)
8781 lpfc_used_cpu[cpu] = phys_id;
8782
8783
8784 cpup->irq = phba->sli4_hba.msix_entries[idx].vector;
8785
8786
8787 cpup->channel_id = idx;
8788 num_io_channel++;
8789
8790 if (first_cpu == LPFC_VECTOR_MAP_EMPTY)
8791 first_cpu = cpu;
8792
8793
8794 i = irq_set_affinity_hint(phba->sli4_hba.msix_entries[idx].
8795 vector, get_cpu_mask(cpu));
8796
8797 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8798 "3330 Set Affinity: CPU %d channel %d "
8799 "irq %d (%x)\n",
8800 cpu, cpup->channel_id,
8801 phba->sli4_hba.msix_entries[idx].vector, i);
8802
8803
8804 phys_id++;
8805 if (phys_id > max_phys_id)
8806 phys_id = min_phys_id;
8807 }
8808
8809
8810
8811
8812
8813
8814
8815
8816 for (i = min_phys_id; i <= max_phys_id; i++) {
8817
8818
8819
8820
8821
8822 for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++)
8823 chann[idx] = idx;
8824
8825 saved_chann = 0;
8826 used_chann = 0;
8827
8828
8829
8830
8831
8832
8833 cpup = phba->sli4_hba.cpu_map;
8834 cpu = first_cpu;
8835 cpup += cpu;
8836 for (idx = 0; idx < phba->sli4_hba.num_present_cpu;
8837 idx++) {
8838 if (cpup->phys_id == i) {
8839
8840
8841
8842
8843 if (cpup->irq != LPFC_VECTOR_MAP_EMPTY) {
8844 if (saved_chann <=
8845 LPFC_FCP_IO_CHAN_MAX) {
8846 chann[saved_chann] =
8847 cpup->channel_id;
8848 saved_chann++;
8849 }
8850 goto out;
8851 }
8852
8853
8854 if (saved_chann == 0)
8855 saved_chann =
8856 phba->cfg_fcp_io_channel;
8857
8858
8859 cpup->channel_id = chann[used_chann];
8860 num_io_channel++;
8861 used_chann++;
8862 if (used_chann == saved_chann)
8863 used_chann = 0;
8864
8865 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8866 "3331 Set IO_CHANN "
8867 "CPU %d channel %d\n",
8868 idx, cpup->channel_id);
8869 }
8870out:
8871 cpu++;
8872 if (cpu >= phba->sli4_hba.num_present_cpu) {
8873 cpup = phba->sli4_hba.cpu_map;
8874 cpu = 0;
8875 } else {
8876 cpup++;
8877 }
8878 }
8879 }
8880
8881 if (phba->sli4_hba.num_online_cpu != phba->sli4_hba.num_present_cpu) {
8882 cpup = phba->sli4_hba.cpu_map;
8883 for (idx = 0; idx < phba->sli4_hba.num_present_cpu; idx++) {
8884 if (cpup->channel_id == LPFC_VECTOR_MAP_EMPTY) {
8885 cpup->channel_id = 0;
8886 num_io_channel++;
8887
8888 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8889 "3332 Assign IO_CHANN "
8890 "CPU %d channel %d\n",
8891 idx, cpup->channel_id);
8892 }
8893 cpup++;
8894 }
8895 }
8896
8897
8898 if (num_io_channel != phba->sli4_hba.num_present_cpu)
8899 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8900 "3333 Set affinity mismatch:"
8901 "%d chann != %d cpus: %d vectors\n",
8902 num_io_channel, phba->sli4_hba.num_present_cpu,
8903 vectors);
8904
8905
8906 phba->cfg_fcp_io_sched = LPFC_FCP_SCHED_BY_CPU;
8907 return 1;
8908}
8909
8910
8911
8912
8913
8914
8915
8916
8917
8918
8919
8920
8921
8922
8923
8924
8925
8926
8927
8928
8929static int
8930lpfc_sli4_enable_msix(struct lpfc_hba *phba)
8931{
8932 int vectors, rc, index;
8933
8934
8935 for (index = 0; index < phba->cfg_fcp_io_channel; index++)
8936 phba->sli4_hba.msix_entries[index].entry = index;
8937
8938
8939 vectors = phba->cfg_fcp_io_channel;
8940 if (phba->cfg_fof) {
8941 phba->sli4_hba.msix_entries[index].entry = index;
8942 vectors++;
8943 }
8944 rc = pci_enable_msix_range(phba->pcidev, phba->sli4_hba.msix_entries,
8945 2, vectors);
8946 if (rc < 0) {
8947 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8948 "0484 PCI enable MSI-X failed (%d)\n", rc);
8949 goto vec_fail_out;
8950 }
8951 vectors = rc;
8952
8953
8954 for (index = 0; index < vectors; index++)
8955 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8956 "0489 MSI-X entry[%d]: vector=x%x "
8957 "message=%d\n", index,
8958 phba->sli4_hba.msix_entries[index].vector,
8959 phba->sli4_hba.msix_entries[index].entry);
8960
8961
8962 for (index = 0; index < vectors; index++) {
8963 memset(&phba->sli4_hba.handler_name[index], 0, 16);
8964 snprintf((char *)&phba->sli4_hba.handler_name[index],
8965 LPFC_SLI4_HANDLER_NAME_SZ,
8966 LPFC_DRIVER_HANDLER_NAME"%d", index);
8967
8968 phba->sli4_hba.fcp_eq_hdl[index].idx = index;
8969 phba->sli4_hba.fcp_eq_hdl[index].phba = phba;
8970 atomic_set(&phba->sli4_hba.fcp_eq_hdl[index].fcp_eq_in_use, 1);
8971 if (phba->cfg_fof && (index == (vectors - 1)))
8972 rc = request_irq(
8973 phba->sli4_hba.msix_entries[index].vector,
8974 &lpfc_sli4_fof_intr_handler, 0,
8975 (char *)&phba->sli4_hba.handler_name[index],
8976 &phba->sli4_hba.fcp_eq_hdl[index]);
8977 else
8978 rc = request_irq(
8979 phba->sli4_hba.msix_entries[index].vector,
8980 &lpfc_sli4_hba_intr_handler, 0,
8981 (char *)&phba->sli4_hba.handler_name[index],
8982 &phba->sli4_hba.fcp_eq_hdl[index]);
8983 if (rc) {
8984 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8985 "0486 MSI-X fast-path (%d) "
8986 "request_irq failed (%d)\n", index, rc);
8987 goto cfg_fail_out;
8988 }
8989 }
8990
8991 if (phba->cfg_fof)
8992 vectors--;
8993
8994 if (vectors != phba->cfg_fcp_io_channel) {
8995 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8996 "3238 Reducing IO channels to match number of "
8997 "MSI-X vectors, requested %d got %d\n",
8998 phba->cfg_fcp_io_channel, vectors);
8999 phba->cfg_fcp_io_channel = vectors;
9000 }
9001
9002 if (!shost_use_blk_mq(lpfc_shost_from_vport(phba->pport)))
9003 lpfc_sli4_set_affinity(phba, vectors);
9004 return rc;
9005
9006cfg_fail_out:
9007
9008 for (--index; index >= 0; index--) {
9009 irq_set_affinity_hint(phba->sli4_hba.msix_entries[index].
9010 vector, NULL);
9011 free_irq(phba->sli4_hba.msix_entries[index].vector,
9012 &phba->sli4_hba.fcp_eq_hdl[index]);
9013 }
9014
9015
9016 pci_disable_msix(phba->pcidev);
9017
9018vec_fail_out:
9019 return rc;
9020}
9021
9022
9023
9024
9025
9026
9027
9028
9029static void
9030lpfc_sli4_disable_msix(struct lpfc_hba *phba)
9031{
9032 int index;
9033
9034
9035 for (index = 0; index < phba->cfg_fcp_io_channel; index++) {
9036 irq_set_affinity_hint(phba->sli4_hba.msix_entries[index].
9037 vector, NULL);
9038 free_irq(phba->sli4_hba.msix_entries[index].vector,
9039 &phba->sli4_hba.fcp_eq_hdl[index]);
9040 }
9041 if (phba->cfg_fof) {
9042 free_irq(phba->sli4_hba.msix_entries[index].vector,
9043 &phba->sli4_hba.fcp_eq_hdl[index]);
9044 }
9045
9046 pci_disable_msix(phba->pcidev);
9047
9048 return;
9049}
9050
9051
9052
9053
9054
9055
9056
9057
9058
9059
9060
9061
9062
9063
9064
9065static int
9066lpfc_sli4_enable_msi(struct lpfc_hba *phba)
9067{
9068 int rc, index;
9069
9070 rc = pci_enable_msi(phba->pcidev);
9071 if (!rc)
9072 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9073 "0487 PCI enable MSI mode success.\n");
9074 else {
9075 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9076 "0488 PCI enable MSI mode failed (%d)\n", rc);
9077 return rc;
9078 }
9079
9080 rc = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
9081 0, LPFC_DRIVER_NAME, phba);
9082 if (rc) {
9083 pci_disable_msi(phba->pcidev);
9084 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
9085 "0490 MSI request_irq failed (%d)\n", rc);
9086 return rc;
9087 }
9088
9089 for (index = 0; index < phba->cfg_fcp_io_channel; index++) {
9090 phba->sli4_hba.fcp_eq_hdl[index].idx = index;
9091 phba->sli4_hba.fcp_eq_hdl[index].phba = phba;
9092 }
9093
9094 if (phba->cfg_fof) {
9095 phba->sli4_hba.fcp_eq_hdl[index].idx = index;
9096 phba->sli4_hba.fcp_eq_hdl[index].phba = phba;
9097 }
9098 return 0;
9099}
9100
9101
9102
9103
9104
9105
9106
9107
9108
9109
9110
9111static void
9112lpfc_sli4_disable_msi(struct lpfc_hba *phba)
9113{
9114 free_irq(phba->pcidev->irq, phba);
9115 pci_disable_msi(phba->pcidev);
9116 return;
9117}
9118
9119
9120
9121
9122
9123
9124
9125
9126
9127
9128
9129
9130
9131
9132
9133
9134
9135static uint32_t
9136lpfc_sli4_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
9137{
9138 uint32_t intr_mode = LPFC_INTR_ERROR;
9139 int retval, index;
9140
9141 if (cfg_mode == 2) {
9142
9143 retval = 0;
9144 if (!retval) {
9145
9146 retval = lpfc_sli4_enable_msix(phba);
9147 if (!retval) {
9148
9149 phba->intr_type = MSIX;
9150 intr_mode = 2;
9151 }
9152 }
9153 }
9154
9155
9156 if (cfg_mode >= 1 && phba->intr_type == NONE) {
9157 retval = lpfc_sli4_enable_msi(phba);
9158 if (!retval) {
9159
9160 phba->intr_type = MSI;
9161 intr_mode = 1;
9162 }
9163 }
9164
9165
9166 if (phba->intr_type == NONE) {
9167 retval = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
9168 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
9169 if (!retval) {
9170
9171 phba->intr_type = INTx;
9172 intr_mode = 0;
9173 for (index = 0; index < phba->cfg_fcp_io_channel;
9174 index++) {
9175 phba->sli4_hba.fcp_eq_hdl[index].idx = index;
9176 phba->sli4_hba.fcp_eq_hdl[index].phba = phba;
9177 atomic_set(&phba->sli4_hba.fcp_eq_hdl[index].
9178 fcp_eq_in_use, 1);
9179 }
9180 if (phba->cfg_fof) {
9181 phba->sli4_hba.fcp_eq_hdl[index].idx = index;
9182 phba->sli4_hba.fcp_eq_hdl[index].phba = phba;
9183 atomic_set(&phba->sli4_hba.fcp_eq_hdl[index].
9184 fcp_eq_in_use, 1);
9185 }
9186 }
9187 }
9188 return intr_mode;
9189}
9190
9191
9192
9193
9194
9195
9196
9197
9198
9199
9200static void
9201lpfc_sli4_disable_intr(struct lpfc_hba *phba)
9202{
9203
9204 if (phba->intr_type == MSIX)
9205 lpfc_sli4_disable_msix(phba);
9206 else if (phba->intr_type == MSI)
9207 lpfc_sli4_disable_msi(phba);
9208 else if (phba->intr_type == INTx)
9209 free_irq(phba->pcidev->irq, phba);
9210
9211
9212 phba->intr_type = NONE;
9213 phba->sli.slistat.sli_intr = 0;
9214
9215 return;
9216}
9217
9218
9219
9220
9221
9222
9223
9224
9225static void
9226lpfc_unset_hba(struct lpfc_hba *phba)
9227{
9228 struct lpfc_vport *vport = phba->pport;
9229 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
9230
9231 spin_lock_irq(shost->host_lock);
9232 vport->load_flag |= FC_UNLOADING;
9233 spin_unlock_irq(shost->host_lock);
9234
9235 kfree(phba->vpi_bmask);
9236 kfree(phba->vpi_ids);
9237
9238 lpfc_stop_hba_timers(phba);
9239
9240 phba->pport->work_port_events = 0;
9241
9242 lpfc_sli_hba_down(phba);
9243
9244 lpfc_sli_brdrestart(phba);
9245
9246 lpfc_sli_disable_intr(phba);
9247
9248 return;
9249}
9250
9251
9252
9253
9254
9255
9256
9257
9258
9259
9260
9261
9262
9263
9264static void
9265lpfc_sli4_xri_exchange_busy_wait(struct lpfc_hba *phba)
9266{
9267 int wait_time = 0;
9268 int fcp_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_scsi_buf_list);
9269 int els_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
9270
9271 while (!fcp_xri_cmpl || !els_xri_cmpl) {
9272 if (wait_time > LPFC_XRI_EXCH_BUSY_WAIT_TMO) {
9273 if (!fcp_xri_cmpl)
9274 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9275 "2877 FCP XRI exchange busy "
9276 "wait time: %d seconds.\n",
9277 wait_time/1000);
9278 if (!els_xri_cmpl)
9279 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9280 "2878 ELS XRI exchange busy "
9281 "wait time: %d seconds.\n",
9282 wait_time/1000);
9283 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T2);
9284 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T2;
9285 } else {
9286 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1);
9287 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T1;
9288 }
9289 fcp_xri_cmpl =
9290 list_empty(&phba->sli4_hba.lpfc_abts_scsi_buf_list);
9291 els_xri_cmpl =
9292 list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
9293 }
9294}
9295
9296
9297
9298
9299
9300
9301
9302
9303
9304
9305
9306static void
9307lpfc_sli4_hba_unset(struct lpfc_hba *phba)
9308{
9309 int wait_cnt = 0;
9310 LPFC_MBOXQ_t *mboxq;
9311 struct pci_dev *pdev = phba->pcidev;
9312
9313 lpfc_stop_hba_timers(phba);
9314 phba->sli4_hba.intr_enable = 0;
9315
9316
9317
9318
9319
9320
9321
9322 spin_lock_irq(&phba->hbalock);
9323 phba->sli.sli_flag |= LPFC_SLI_ASYNC_MBX_BLK;
9324 spin_unlock_irq(&phba->hbalock);
9325
9326 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
9327 msleep(10);
9328 if (++wait_cnt > LPFC_ACTIVE_MBOX_WAIT_CNT)
9329 break;
9330 }
9331
9332 if (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
9333 spin_lock_irq(&phba->hbalock);
9334 mboxq = phba->sli.mbox_active;
9335 mboxq->u.mb.mbxStatus = MBX_NOT_FINISHED;
9336 __lpfc_mbox_cmpl_put(phba, mboxq);
9337 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
9338 phba->sli.mbox_active = NULL;
9339 spin_unlock_irq(&phba->hbalock);
9340 }
9341
9342
9343 lpfc_sli_hba_iocb_abort(phba);
9344
9345
9346 lpfc_sli4_xri_exchange_busy_wait(phba);
9347
9348
9349 lpfc_sli4_disable_intr(phba);
9350
9351
9352 if (phba->cfg_sriov_nr_virtfn)
9353 pci_disable_sriov(pdev);
9354
9355
9356 kthread_stop(phba->worker_thread);
9357
9358
9359 lpfc_pci_function_reset(phba);
9360 lpfc_sli4_queue_destroy(phba);
9361
9362
9363 phba->pport->work_port_events = 0;
9364}
9365
9366
9367
9368
9369
9370
9371
9372
9373
9374
9375
9376
9377
9378int
9379lpfc_pc_sli4_params_get(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
9380{
9381 int rc;
9382 struct lpfc_mqe *mqe;
9383 struct lpfc_pc_sli4_params *sli4_params;
9384 uint32_t mbox_tmo;
9385
9386 rc = 0;
9387 mqe = &mboxq->u.mqe;
9388
9389
9390 lpfc_pc_sli4_params(mboxq);
9391 if (!phba->sli4_hba.intr_enable)
9392 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9393 else {
9394 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
9395 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
9396 }
9397
9398 if (unlikely(rc))
9399 return 1;
9400
9401 sli4_params = &phba->sli4_hba.pc_sli4_params;
9402 sli4_params->if_type = bf_get(if_type, &mqe->un.sli4_params);
9403 sli4_params->sli_rev = bf_get(sli_rev, &mqe->un.sli4_params);
9404 sli4_params->sli_family = bf_get(sli_family, &mqe->un.sli4_params);
9405 sli4_params->featurelevel_1 = bf_get(featurelevel_1,
9406 &mqe->un.sli4_params);
9407 sli4_params->featurelevel_2 = bf_get(featurelevel_2,
9408 &mqe->un.sli4_params);
9409 sli4_params->proto_types = mqe->un.sli4_params.word3;
9410 sli4_params->sge_supp_len = mqe->un.sli4_params.sge_supp_len;
9411 sli4_params->if_page_sz = bf_get(if_page_sz, &mqe->un.sli4_params);
9412 sli4_params->rq_db_window = bf_get(rq_db_window, &mqe->un.sli4_params);
9413 sli4_params->loopbk_scope = bf_get(loopbk_scope, &mqe->un.sli4_params);
9414 sli4_params->eq_pages_max = bf_get(eq_pages, &mqe->un.sli4_params);
9415 sli4_params->eqe_size = bf_get(eqe_size, &mqe->un.sli4_params);
9416 sli4_params->cq_pages_max = bf_get(cq_pages, &mqe->un.sli4_params);
9417 sli4_params->cqe_size = bf_get(cqe_size, &mqe->un.sli4_params);
9418 sli4_params->mq_pages_max = bf_get(mq_pages, &mqe->un.sli4_params);
9419 sli4_params->mqe_size = bf_get(mqe_size, &mqe->un.sli4_params);
9420 sli4_params->mq_elem_cnt = bf_get(mq_elem_cnt, &mqe->un.sli4_params);
9421 sli4_params->wq_pages_max = bf_get(wq_pages, &mqe->un.sli4_params);
9422 sli4_params->wqe_size = bf_get(wqe_size, &mqe->un.sli4_params);
9423 sli4_params->rq_pages_max = bf_get(rq_pages, &mqe->un.sli4_params);
9424 sli4_params->rqe_size = bf_get(rqe_size, &mqe->un.sli4_params);
9425 sli4_params->hdr_pages_max = bf_get(hdr_pages, &mqe->un.sli4_params);
9426 sli4_params->hdr_size = bf_get(hdr_size, &mqe->un.sli4_params);
9427 sli4_params->hdr_pp_align = bf_get(hdr_pp_align, &mqe->un.sli4_params);
9428 sli4_params->sgl_pages_max = bf_get(sgl_pages, &mqe->un.sli4_params);
9429 sli4_params->sgl_pp_align = bf_get(sgl_pp_align, &mqe->un.sli4_params);
9430
9431
9432 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
9433 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
9434
9435 return rc;
9436}
9437
9438
9439
9440
9441
9442
9443
9444
9445
9446
9447
9448
9449
9450int
9451lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
9452{
9453 int rc;
9454 struct lpfc_mqe *mqe = &mboxq->u.mqe;
9455 struct lpfc_pc_sli4_params *sli4_params;
9456 uint32_t mbox_tmo;
9457 int length;
9458 struct lpfc_sli4_parameters *mbx_sli4_parameters;
9459
9460
9461
9462
9463
9464
9465 phba->sli4_hba.rpi_hdrs_in_use = 1;
9466
9467
9468 length = (sizeof(struct lpfc_mbx_get_sli4_parameters) -
9469 sizeof(struct lpfc_sli4_cfg_mhdr));
9470 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9471 LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS,
9472 length, LPFC_SLI4_MBX_EMBED);
9473 if (!phba->sli4_hba.intr_enable)
9474 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9475 else {
9476 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
9477 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
9478 }
9479 if (unlikely(rc))
9480 return rc;
9481 sli4_params = &phba->sli4_hba.pc_sli4_params;
9482 mbx_sli4_parameters = &mqe->un.get_sli4_parameters.sli4_parameters;
9483 sli4_params->if_type = bf_get(cfg_if_type, mbx_sli4_parameters);
9484 sli4_params->sli_rev = bf_get(cfg_sli_rev, mbx_sli4_parameters);
9485 sli4_params->sli_family = bf_get(cfg_sli_family, mbx_sli4_parameters);
9486 sli4_params->featurelevel_1 = bf_get(cfg_sli_hint_1,
9487 mbx_sli4_parameters);
9488 sli4_params->featurelevel_2 = bf_get(cfg_sli_hint_2,
9489 mbx_sli4_parameters);
9490 if (bf_get(cfg_phwq, mbx_sli4_parameters))
9491 phba->sli3_options |= LPFC_SLI4_PHWQ_ENABLED;
9492 else
9493 phba->sli3_options &= ~LPFC_SLI4_PHWQ_ENABLED;
9494 sli4_params->sge_supp_len = mbx_sli4_parameters->sge_supp_len;
9495 sli4_params->loopbk_scope = bf_get(loopbk_scope, mbx_sli4_parameters);
9496 sli4_params->oas_supported = bf_get(cfg_oas, mbx_sli4_parameters);
9497 sli4_params->cqv = bf_get(cfg_cqv, mbx_sli4_parameters);
9498 sli4_params->mqv = bf_get(cfg_mqv, mbx_sli4_parameters);
9499 sli4_params->wqv = bf_get(cfg_wqv, mbx_sli4_parameters);
9500 sli4_params->rqv = bf_get(cfg_rqv, mbx_sli4_parameters);
9501 sli4_params->wqsize = bf_get(cfg_wqsize, mbx_sli4_parameters);
9502 sli4_params->sgl_pages_max = bf_get(cfg_sgl_page_cnt,
9503 mbx_sli4_parameters);
9504 sli4_params->sgl_pp_align = bf_get(cfg_sgl_pp_align,
9505 mbx_sli4_parameters);
9506 phba->sli4_hba.extents_in_use = bf_get(cfg_ext, mbx_sli4_parameters);
9507 phba->sli4_hba.rpi_hdrs_in_use = bf_get(cfg_hdrr, mbx_sli4_parameters);
9508
9509
9510 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
9511 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
9512
9513 return 0;
9514}
9515
9516
9517
9518
9519
9520
9521
9522
9523
9524
9525
9526
9527
9528
9529
9530
9531
9532
9533static int
9534lpfc_pci_probe_one_s3(struct pci_dev *pdev, const struct pci_device_id *pid)
9535{
9536 struct lpfc_hba *phba;
9537 struct lpfc_vport *vport = NULL;
9538 struct Scsi_Host *shost = NULL;
9539 int error;
9540 uint32_t cfg_mode, intr_mode;
9541
9542
9543 phba = lpfc_hba_alloc(pdev);
9544 if (!phba)
9545 return -ENOMEM;
9546
9547
9548 error = lpfc_enable_pci_dev(phba);
9549 if (error)
9550 goto out_free_phba;
9551
9552
9553 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_LP);
9554 if (error)
9555 goto out_disable_pci_dev;
9556
9557
9558 error = lpfc_sli_pci_mem_setup(phba);
9559 if (error) {
9560 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9561 "1402 Failed to set up pci memory space.\n");
9562 goto out_disable_pci_dev;
9563 }
9564
9565
9566 error = lpfc_setup_driver_resource_phase1(phba);
9567 if (error) {
9568 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9569 "1403 Failed to set up driver resource.\n");
9570 goto out_unset_pci_mem_s3;
9571 }
9572
9573
9574 error = lpfc_sli_driver_resource_setup(phba);
9575 if (error) {
9576 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9577 "1404 Failed to set up driver resource.\n");
9578 goto out_unset_pci_mem_s3;
9579 }
9580
9581
9582 error = lpfc_init_iocb_list(phba, LPFC_IOCB_LIST_CNT);
9583 if (error) {
9584 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9585 "1405 Failed to initialize iocb list.\n");
9586 goto out_unset_driver_resource_s3;
9587 }
9588
9589
9590 error = lpfc_setup_driver_resource_phase2(phba);
9591 if (error) {
9592 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9593 "1406 Failed to set up driver resource.\n");
9594 goto out_free_iocb_list;
9595 }
9596
9597
9598 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
9599
9600
9601 error = lpfc_create_shost(phba);
9602 if (error) {
9603 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9604 "1407 Failed to create scsi host.\n");
9605 goto out_unset_driver_resource;
9606 }
9607
9608
9609 vport = phba->pport;
9610 error = lpfc_alloc_sysfs_attr(vport);
9611 if (error) {
9612 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9613 "1476 Failed to allocate sysfs attr\n");
9614 goto out_destroy_shost;
9615 }
9616
9617 shost = lpfc_shost_from_vport(vport);
9618
9619 cfg_mode = phba->cfg_use_msi;
9620 while (true) {
9621
9622 lpfc_stop_port(phba);
9623
9624 intr_mode = lpfc_sli_enable_intr(phba, cfg_mode);
9625 if (intr_mode == LPFC_INTR_ERROR) {
9626 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9627 "0431 Failed to enable interrupt.\n");
9628 error = -ENODEV;
9629 goto out_free_sysfs_attr;
9630 }
9631
9632 if (lpfc_sli_hba_setup(phba)) {
9633 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9634 "1477 Failed to set up hba\n");
9635 error = -ENODEV;
9636 goto out_remove_device;
9637 }
9638
9639
9640 msleep(50);
9641
9642 if (intr_mode == 0 ||
9643 phba->sli.slistat.sli_intr > LPFC_MSIX_VECTORS) {
9644
9645 phba->intr_mode = intr_mode;
9646 lpfc_log_intr_mode(phba, intr_mode);
9647 break;
9648 } else {
9649 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9650 "0447 Configure interrupt mode (%d) "
9651 "failed active interrupt test.\n",
9652 intr_mode);
9653
9654 lpfc_sli_disable_intr(phba);
9655
9656 cfg_mode = --intr_mode;
9657 }
9658 }
9659
9660
9661 lpfc_post_init_setup(phba);
9662
9663
9664 lpfc_create_static_vport(phba);
9665
9666 return 0;
9667
9668out_remove_device:
9669 lpfc_unset_hba(phba);
9670out_free_sysfs_attr:
9671 lpfc_free_sysfs_attr(vport);
9672out_destroy_shost:
9673 lpfc_destroy_shost(phba);
9674out_unset_driver_resource:
9675 lpfc_unset_driver_resource_phase2(phba);
9676out_free_iocb_list:
9677 lpfc_free_iocb_list(phba);
9678out_unset_driver_resource_s3:
9679 lpfc_sli_driver_resource_unset(phba);
9680out_unset_pci_mem_s3:
9681 lpfc_sli_pci_mem_unset(phba);
9682out_disable_pci_dev:
9683 lpfc_disable_pci_dev(phba);
9684 if (shost)
9685 scsi_host_put(shost);
9686out_free_phba:
9687 lpfc_hba_free(phba);
9688 return error;
9689}
9690
9691
9692
9693
9694
9695
9696
9697
9698
9699
9700static void
9701lpfc_pci_remove_one_s3(struct pci_dev *pdev)
9702{
9703 struct Scsi_Host *shost = pci_get_drvdata(pdev);
9704 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
9705 struct lpfc_vport **vports;
9706 struct lpfc_hba *phba = vport->phba;
9707 int i;
9708 int bars = pci_select_bars(pdev, IORESOURCE_MEM);
9709
9710 spin_lock_irq(&phba->hbalock);
9711 vport->load_flag |= FC_UNLOADING;
9712 spin_unlock_irq(&phba->hbalock);
9713
9714 lpfc_free_sysfs_attr(vport);
9715
9716
9717 vports = lpfc_create_vport_work_array(phba);
9718 if (vports != NULL)
9719 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
9720 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
9721 continue;
9722 fc_vport_terminate(vports[i]->fc_vport);
9723 }
9724 lpfc_destroy_vport_work_array(phba, vports);
9725
9726
9727 fc_remove_host(shost);
9728 scsi_remove_host(shost);
9729 lpfc_cleanup(vport);
9730
9731
9732
9733
9734
9735
9736
9737
9738 lpfc_sli_hba_down(phba);
9739
9740 kthread_stop(phba->worker_thread);
9741
9742 lpfc_sli_brdrestart(phba);
9743
9744 kfree(phba->vpi_bmask);
9745 kfree(phba->vpi_ids);
9746
9747 lpfc_stop_hba_timers(phba);
9748 spin_lock_irq(&phba->hbalock);
9749 list_del_init(&vport->listentry);
9750 spin_unlock_irq(&phba->hbalock);
9751
9752 lpfc_debugfs_terminate(vport);
9753
9754
9755 if (phba->cfg_sriov_nr_virtfn)
9756 pci_disable_sriov(pdev);
9757
9758
9759 lpfc_sli_disable_intr(phba);
9760
9761 scsi_host_put(shost);
9762
9763
9764
9765
9766
9767 lpfc_scsi_free(phba);
9768 lpfc_mem_free_all(phba);
9769
9770 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
9771 phba->hbqslimp.virt, phba->hbqslimp.phys);
9772
9773
9774 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
9775 phba->slim2p.virt, phba->slim2p.phys);
9776
9777
9778 iounmap(phba->ctrl_regs_memmap_p);
9779 iounmap(phba->slim_memmap_p);
9780
9781 lpfc_hba_free(phba);
9782
9783 pci_release_selected_regions(pdev, bars);
9784 pci_disable_device(pdev);
9785}
9786
9787
9788
9789
9790
9791
9792
9793
9794
9795
9796
9797
9798
9799
9800
9801
9802
9803
9804
9805
9806
9807
9808static int
9809lpfc_pci_suspend_one_s3(struct pci_dev *pdev, pm_message_t msg)
9810{
9811 struct Scsi_Host *shost = pci_get_drvdata(pdev);
9812 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
9813
9814 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9815 "0473 PCI device Power Management suspend.\n");
9816
9817
9818 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
9819 lpfc_offline(phba);
9820 kthread_stop(phba->worker_thread);
9821
9822
9823 lpfc_sli_disable_intr(phba);
9824
9825
9826 pci_save_state(pdev);
9827 pci_set_power_state(pdev, PCI_D3hot);
9828
9829 return 0;
9830}
9831
9832
9833
9834
9835
9836
9837
9838
9839
9840
9841
9842
9843
9844
9845
9846
9847
9848
9849
9850
9851static int
9852lpfc_pci_resume_one_s3(struct pci_dev *pdev)
9853{
9854 struct Scsi_Host *shost = pci_get_drvdata(pdev);
9855 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
9856 uint32_t intr_mode;
9857 int error;
9858
9859 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9860 "0452 PCI device Power Management resume.\n");
9861
9862
9863 pci_set_power_state(pdev, PCI_D0);
9864 pci_restore_state(pdev);
9865
9866
9867
9868
9869
9870 pci_save_state(pdev);
9871
9872 if (pdev->is_busmaster)
9873 pci_set_master(pdev);
9874
9875
9876 phba->worker_thread = kthread_run(lpfc_do_work, phba,
9877 "lpfc_worker_%d", phba->brd_no);
9878 if (IS_ERR(phba->worker_thread)) {
9879 error = PTR_ERR(phba->worker_thread);
9880 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9881 "0434 PM resume failed to start worker "
9882 "thread: error=x%x.\n", error);
9883 return error;
9884 }
9885
9886
9887 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
9888 if (intr_mode == LPFC_INTR_ERROR) {
9889 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9890 "0430 PM resume Failed to enable interrupt\n");
9891 return -EIO;
9892 } else
9893 phba->intr_mode = intr_mode;
9894
9895
9896 lpfc_sli_brdrestart(phba);
9897 lpfc_online(phba);
9898
9899
9900 lpfc_log_intr_mode(phba, phba->intr_mode);
9901
9902 return 0;
9903}
9904
9905
9906
9907
9908
9909
9910
9911
9912static void
9913lpfc_sli_prep_dev_for_recover(struct lpfc_hba *phba)
9914{
9915 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9916 "2723 PCI channel I/O abort preparing for recovery\n");
9917
9918
9919
9920
9921
9922 lpfc_sli_abort_fcp_rings(phba);
9923}
9924
9925
9926
9927
9928
9929
9930
9931
9932
9933static void
9934lpfc_sli_prep_dev_for_reset(struct lpfc_hba *phba)
9935{
9936 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9937 "2710 PCI channel disable preparing for reset\n");
9938
9939
9940 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
9941
9942
9943 lpfc_scsi_dev_block(phba);
9944
9945
9946 lpfc_sli_flush_fcp_rings(phba);
9947
9948
9949 lpfc_stop_hba_timers(phba);
9950
9951
9952 lpfc_sli_disable_intr(phba);
9953 pci_disable_device(phba->pcidev);
9954}
9955
9956
9957
9958
9959
9960
9961
9962
9963
9964static void
9965lpfc_sli_prep_dev_for_perm_failure(struct lpfc_hba *phba)
9966{
9967 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9968 "2711 PCI channel permanent disable for failure\n");
9969
9970 lpfc_scsi_dev_block(phba);
9971
9972
9973 lpfc_stop_hba_timers(phba);
9974
9975
9976 lpfc_sli_flush_fcp_rings(phba);
9977}
9978
9979
9980
9981
9982
9983
9984
9985
9986
9987
9988
9989
9990
9991
9992
9993
9994
9995
9996
9997static pci_ers_result_t
9998lpfc_io_error_detected_s3(struct pci_dev *pdev, pci_channel_state_t state)
9999{
10000 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10001 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10002
10003 switch (state) {
10004 case pci_channel_io_normal:
10005
10006 lpfc_sli_prep_dev_for_recover(phba);
10007 return PCI_ERS_RESULT_CAN_RECOVER;
10008 case pci_channel_io_frozen:
10009
10010 lpfc_sli_prep_dev_for_reset(phba);
10011 return PCI_ERS_RESULT_NEED_RESET;
10012 case pci_channel_io_perm_failure:
10013
10014 lpfc_sli_prep_dev_for_perm_failure(phba);
10015 return PCI_ERS_RESULT_DISCONNECT;
10016 default:
10017
10018 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10019 "0472 Unknown PCI error state: x%x\n", state);
10020 lpfc_sli_prep_dev_for_reset(phba);
10021 return PCI_ERS_RESULT_NEED_RESET;
10022 }
10023}
10024
10025
10026
10027
10028
10029
10030
10031
10032
10033
10034
10035
10036
10037
10038
10039
10040
10041
10042
10043static pci_ers_result_t
10044lpfc_io_slot_reset_s3(struct pci_dev *pdev)
10045{
10046 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10047 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10048 struct lpfc_sli *psli = &phba->sli;
10049 uint32_t intr_mode;
10050
10051 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
10052 if (pci_enable_device_mem(pdev)) {
10053 printk(KERN_ERR "lpfc: Cannot re-enable "
10054 "PCI device after reset.\n");
10055 return PCI_ERS_RESULT_DISCONNECT;
10056 }
10057
10058 pci_restore_state(pdev);
10059
10060
10061
10062
10063
10064 pci_save_state(pdev);
10065
10066 if (pdev->is_busmaster)
10067 pci_set_master(pdev);
10068
10069 spin_lock_irq(&phba->hbalock);
10070 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
10071 spin_unlock_irq(&phba->hbalock);
10072
10073
10074 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
10075 if (intr_mode == LPFC_INTR_ERROR) {
10076 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10077 "0427 Cannot re-enable interrupt after "
10078 "slot reset.\n");
10079 return PCI_ERS_RESULT_DISCONNECT;
10080 } else
10081 phba->intr_mode = intr_mode;
10082
10083
10084 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
10085 lpfc_offline(phba);
10086 lpfc_sli_brdrestart(phba);
10087
10088
10089 lpfc_log_intr_mode(phba, phba->intr_mode);
10090
10091 return PCI_ERS_RESULT_RECOVERED;
10092}
10093
10094
10095
10096
10097
10098
10099
10100
10101
10102
10103
10104static void
10105lpfc_io_resume_s3(struct pci_dev *pdev)
10106{
10107 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10108 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10109
10110
10111 lpfc_online(phba);
10112
10113
10114 if (phba->hba_flag & HBA_AER_ENABLED)
10115 pci_cleanup_aer_uncorrect_error_status(pdev);
10116}
10117
10118
10119
10120
10121
10122
10123
10124int
10125lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *phba)
10126{
10127 int max_xri = phba->sli4_hba.max_cfg_param.max_xri;
10128
10129 if (phba->sli_rev == LPFC_SLI_REV4) {
10130 if (max_xri <= 100)
10131 return 10;
10132 else if (max_xri <= 256)
10133 return 25;
10134 else if (max_xri <= 512)
10135 return 50;
10136 else if (max_xri <= 1024)
10137 return 100;
10138 else if (max_xri <= 1536)
10139 return 150;
10140 else if (max_xri <= 2048)
10141 return 200;
10142 else
10143 return 250;
10144 } else
10145 return 0;
10146}
10147
10148
10149
10150
10151
10152
10153
10154static void
10155lpfc_write_firmware(const struct firmware *fw, void *context)
10156{
10157 struct lpfc_hba *phba = (struct lpfc_hba *)context;
10158 char fwrev[FW_REV_STR_SIZE];
10159 struct lpfc_grp_hdr *image;
10160 struct list_head dma_buffer_list;
10161 int i, rc = 0;
10162 struct lpfc_dmabuf *dmabuf, *next;
10163 uint32_t offset = 0, temp_offset = 0;
10164
10165
10166 if (!fw) {
10167 rc = -ENXIO;
10168 goto out;
10169 }
10170 image = (struct lpfc_grp_hdr *)fw->data;
10171
10172 INIT_LIST_HEAD(&dma_buffer_list);
10173 if ((be32_to_cpu(image->magic_number) != LPFC_GROUP_OJECT_MAGIC_NUM) ||
10174 (bf_get_be32(lpfc_grp_hdr_file_type, image) !=
10175 LPFC_FILE_TYPE_GROUP) ||
10176 (bf_get_be32(lpfc_grp_hdr_id, image) != LPFC_FILE_ID_GROUP) ||
10177 (be32_to_cpu(image->size) != fw->size)) {
10178 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10179 "3022 Invalid FW image found. "
10180 "Magic:%x Type:%x ID:%x\n",
10181 be32_to_cpu(image->magic_number),
10182 bf_get_be32(lpfc_grp_hdr_file_type, image),
10183 bf_get_be32(lpfc_grp_hdr_id, image));
10184 rc = -EINVAL;
10185 goto release_out;
10186 }
10187 lpfc_decode_firmware_rev(phba, fwrev, 1);
10188 if (strncmp(fwrev, image->revision, strnlen(image->revision, 16))) {
10189 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10190 "3023 Updating Firmware, Current Version:%s "
10191 "New Version:%s\n",
10192 fwrev, image->revision);
10193 for (i = 0; i < LPFC_MBX_WR_CONFIG_MAX_BDE; i++) {
10194 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf),
10195 GFP_KERNEL);
10196 if (!dmabuf) {
10197 rc = -ENOMEM;
10198 goto release_out;
10199 }
10200 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
10201 SLI4_PAGE_SIZE,
10202 &dmabuf->phys,
10203 GFP_KERNEL);
10204 if (!dmabuf->virt) {
10205 kfree(dmabuf);
10206 rc = -ENOMEM;
10207 goto release_out;
10208 }
10209 list_add_tail(&dmabuf->list, &dma_buffer_list);
10210 }
10211 while (offset < fw->size) {
10212 temp_offset = offset;
10213 list_for_each_entry(dmabuf, &dma_buffer_list, list) {
10214 if (temp_offset + SLI4_PAGE_SIZE > fw->size) {
10215 memcpy(dmabuf->virt,
10216 fw->data + temp_offset,
10217 fw->size - temp_offset);
10218 temp_offset = fw->size;
10219 break;
10220 }
10221 memcpy(dmabuf->virt, fw->data + temp_offset,
10222 SLI4_PAGE_SIZE);
10223 temp_offset += SLI4_PAGE_SIZE;
10224 }
10225 rc = lpfc_wr_object(phba, &dma_buffer_list,
10226 (fw->size - offset), &offset);
10227 if (rc)
10228 goto release_out;
10229 }
10230 rc = offset;
10231 }
10232
10233release_out:
10234 list_for_each_entry_safe(dmabuf, next, &dma_buffer_list, list) {
10235 list_del(&dmabuf->list);
10236 dma_free_coherent(&phba->pcidev->dev, SLI4_PAGE_SIZE,
10237 dmabuf->virt, dmabuf->phys);
10238 kfree(dmabuf);
10239 }
10240 release_firmware(fw);
10241out:
10242 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10243 "3024 Firmware update done: %d.\n", rc);
10244 return;
10245}
10246
10247
10248
10249
10250
10251
10252
10253
10254int
10255lpfc_sli4_request_firmware_update(struct lpfc_hba *phba, uint8_t fw_upgrade)
10256{
10257 uint8_t file_name[ELX_MODEL_NAME_SIZE];
10258 int ret;
10259 const struct firmware *fw;
10260
10261
10262 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
10263 LPFC_SLI_INTF_IF_TYPE_2)
10264 return -EPERM;
10265
10266 snprintf(file_name, ELX_MODEL_NAME_SIZE, "%s.grp", phba->ModelName);
10267
10268 if (fw_upgrade == INT_FW_UPGRADE) {
10269 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
10270 file_name, &phba->pcidev->dev,
10271 GFP_KERNEL, (void *)phba,
10272 lpfc_write_firmware);
10273 } else if (fw_upgrade == RUN_FW_UPGRADE) {
10274 ret = request_firmware(&fw, file_name, &phba->pcidev->dev);
10275 if (!ret)
10276 lpfc_write_firmware(fw, (void *)phba);
10277 } else {
10278 ret = -EINVAL;
10279 }
10280
10281 return ret;
10282}
10283
10284
10285
10286
10287
10288
10289
10290
10291
10292
10293
10294
10295
10296
10297
10298
10299
10300
10301
10302static int
10303lpfc_pci_probe_one_s4(struct pci_dev *pdev, const struct pci_device_id *pid)
10304{
10305 struct lpfc_hba *phba;
10306 struct lpfc_vport *vport = NULL;
10307 struct Scsi_Host *shost = NULL;
10308 int error;
10309 uint32_t cfg_mode, intr_mode;
10310 int adjusted_fcp_io_channel;
10311
10312
10313 phba = lpfc_hba_alloc(pdev);
10314 if (!phba)
10315 return -ENOMEM;
10316
10317
10318 error = lpfc_enable_pci_dev(phba);
10319 if (error)
10320 goto out_free_phba;
10321
10322
10323 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_OC);
10324 if (error)
10325 goto out_disable_pci_dev;
10326
10327
10328 error = lpfc_sli4_pci_mem_setup(phba);
10329 if (error) {
10330 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10331 "1410 Failed to set up pci memory space.\n");
10332 goto out_disable_pci_dev;
10333 }
10334
10335
10336 error = lpfc_setup_driver_resource_phase1(phba);
10337 if (error) {
10338 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10339 "1411 Failed to set up driver resource.\n");
10340 goto out_unset_pci_mem_s4;
10341 }
10342
10343
10344 error = lpfc_sli4_driver_resource_setup(phba);
10345 if (error) {
10346 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10347 "1412 Failed to set up driver resource.\n");
10348 goto out_unset_pci_mem_s4;
10349 }
10350
10351
10352
10353 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10354 "2821 initialize iocb list %d.\n",
10355 phba->cfg_iocb_cnt*1024);
10356 error = lpfc_init_iocb_list(phba, phba->cfg_iocb_cnt*1024);
10357
10358 if (error) {
10359 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10360 "1413 Failed to initialize iocb list.\n");
10361 goto out_unset_driver_resource_s4;
10362 }
10363
10364 INIT_LIST_HEAD(&phba->active_rrq_list);
10365 INIT_LIST_HEAD(&phba->fcf.fcf_pri_list);
10366
10367
10368 error = lpfc_setup_driver_resource_phase2(phba);
10369 if (error) {
10370 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10371 "1414 Failed to set up driver resource.\n");
10372 goto out_free_iocb_list;
10373 }
10374
10375
10376 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
10377
10378
10379 error = lpfc_create_shost(phba);
10380 if (error) {
10381 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10382 "1415 Failed to create scsi host.\n");
10383 goto out_unset_driver_resource;
10384 }
10385
10386
10387 vport = phba->pport;
10388 error = lpfc_alloc_sysfs_attr(vport);
10389 if (error) {
10390 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10391 "1416 Failed to allocate sysfs attr\n");
10392 goto out_destroy_shost;
10393 }
10394
10395 shost = lpfc_shost_from_vport(vport);
10396
10397 cfg_mode = phba->cfg_use_msi;
10398
10399
10400 lpfc_stop_port(phba);
10401
10402 intr_mode = lpfc_sli4_enable_intr(phba, cfg_mode);
10403 if (intr_mode == LPFC_INTR_ERROR) {
10404 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10405 "0426 Failed to enable interrupt.\n");
10406 error = -ENODEV;
10407 goto out_free_sysfs_attr;
10408 }
10409
10410 if (phba->intr_type != MSIX)
10411 adjusted_fcp_io_channel = 1;
10412 else
10413 adjusted_fcp_io_channel = phba->cfg_fcp_io_channel;
10414 phba->cfg_fcp_io_channel = adjusted_fcp_io_channel;
10415
10416 if (lpfc_sli4_hba_setup(phba)) {
10417 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10418 "1421 Failed to set up hba\n");
10419 error = -ENODEV;
10420 goto out_disable_intr;
10421 }
10422
10423
10424 phba->intr_mode = intr_mode;
10425 lpfc_log_intr_mode(phba, intr_mode);
10426
10427
10428 lpfc_post_init_setup(phba);
10429
10430
10431 if (phba->cfg_request_firmware_upgrade)
10432 lpfc_sli4_request_firmware_update(phba, INT_FW_UPGRADE);
10433
10434
10435 lpfc_create_static_vport(phba);
10436 return 0;
10437
10438out_disable_intr:
10439 lpfc_sli4_disable_intr(phba);
10440out_free_sysfs_attr:
10441 lpfc_free_sysfs_attr(vport);
10442out_destroy_shost:
10443 lpfc_destroy_shost(phba);
10444out_unset_driver_resource:
10445 lpfc_unset_driver_resource_phase2(phba);
10446out_free_iocb_list:
10447 lpfc_free_iocb_list(phba);
10448out_unset_driver_resource_s4:
10449 lpfc_sli4_driver_resource_unset(phba);
10450out_unset_pci_mem_s4:
10451 lpfc_sli4_pci_mem_unset(phba);
10452out_disable_pci_dev:
10453 lpfc_disable_pci_dev(phba);
10454 if (shost)
10455 scsi_host_put(shost);
10456out_free_phba:
10457 lpfc_hba_free(phba);
10458 return error;
10459}
10460
10461
10462
10463
10464
10465
10466
10467
10468
10469
10470static void
10471lpfc_pci_remove_one_s4(struct pci_dev *pdev)
10472{
10473 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10474 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
10475 struct lpfc_vport **vports;
10476 struct lpfc_hba *phba = vport->phba;
10477 int i;
10478
10479
10480 spin_lock_irq(&phba->hbalock);
10481 vport->load_flag |= FC_UNLOADING;
10482 spin_unlock_irq(&phba->hbalock);
10483
10484
10485 lpfc_free_sysfs_attr(vport);
10486
10487
10488 vports = lpfc_create_vport_work_array(phba);
10489 if (vports != NULL)
10490 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
10491 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
10492 continue;
10493 fc_vport_terminate(vports[i]->fc_vport);
10494 }
10495 lpfc_destroy_vport_work_array(phba, vports);
10496
10497
10498 fc_remove_host(shost);
10499 scsi_remove_host(shost);
10500
10501
10502 lpfc_cleanup(vport);
10503
10504
10505
10506
10507
10508
10509 lpfc_debugfs_terminate(vport);
10510 lpfc_sli4_hba_unset(phba);
10511
10512 spin_lock_irq(&phba->hbalock);
10513 list_del_init(&vport->listentry);
10514 spin_unlock_irq(&phba->hbalock);
10515
10516
10517
10518
10519 lpfc_scsi_free(phba);
10520
10521 lpfc_sli4_driver_resource_unset(phba);
10522
10523
10524 lpfc_sli4_pci_mem_unset(phba);
10525
10526
10527 scsi_host_put(shost);
10528 lpfc_disable_pci_dev(phba);
10529
10530
10531 lpfc_hba_free(phba);
10532
10533 return;
10534}
10535
10536
10537
10538
10539
10540
10541
10542
10543
10544
10545
10546
10547
10548
10549
10550
10551
10552
10553
10554
10555
10556
10557static int
10558lpfc_pci_suspend_one_s4(struct pci_dev *pdev, pm_message_t msg)
10559{
10560 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10561 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10562
10563 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10564 "2843 PCI device Power Management suspend.\n");
10565
10566
10567 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
10568 lpfc_offline(phba);
10569 kthread_stop(phba->worker_thread);
10570
10571
10572 lpfc_sli4_disable_intr(phba);
10573 lpfc_sli4_queue_destroy(phba);
10574
10575
10576 pci_save_state(pdev);
10577 pci_set_power_state(pdev, PCI_D3hot);
10578
10579 return 0;
10580}
10581
10582
10583
10584
10585
10586
10587
10588
10589
10590
10591
10592
10593
10594
10595
10596
10597
10598
10599
10600
10601static int
10602lpfc_pci_resume_one_s4(struct pci_dev *pdev)
10603{
10604 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10605 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10606 uint32_t intr_mode;
10607 int error;
10608
10609 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10610 "0292 PCI device Power Management resume.\n");
10611
10612
10613 pci_set_power_state(pdev, PCI_D0);
10614 pci_restore_state(pdev);
10615
10616
10617
10618
10619
10620 pci_save_state(pdev);
10621
10622 if (pdev->is_busmaster)
10623 pci_set_master(pdev);
10624
10625
10626 phba->worker_thread = kthread_run(lpfc_do_work, phba,
10627 "lpfc_worker_%d", phba->brd_no);
10628 if (IS_ERR(phba->worker_thread)) {
10629 error = PTR_ERR(phba->worker_thread);
10630 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10631 "0293 PM resume failed to start worker "
10632 "thread: error=x%x.\n", error);
10633 return error;
10634 }
10635
10636
10637 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
10638 if (intr_mode == LPFC_INTR_ERROR) {
10639 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10640 "0294 PM resume Failed to enable interrupt\n");
10641 return -EIO;
10642 } else
10643 phba->intr_mode = intr_mode;
10644
10645
10646 lpfc_sli_brdrestart(phba);
10647 lpfc_online(phba);
10648
10649
10650 lpfc_log_intr_mode(phba, phba->intr_mode);
10651
10652 return 0;
10653}
10654
10655
10656
10657
10658
10659
10660
10661
10662static void
10663lpfc_sli4_prep_dev_for_recover(struct lpfc_hba *phba)
10664{
10665 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10666 "2828 PCI channel I/O abort preparing for recovery\n");
10667
10668
10669
10670
10671 lpfc_sli_abort_fcp_rings(phba);
10672}
10673
10674
10675
10676
10677
10678
10679
10680
10681
10682static void
10683lpfc_sli4_prep_dev_for_reset(struct lpfc_hba *phba)
10684{
10685 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10686 "2826 PCI channel disable preparing for reset\n");
10687
10688
10689 lpfc_block_mgmt_io(phba, LPFC_MBX_NO_WAIT);
10690
10691
10692 lpfc_scsi_dev_block(phba);
10693
10694
10695 lpfc_sli_flush_fcp_rings(phba);
10696
10697
10698 lpfc_stop_hba_timers(phba);
10699
10700
10701 lpfc_sli4_disable_intr(phba);
10702 lpfc_sli4_queue_destroy(phba);
10703 pci_disable_device(phba->pcidev);
10704}
10705
10706
10707
10708
10709
10710
10711
10712
10713
10714static void
10715lpfc_sli4_prep_dev_for_perm_failure(struct lpfc_hba *phba)
10716{
10717 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10718 "2827 PCI channel permanent disable for failure\n");
10719
10720
10721 lpfc_scsi_dev_block(phba);
10722
10723
10724 lpfc_stop_hba_timers(phba);
10725
10726
10727 lpfc_sli_flush_fcp_rings(phba);
10728}
10729
10730
10731
10732
10733
10734
10735
10736
10737
10738
10739
10740
10741
10742
10743
10744
10745
10746static pci_ers_result_t
10747lpfc_io_error_detected_s4(struct pci_dev *pdev, pci_channel_state_t state)
10748{
10749 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10750 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10751
10752 switch (state) {
10753 case pci_channel_io_normal:
10754
10755 lpfc_sli4_prep_dev_for_recover(phba);
10756 return PCI_ERS_RESULT_CAN_RECOVER;
10757 case pci_channel_io_frozen:
10758
10759 lpfc_sli4_prep_dev_for_reset(phba);
10760 return PCI_ERS_RESULT_NEED_RESET;
10761 case pci_channel_io_perm_failure:
10762
10763 lpfc_sli4_prep_dev_for_perm_failure(phba);
10764 return PCI_ERS_RESULT_DISCONNECT;
10765 default:
10766
10767 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10768 "2825 Unknown PCI error state: x%x\n", state);
10769 lpfc_sli4_prep_dev_for_reset(phba);
10770 return PCI_ERS_RESULT_NEED_RESET;
10771 }
10772}
10773
10774
10775
10776
10777
10778
10779
10780
10781
10782
10783
10784
10785
10786
10787
10788
10789
10790
10791
10792static pci_ers_result_t
10793lpfc_io_slot_reset_s4(struct pci_dev *pdev)
10794{
10795 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10796 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10797 struct lpfc_sli *psli = &phba->sli;
10798 uint32_t intr_mode;
10799
10800 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
10801 if (pci_enable_device_mem(pdev)) {
10802 printk(KERN_ERR "lpfc: Cannot re-enable "
10803 "PCI device after reset.\n");
10804 return PCI_ERS_RESULT_DISCONNECT;
10805 }
10806
10807 pci_restore_state(pdev);
10808
10809
10810
10811
10812
10813 pci_save_state(pdev);
10814
10815 if (pdev->is_busmaster)
10816 pci_set_master(pdev);
10817
10818 spin_lock_irq(&phba->hbalock);
10819 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
10820 spin_unlock_irq(&phba->hbalock);
10821
10822
10823 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
10824 if (intr_mode == LPFC_INTR_ERROR) {
10825 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10826 "2824 Cannot re-enable interrupt after "
10827 "slot reset.\n");
10828 return PCI_ERS_RESULT_DISCONNECT;
10829 } else
10830 phba->intr_mode = intr_mode;
10831
10832
10833 lpfc_log_intr_mode(phba, phba->intr_mode);
10834
10835 return PCI_ERS_RESULT_RECOVERED;
10836}
10837
10838
10839
10840
10841
10842
10843
10844
10845
10846
10847
10848static void
10849lpfc_io_resume_s4(struct pci_dev *pdev)
10850{
10851 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10852 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10853
10854
10855
10856
10857
10858
10859
10860 if (!(phba->sli.sli_flag & LPFC_SLI_ACTIVE)) {
10861
10862 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
10863 lpfc_offline(phba);
10864 lpfc_sli_brdrestart(phba);
10865
10866 lpfc_online(phba);
10867 }
10868
10869
10870 if (phba->hba_flag & HBA_AER_ENABLED)
10871 pci_cleanup_aer_uncorrect_error_status(pdev);
10872}
10873
10874
10875
10876
10877
10878
10879
10880
10881
10882
10883
10884
10885
10886
10887
10888
10889
10890
10891
10892static int
10893lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
10894{
10895 int rc;
10896 struct lpfc_sli_intf intf;
10897
10898 if (pci_read_config_dword(pdev, LPFC_SLI_INTF, &intf.word0))
10899 return -ENODEV;
10900
10901 if ((bf_get(lpfc_sli_intf_valid, &intf) == LPFC_SLI_INTF_VALID) &&
10902 (bf_get(lpfc_sli_intf_slirev, &intf) == LPFC_SLI_INTF_REV_SLI4))
10903 rc = lpfc_pci_probe_one_s4(pdev, pid);
10904 else
10905 rc = lpfc_pci_probe_one_s3(pdev, pid);
10906
10907 return rc;
10908}
10909
10910
10911
10912
10913
10914
10915
10916
10917
10918
10919
10920static void
10921lpfc_pci_remove_one(struct pci_dev *pdev)
10922{
10923 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10924 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10925
10926 switch (phba->pci_dev_grp) {
10927 case LPFC_PCI_DEV_LP:
10928 lpfc_pci_remove_one_s3(pdev);
10929 break;
10930 case LPFC_PCI_DEV_OC:
10931 lpfc_pci_remove_one_s4(pdev);
10932 break;
10933 default:
10934 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10935 "1424 Invalid PCI device group: 0x%x\n",
10936 phba->pci_dev_grp);
10937 break;
10938 }
10939 return;
10940}
10941
10942
10943
10944
10945
10946
10947
10948
10949
10950
10951
10952
10953
10954
10955
10956static int
10957lpfc_pci_suspend_one(struct pci_dev *pdev, pm_message_t msg)
10958{
10959 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10960 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10961 int rc = -ENODEV;
10962
10963 switch (phba->pci_dev_grp) {
10964 case LPFC_PCI_DEV_LP:
10965 rc = lpfc_pci_suspend_one_s3(pdev, msg);
10966 break;
10967 case LPFC_PCI_DEV_OC:
10968 rc = lpfc_pci_suspend_one_s4(pdev, msg);
10969 break;
10970 default:
10971 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10972 "1425 Invalid PCI device group: 0x%x\n",
10973 phba->pci_dev_grp);
10974 break;
10975 }
10976 return rc;
10977}
10978
10979
10980
10981
10982
10983
10984
10985
10986
10987
10988
10989
10990
10991
10992static int
10993lpfc_pci_resume_one(struct pci_dev *pdev)
10994{
10995 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10996 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10997 int rc = -ENODEV;
10998
10999 switch (phba->pci_dev_grp) {
11000 case LPFC_PCI_DEV_LP:
11001 rc = lpfc_pci_resume_one_s3(pdev);
11002 break;
11003 case LPFC_PCI_DEV_OC:
11004 rc = lpfc_pci_resume_one_s4(pdev);
11005 break;
11006 default:
11007 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11008 "1426 Invalid PCI device group: 0x%x\n",
11009 phba->pci_dev_grp);
11010 break;
11011 }
11012 return rc;
11013}
11014
11015
11016
11017
11018
11019
11020
11021
11022
11023
11024
11025
11026
11027
11028
11029
11030static pci_ers_result_t
11031lpfc_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
11032{
11033 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11034 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11035 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
11036
11037 switch (phba->pci_dev_grp) {
11038 case LPFC_PCI_DEV_LP:
11039 rc = lpfc_io_error_detected_s3(pdev, state);
11040 break;
11041 case LPFC_PCI_DEV_OC:
11042 rc = lpfc_io_error_detected_s4(pdev, state);
11043 break;
11044 default:
11045 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11046 "1427 Invalid PCI device group: 0x%x\n",
11047 phba->pci_dev_grp);
11048 break;
11049 }
11050 return rc;
11051}
11052
11053
11054
11055
11056
11057
11058
11059
11060
11061
11062
11063
11064
11065
11066
11067static pci_ers_result_t
11068lpfc_io_slot_reset(struct pci_dev *pdev)
11069{
11070 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11071 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11072 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
11073
11074 switch (phba->pci_dev_grp) {
11075 case LPFC_PCI_DEV_LP:
11076 rc = lpfc_io_slot_reset_s3(pdev);
11077 break;
11078 case LPFC_PCI_DEV_OC:
11079 rc = lpfc_io_slot_reset_s4(pdev);
11080 break;
11081 default:
11082 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11083 "1428 Invalid PCI device group: 0x%x\n",
11084 phba->pci_dev_grp);
11085 break;
11086 }
11087 return rc;
11088}
11089
11090
11091
11092
11093
11094
11095
11096
11097
11098
11099
11100static void
11101lpfc_io_resume(struct pci_dev *pdev)
11102{
11103 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11104 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11105
11106 switch (phba->pci_dev_grp) {
11107 case LPFC_PCI_DEV_LP:
11108 lpfc_io_resume_s3(pdev);
11109 break;
11110 case LPFC_PCI_DEV_OC:
11111 lpfc_io_resume_s4(pdev);
11112 break;
11113 default:
11114 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11115 "1429 Invalid PCI device group: 0x%x\n",
11116 phba->pci_dev_grp);
11117 break;
11118 }
11119 return;
11120}
11121
11122
11123
11124
11125
11126
11127
11128
11129
11130
11131
11132void
11133lpfc_sli4_oas_verify(struct lpfc_hba *phba)
11134{
11135
11136 if (!phba->cfg_EnableXLane)
11137 return;
11138
11139 if (phba->sli4_hba.pc_sli4_params.oas_supported) {
11140 phba->cfg_fof = 1;
11141 } else {
11142 phba->cfg_fof = 0;
11143 if (phba->device_data_mem_pool)
11144 mempool_destroy(phba->device_data_mem_pool);
11145 phba->device_data_mem_pool = NULL;
11146 }
11147
11148 return;
11149}
11150
11151
11152
11153
11154
11155
11156
11157
11158
11159
11160
11161
11162int
11163lpfc_fof_queue_setup(struct lpfc_hba *phba)
11164{
11165 struct lpfc_sli *psli = &phba->sli;
11166 int rc;
11167
11168 rc = lpfc_eq_create(phba, phba->sli4_hba.fof_eq, LPFC_MAX_IMAX);
11169 if (rc)
11170 return -ENOMEM;
11171
11172 if (phba->cfg_fof) {
11173
11174 rc = lpfc_cq_create(phba, phba->sli4_hba.oas_cq,
11175 phba->sli4_hba.fof_eq, LPFC_WCQ, LPFC_FCP);
11176 if (rc)
11177 goto out_oas_cq;
11178
11179 rc = lpfc_wq_create(phba, phba->sli4_hba.oas_wq,
11180 phba->sli4_hba.oas_cq, LPFC_FCP);
11181 if (rc)
11182 goto out_oas_wq;
11183
11184 phba->sli4_hba.oas_cq->pring = &psli->ring[LPFC_FCP_OAS_RING];
11185 phba->sli4_hba.oas_ring = &psli->ring[LPFC_FCP_OAS_RING];
11186 }
11187
11188 return 0;
11189
11190out_oas_wq:
11191 lpfc_cq_destroy(phba, phba->sli4_hba.oas_cq);
11192out_oas_cq:
11193 lpfc_eq_destroy(phba, phba->sli4_hba.fof_eq);
11194 return rc;
11195
11196}
11197
11198
11199
11200
11201
11202
11203
11204
11205
11206
11207
11208
11209
11210
11211
11212int
11213lpfc_fof_queue_create(struct lpfc_hba *phba)
11214{
11215 struct lpfc_queue *qdesc;
11216
11217
11218 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.eq_esize,
11219 phba->sli4_hba.eq_ecount);
11220 if (!qdesc)
11221 goto out_error;
11222
11223 phba->sli4_hba.fof_eq = qdesc;
11224
11225 if (phba->cfg_fof) {
11226
11227
11228 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
11229 phba->sli4_hba.cq_ecount);
11230 if (!qdesc)
11231 goto out_error;
11232
11233 phba->sli4_hba.oas_cq = qdesc;
11234
11235
11236 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.wq_esize,
11237 phba->sli4_hba.wq_ecount);
11238 if (!qdesc)
11239 goto out_error;
11240
11241 phba->sli4_hba.oas_wq = qdesc;
11242
11243 }
11244 return 0;
11245
11246out_error:
11247 lpfc_fof_queue_destroy(phba);
11248 return -ENOMEM;
11249}
11250
11251
11252
11253
11254
11255
11256
11257
11258
11259
11260
11261int
11262lpfc_fof_queue_destroy(struct lpfc_hba *phba)
11263{
11264
11265 if (phba->sli4_hba.fof_eq != NULL) {
11266 lpfc_sli4_queue_free(phba->sli4_hba.fof_eq);
11267 phba->sli4_hba.fof_eq = NULL;
11268 }
11269
11270
11271 if (phba->sli4_hba.oas_cq != NULL) {
11272 lpfc_sli4_queue_free(phba->sli4_hba.oas_cq);
11273 phba->sli4_hba.oas_cq = NULL;
11274 }
11275
11276
11277 if (phba->sli4_hba.oas_wq != NULL) {
11278 lpfc_sli4_queue_free(phba->sli4_hba.oas_wq);
11279 phba->sli4_hba.oas_wq = NULL;
11280 }
11281 return 0;
11282}
11283
11284static struct pci_device_id lpfc_id_table[] = {
11285 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_VIPER,
11286 PCI_ANY_ID, PCI_ANY_ID, },
11287 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_FIREFLY,
11288 PCI_ANY_ID, PCI_ANY_ID, },
11289 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_THOR,
11290 PCI_ANY_ID, PCI_ANY_ID, },
11291 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_PEGASUS,
11292 PCI_ANY_ID, PCI_ANY_ID, },
11293 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_CENTAUR,
11294 PCI_ANY_ID, PCI_ANY_ID, },
11295 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_DRAGONFLY,
11296 PCI_ANY_ID, PCI_ANY_ID, },
11297 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SUPERFLY,
11298 PCI_ANY_ID, PCI_ANY_ID, },
11299 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_RFLY,
11300 PCI_ANY_ID, PCI_ANY_ID, },
11301 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_PFLY,
11302 PCI_ANY_ID, PCI_ANY_ID, },
11303 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_NEPTUNE,
11304 PCI_ANY_ID, PCI_ANY_ID, },
11305 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_NEPTUNE_SCSP,
11306 PCI_ANY_ID, PCI_ANY_ID, },
11307 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_NEPTUNE_DCSP,
11308 PCI_ANY_ID, PCI_ANY_ID, },
11309 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HELIOS,
11310 PCI_ANY_ID, PCI_ANY_ID, },
11311 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HELIOS_SCSP,
11312 PCI_ANY_ID, PCI_ANY_ID, },
11313 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HELIOS_DCSP,
11314 PCI_ANY_ID, PCI_ANY_ID, },
11315 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_BMID,
11316 PCI_ANY_ID, PCI_ANY_ID, },
11317 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_BSMB,
11318 PCI_ANY_ID, PCI_ANY_ID, },
11319 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR,
11320 PCI_ANY_ID, PCI_ANY_ID, },
11321 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HORNET,
11322 PCI_ANY_ID, PCI_ANY_ID, },
11323 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR_SCSP,
11324 PCI_ANY_ID, PCI_ANY_ID, },
11325 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR_DCSP,
11326 PCI_ANY_ID, PCI_ANY_ID, },
11327 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZMID,
11328 PCI_ANY_ID, PCI_ANY_ID, },
11329 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZSMB,
11330 PCI_ANY_ID, PCI_ANY_ID, },
11331 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_TFLY,
11332 PCI_ANY_ID, PCI_ANY_ID, },
11333 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LP101,
11334 PCI_ANY_ID, PCI_ANY_ID, },
11335 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LP10000S,
11336 PCI_ANY_ID, PCI_ANY_ID, },
11337 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LP11000S,
11338 PCI_ANY_ID, PCI_ANY_ID, },
11339 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LPE11000S,
11340 PCI_ANY_ID, PCI_ANY_ID, },
11341 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SAT,
11342 PCI_ANY_ID, PCI_ANY_ID, },
11343 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SAT_MID,
11344 PCI_ANY_ID, PCI_ANY_ID, },
11345 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SAT_SMB,
11346 PCI_ANY_ID, PCI_ANY_ID, },
11347 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SAT_DCSP,
11348 PCI_ANY_ID, PCI_ANY_ID, },
11349 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SAT_SCSP,
11350 PCI_ANY_ID, PCI_ANY_ID, },
11351 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SAT_S,
11352 PCI_ANY_ID, PCI_ANY_ID, },
11353 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_PROTEUS_VF,
11354 PCI_ANY_ID, PCI_ANY_ID, },
11355 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_PROTEUS_PF,
11356 PCI_ANY_ID, PCI_ANY_ID, },
11357 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_PROTEUS_S,
11358 PCI_ANY_ID, PCI_ANY_ID, },
11359 {PCI_VENDOR_ID_SERVERENGINE, PCI_DEVICE_ID_TIGERSHARK,
11360 PCI_ANY_ID, PCI_ANY_ID, },
11361 {PCI_VENDOR_ID_SERVERENGINE, PCI_DEVICE_ID_TOMCAT,
11362 PCI_ANY_ID, PCI_ANY_ID, },
11363 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_FALCON,
11364 PCI_ANY_ID, PCI_ANY_ID, },
11365 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_BALIUS,
11366 PCI_ANY_ID, PCI_ANY_ID, },
11367 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FC,
11368 PCI_ANY_ID, PCI_ANY_ID, },
11369 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FCOE,
11370 PCI_ANY_ID, PCI_ANY_ID, },
11371 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FC_VF,
11372 PCI_ANY_ID, PCI_ANY_ID, },
11373 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FCOE_VF,
11374 PCI_ANY_ID, PCI_ANY_ID, },
11375 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_G6_FC,
11376 PCI_ANY_ID, PCI_ANY_ID, },
11377 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SKYHAWK,
11378 PCI_ANY_ID, PCI_ANY_ID, },
11379 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SKYHAWK_VF,
11380 PCI_ANY_ID, PCI_ANY_ID, },
11381 { 0 }
11382};
11383
11384MODULE_DEVICE_TABLE(pci, lpfc_id_table);
11385
11386static const struct pci_error_handlers lpfc_err_handler = {
11387 .error_detected = lpfc_io_error_detected,
11388 .slot_reset = lpfc_io_slot_reset,
11389 .resume = lpfc_io_resume,
11390};
11391
11392static struct pci_driver lpfc_driver = {
11393 .name = LPFC_DRIVER_NAME,
11394 .id_table = lpfc_id_table,
11395 .probe = lpfc_pci_probe_one,
11396 .remove = lpfc_pci_remove_one,
11397 .suspend = lpfc_pci_suspend_one,
11398 .resume = lpfc_pci_resume_one,
11399 .err_handler = &lpfc_err_handler,
11400};
11401
11402static const struct file_operations lpfc_mgmt_fop = {
11403 .owner = THIS_MODULE,
11404};
11405
11406static struct miscdevice lpfc_mgmt_dev = {
11407 .minor = MISC_DYNAMIC_MINOR,
11408 .name = "lpfcmgmt",
11409 .fops = &lpfc_mgmt_fop,
11410};
11411
11412
11413
11414
11415
11416
11417
11418
11419
11420
11421
11422
11423
11424static int __init
11425lpfc_init(void)
11426{
11427 int cpu;
11428 int error = 0;
11429
11430 printk(LPFC_MODULE_DESC "\n");
11431 printk(LPFC_COPYRIGHT "\n");
11432
11433 error = misc_register(&lpfc_mgmt_dev);
11434 if (error)
11435 printk(KERN_ERR "Could not register lpfcmgmt device, "
11436 "misc_register returned with status %d", error);
11437
11438 if (lpfc_enable_npiv) {
11439 lpfc_transport_functions.vport_create = lpfc_vport_create;
11440 lpfc_transport_functions.vport_delete = lpfc_vport_delete;
11441 }
11442 lpfc_transport_template =
11443 fc_attach_transport(&lpfc_transport_functions);
11444 if (lpfc_transport_template == NULL)
11445 return -ENOMEM;
11446 if (lpfc_enable_npiv) {
11447 lpfc_vport_transport_template =
11448 fc_attach_transport(&lpfc_vport_transport_functions);
11449 if (lpfc_vport_transport_template == NULL) {
11450 fc_release_transport(lpfc_transport_template);
11451 return -ENOMEM;
11452 }
11453 }
11454
11455
11456 lpfc_used_cpu = NULL;
11457 lpfc_present_cpu = 0;
11458 for_each_present_cpu(cpu)
11459 lpfc_present_cpu++;
11460
11461 error = pci_register_driver(&lpfc_driver);
11462 if (error) {
11463 fc_release_transport(lpfc_transport_template);
11464 if (lpfc_enable_npiv)
11465 fc_release_transport(lpfc_vport_transport_template);
11466 }
11467
11468 return error;
11469}
11470
11471
11472
11473
11474
11475
11476
11477
11478static void __exit
11479lpfc_exit(void)
11480{
11481 misc_deregister(&lpfc_mgmt_dev);
11482 pci_unregister_driver(&lpfc_driver);
11483 fc_release_transport(lpfc_transport_template);
11484 if (lpfc_enable_npiv)
11485 fc_release_transport(lpfc_vport_transport_template);
11486 if (_dump_buf_data) {
11487 printk(KERN_ERR "9062 BLKGRD: freeing %lu pages for "
11488 "_dump_buf_data at 0x%p\n",
11489 (1L << _dump_buf_data_order), _dump_buf_data);
11490 free_pages((unsigned long)_dump_buf_data, _dump_buf_data_order);
11491 }
11492
11493 if (_dump_buf_dif) {
11494 printk(KERN_ERR "9049 BLKGRD: freeing %lu pages for "
11495 "_dump_buf_dif at 0x%p\n",
11496 (1L << _dump_buf_dif_order), _dump_buf_dif);
11497 free_pages((unsigned long)_dump_buf_dif, _dump_buf_dif_order);
11498 }
11499 kfree(lpfc_used_cpu);
11500 idr_destroy(&lpfc_hba_index);
11501}
11502
11503module_init(lpfc_init);
11504module_exit(lpfc_exit);
11505MODULE_LICENSE("GPL");
11506MODULE_DESCRIPTION(LPFC_MODULE_DESC);
11507MODULE_AUTHOR("Emulex Corporation - tech.support@emulex.com");
11508MODULE_VERSION("0:" LPFC_DRIVER_VERSION);
11509