1#ifndef __LINUX_UHCI_HCD_H
2#define __LINUX_UHCI_HCD_H
3
4#include <linux/list.h>
5#include <linux/usb.h>
6
7#define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
8#define PIPE_DEVEP_MASK 0x0007ff00
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15
16#define USBCMD 0
17#define USBCMD_RS 0x0001
18#define USBCMD_HCRESET 0x0002
19#define USBCMD_GRESET 0x0004
20#define USBCMD_EGSM 0x0008
21#define USBCMD_FGR 0x0010
22#define USBCMD_SWDBG 0x0020
23#define USBCMD_CF 0x0040
24#define USBCMD_MAXP 0x0080
25
26
27#define USBSTS 2
28#define USBSTS_USBINT 0x0001
29#define USBSTS_ERROR 0x0002
30#define USBSTS_RD 0x0004
31#define USBSTS_HSE 0x0008
32#define USBSTS_HCPE 0x0010
33
34#define USBSTS_HCH 0x0020
35
36
37#define USBINTR 4
38#define USBINTR_TIMEOUT 0x0001
39#define USBINTR_RESUME 0x0002
40#define USBINTR_IOC 0x0004
41#define USBINTR_SP 0x0008
42
43#define USBFRNUM 6
44#define USBFLBASEADD 8
45#define USBSOF 12
46#define USBSOF_DEFAULT 64
47
48
49#define USBPORTSC1 16
50#define USBPORTSC2 18
51#define USBPORTSC_CCS 0x0001
52
53#define USBPORTSC_CSC 0x0002
54#define USBPORTSC_PE 0x0004
55#define USBPORTSC_PEC 0x0008
56#define USBPORTSC_DPLUS 0x0010
57#define USBPORTSC_DMINUS 0x0020
58#define USBPORTSC_RD 0x0040
59#define USBPORTSC_RES1 0x0080
60#define USBPORTSC_LSDA 0x0100
61#define USBPORTSC_PR 0x0200
62
63#define USBPORTSC_OC 0x0400
64#define USBPORTSC_OCC 0x0800
65#define USBPORTSC_SUSP 0x1000
66#define USBPORTSC_RES2 0x2000
67#define USBPORTSC_RES3 0x4000
68#define USBPORTSC_RES4 0x8000
69
70
71#define USBLEGSUP 0xc0
72#define USBLEGSUP_DEFAULT 0x2000
73#define USBLEGSUP_RWC 0x8f00
74#define USBLEGSUP_RO 0x5040
75
76
77#define USBRES_INTEL 0xc4
78#define USBPORT1EN 0x01
79#define USBPORT2EN 0x02
80
81#define UHCI_PTR_BITS(uhci) cpu_to_hc32((uhci), 0x000F)
82#define UHCI_PTR_TERM(uhci) cpu_to_hc32((uhci), 0x0001)
83#define UHCI_PTR_QH(uhci) cpu_to_hc32((uhci), 0x0002)
84#define UHCI_PTR_DEPTH(uhci) cpu_to_hc32((uhci), 0x0004)
85#define UHCI_PTR_BREADTH(uhci) cpu_to_hc32((uhci), 0x0000)
86
87#define UHCI_NUMFRAMES 1024
88#define UHCI_MAX_SOF_NUMBER 2047
89#define CAN_SCHEDULE_FRAMES 1000
90
91#define MAX_PHASE 32
92
93
94
95#define FSBR_OFF_DELAY msecs_to_jiffies(10)
96
97
98#define QH_WAIT_TIMEOUT msecs_to_jiffies(200)
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108
109#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
110typedef __u32 __bitwise __hc32;
111typedef __u16 __bitwise __hc16;
112#else
113#define __hc32 __le32
114#define __hc16 __le16
115#endif
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140
141#define QH_STATE_IDLE 1
142#define QH_STATE_UNLINKING 2
143
144
145#define QH_STATE_ACTIVE 3
146
147struct uhci_qh {
148
149 __hc32 link;
150 __hc32 element;
151
152
153 dma_addr_t dma_handle;
154
155 struct list_head node;
156 struct usb_host_endpoint *hep;
157 struct usb_device *udev;
158 struct list_head queue;
159 struct uhci_td *dummy_td;
160 struct uhci_td *post_td;
161
162 struct usb_iso_packet_descriptor *iso_packet_desc;
163
164 unsigned long advance_jiffies;
165 unsigned int unlink_frame;
166 unsigned int period;
167 short phase;
168 short load;
169 unsigned int iso_frame;
170
171 int state;
172 int type;
173 int skel;
174
175 unsigned int initial_toggle:1;
176 unsigned int needs_fixup:1;
177 unsigned int is_stopped:1;
178 unsigned int wait_expired:1;
179 unsigned int bandwidth_reserved:1;
180
181} __attribute__((aligned(16)));
182
183
184
185
186
187#define qh_element(qh) ACCESS_ONCE((qh)->element)
188
189#define LINK_TO_QH(uhci, qh) (UHCI_PTR_QH((uhci)) | \
190 cpu_to_hc32((uhci), (qh)->dma_handle))
191
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199
200#define TD_CTRL_SPD (1 << 29)
201#define TD_CTRL_C_ERR_MASK (3 << 27)
202#define TD_CTRL_C_ERR_SHIFT 27
203#define TD_CTRL_LS (1 << 26)
204#define TD_CTRL_IOS (1 << 25)
205#define TD_CTRL_IOC (1 << 24)
206#define TD_CTRL_ACTIVE (1 << 23)
207#define TD_CTRL_STALLED (1 << 22)
208#define TD_CTRL_DBUFERR (1 << 21)
209#define TD_CTRL_BABBLE (1 << 20)
210#define TD_CTRL_NAK (1 << 19)
211#define TD_CTRL_CRCTIMEO (1 << 18)
212#define TD_CTRL_BITSTUFF (1 << 17)
213#define TD_CTRL_ACTLEN_MASK 0x7FF
214
215#define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT)
216#define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000)
217#define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \
218 TD_CTRL_ACTLEN_MASK)
219
220
221
222
223#define td_token(uhci, td) hc32_to_cpu((uhci), (td)->token)
224#define TD_TOKEN_DEVADDR_SHIFT 8
225#define TD_TOKEN_TOGGLE_SHIFT 19
226#define TD_TOKEN_TOGGLE (1 << 19)
227#define TD_TOKEN_EXPLEN_SHIFT 21
228#define TD_TOKEN_EXPLEN_MASK 0x7FF
229#define TD_TOKEN_PID_MASK 0xFF
230
231#define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
232 TD_TOKEN_EXPLEN_SHIFT)
233
234#define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
235 1) & TD_TOKEN_EXPLEN_MASK)
236#define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
237#define uhci_endpoint(token) (((token) >> 15) & 0xf)
238#define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
239#define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
240#define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK)
241#define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN)
242#define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN)
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253
254struct uhci_td {
255
256 __hc32 link;
257 __hc32 status;
258 __hc32 token;
259 __hc32 buffer;
260
261
262 dma_addr_t dma_handle;
263
264 struct list_head list;
265
266 int frame;
267 struct list_head fl_list;
268} __attribute__((aligned(16)));
269
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273
274#define td_status(uhci, td) hc32_to_cpu((uhci), \
275 ACCESS_ONCE((td)->status))
276
277#define LINK_TO_TD(uhci, td) (cpu_to_hc32((uhci), (td)->dma_handle))
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324
325#define UHCI_NUM_SKELQH 11
326#define SKEL_UNLINK 0
327#define skel_unlink_qh skelqh[SKEL_UNLINK]
328#define SKEL_ISO 1
329#define skel_iso_qh skelqh[SKEL_ISO]
330
331#define SKEL_INDEX(exponent) (9 - exponent)
332#define SKEL_ASYNC 9
333#define skel_async_qh skelqh[SKEL_ASYNC]
334#define SKEL_TERM 10
335#define skel_term_qh skelqh[SKEL_TERM]
336
337
338#define SKEL_LS_CONTROL 20
339#define SKEL_FS_CONTROL 21
340#define SKEL_FSBR SKEL_FS_CONTROL
341#define SKEL_BULK 22
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356
357enum uhci_rh_state {
358
359
360 UHCI_RH_RESET,
361 UHCI_RH_SUSPENDED,
362
363 UHCI_RH_AUTO_STOPPED,
364 UHCI_RH_RESUMING,
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367
368 UHCI_RH_SUSPENDING,
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371
372 UHCI_RH_RUNNING,
373 UHCI_RH_RUNNING_NODEVS,
374};
375
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378
379struct uhci_hcd {
380
381
382 struct dentry *dentry;
383
384
385 unsigned long io_addr;
386
387
388 void __iomem *regs;
389
390 struct dma_pool *qh_pool;
391 struct dma_pool *td_pool;
392
393 struct uhci_td *term_td;
394 struct uhci_qh *skelqh[UHCI_NUM_SKELQH];
395 struct uhci_qh *next_qh;
396
397 spinlock_t lock;
398
399 dma_addr_t frame_dma_handle;
400 __hc32 *frame;
401 void **frame_cpu;
402
403 enum uhci_rh_state rh_state;
404 unsigned long auto_stop_time;
405
406 unsigned int frame_number;
407 unsigned int is_stopped;
408#define UHCI_IS_STOPPED 9999
409 unsigned int last_iso_frame;
410 unsigned int cur_iso_frame;
411
412 unsigned int scan_in_progress:1;
413 unsigned int need_rescan:1;
414 unsigned int dead:1;
415 unsigned int RD_enable:1;
416
417
418 unsigned int is_initialized:1;
419 unsigned int fsbr_is_on:1;
420 unsigned int fsbr_is_wanted:1;
421 unsigned int fsbr_expiring:1;
422
423 struct timer_list fsbr_timer;
424
425
426 unsigned int oc_low:1;
427 unsigned int wait_for_hp:1;
428 unsigned int big_endian_mmio:1;
429 unsigned int big_endian_desc:1;
430
431
432 unsigned long port_c_suspend;
433 unsigned long resuming_ports;
434 unsigned long ports_timeout;
435
436 struct list_head idle_qh_list;
437
438 int rh_numports;
439
440 wait_queue_head_t waitqh;
441 int num_waiting;
442
443 int total_load;
444 short load[MAX_PHASE];
445
446
447 void (*reset_hc) (struct uhci_hcd *uhci);
448 int (*check_and_reset_hc) (struct uhci_hcd *uhci);
449
450 void (*configure_hc) (struct uhci_hcd *uhci);
451
452 int (*resume_detect_interrupts_are_broken) (struct uhci_hcd *uhci);
453
454 int (*global_suspend_mode_is_broken) (struct uhci_hcd *uhci);
455};
456
457
458static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
459{
460 return (struct uhci_hcd *) (hcd->hcd_priv);
461}
462static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
463{
464 return container_of((void *) uhci, struct usb_hcd, hcd_priv);
465}
466
467#define uhci_dev(u) (uhci_to_hcd(u)->self.controller)
468
469
470#define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1)))
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474
475
476struct urb_priv {
477 struct list_head node;
478
479 struct urb *urb;
480
481 struct uhci_qh *qh;
482 struct list_head td_list;
483
484 unsigned fsbr:1;
485};
486
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489
490#define PCI_VENDOR_ID_GENESYS 0x17a0
491#define PCI_DEVICE_ID_GL880S_UHCI 0x8083
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498
499#ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC
500
501static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
502{
503 return inl(uhci->io_addr + reg);
504}
505
506static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
507{
508 outl(val, uhci->io_addr + reg);
509}
510
511static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
512{
513 return inw(uhci->io_addr + reg);
514}
515
516static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
517{
518 outw(val, uhci->io_addr + reg);
519}
520
521static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
522{
523 return inb(uhci->io_addr + reg);
524}
525
526static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
527{
528 outb(val, uhci->io_addr + reg);
529}
530
531#else
532
533#ifdef CONFIG_PCI
534
535#define uhci_has_pci_registers(u) ((u)->io_addr != 0)
536#else
537
538#define uhci_has_pci_registers(u) 0
539#endif
540
541#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
542
543#define uhci_big_endian_mmio(u) ((u)->big_endian_mmio)
544#else
545#define uhci_big_endian_mmio(u) 0
546#endif
547
548static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
549{
550 if (uhci_has_pci_registers(uhci))
551 return inl(uhci->io_addr + reg);
552#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
553 else if (uhci_big_endian_mmio(uhci))
554 return readl_be(uhci->regs + reg);
555#endif
556 else
557 return readl(uhci->regs + reg);
558}
559
560static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
561{
562 if (uhci_has_pci_registers(uhci))
563 outl(val, uhci->io_addr + reg);
564#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
565 else if (uhci_big_endian_mmio(uhci))
566 writel_be(val, uhci->regs + reg);
567#endif
568 else
569 writel(val, uhci->regs + reg);
570}
571
572static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
573{
574 if (uhci_has_pci_registers(uhci))
575 return inw(uhci->io_addr + reg);
576#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
577 else if (uhci_big_endian_mmio(uhci))
578 return readw_be(uhci->regs + reg);
579#endif
580 else
581 return readw(uhci->regs + reg);
582}
583
584static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
585{
586 if (uhci_has_pci_registers(uhci))
587 outw(val, uhci->io_addr + reg);
588#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
589 else if (uhci_big_endian_mmio(uhci))
590 writew_be(val, uhci->regs + reg);
591#endif
592 else
593 writew(val, uhci->regs + reg);
594}
595
596static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
597{
598 if (uhci_has_pci_registers(uhci))
599 return inb(uhci->io_addr + reg);
600#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
601 else if (uhci_big_endian_mmio(uhci))
602 return readb_be(uhci->regs + reg);
603#endif
604 else
605 return readb(uhci->regs + reg);
606}
607
608static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
609{
610 if (uhci_has_pci_registers(uhci))
611 outb(val, uhci->io_addr + reg);
612#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
613 else if (uhci_big_endian_mmio(uhci))
614 writeb_be(val, uhci->regs + reg);
615#endif
616 else
617 writeb(val, uhci->regs + reg);
618}
619#endif
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626
627#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
628#define uhci_big_endian_desc(u) ((u)->big_endian_desc)
629
630
631static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
632{
633 return uhci_big_endian_desc(uhci)
634 ? (__force __hc32)cpu_to_be32(x)
635 : (__force __hc32)cpu_to_le32(x);
636}
637
638
639static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
640{
641 return uhci_big_endian_desc(uhci)
642 ? be32_to_cpu((__force __be32)x)
643 : le32_to_cpu((__force __le32)x);
644}
645
646#else
647
648static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
649{
650 return cpu_to_le32(x);
651}
652
653
654static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
655{
656 return le32_to_cpu(x);
657}
658#endif
659
660#endif
661