LXR linux/include/media/i2c/adv7842.h

   1/*
   2 * adv7842 - Analog Devices ADV7842 video decoder driver
   3 *
   4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5 *
   6 * This program is free software; you may redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; version 2 of the License.
   9 *
  10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17 * SOFTWARE.
  18 *
  19 */
  20
  21#ifndef _ADV7842_
  22#define _ADV7842_
  23
  24/* Analog input muxing modes (AFE register 0x02, [2:0]) */
  25enum adv7842_ain_sel {
  26        ADV7842_AIN1_2_3_NC_SYNC_1_2 = 0,
  27        ADV7842_AIN4_5_6_NC_SYNC_2_1 = 1,
  28        ADV7842_AIN7_8_9_NC_SYNC_3_1 = 2,
  29        ADV7842_AIN10_11_12_NC_SYNC_4_1 = 3,
  30        ADV7842_AIN9_4_5_6_SYNC_2_1 = 4,
  31};
  32
  33/*
  34 * Bus rotation and reordering. This is used to specify component reordering on
  35 * the board and describes the components order on the bus when the ADV7842
  36 * outputs RGB.
  37 */
  38enum adv7842_bus_order {
  39        ADV7842_BUS_ORDER_RGB,          /* No operation */
  40        ADV7842_BUS_ORDER_GRB,          /* Swap 1-2     */
  41        ADV7842_BUS_ORDER_RBG,          /* Swap 2-3     */
  42        ADV7842_BUS_ORDER_BGR,          /* Swap 1-3     */
  43        ADV7842_BUS_ORDER_BRG,          /* Rotate right */
  44        ADV7842_BUS_ORDER_GBR,          /* Rotate left  */
  45};
  46
  47/* Input Color Space (IO register 0x02, [7:4]) */
  48enum adv7842_inp_color_space {
  49        ADV7842_INP_COLOR_SPACE_LIM_RGB = 0,
  50        ADV7842_INP_COLOR_SPACE_FULL_RGB = 1,
  51        ADV7842_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
  52        ADV7842_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
  53        ADV7842_INP_COLOR_SPACE_XVYCC_601 = 4,
  54        ADV7842_INP_COLOR_SPACE_XVYCC_709 = 5,
  55        ADV7842_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
  56        ADV7842_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
  57        ADV7842_INP_COLOR_SPACE_AUTO = 0xf,
  58};
  59
  60/* Select output format (IO register 0x03, [4:2]) */
  61enum adv7842_op_format_mode_sel {
  62        ADV7842_OP_FORMAT_MODE0 = 0x00,
  63        ADV7842_OP_FORMAT_MODE1 = 0x04,
  64        ADV7842_OP_FORMAT_MODE2 = 0x08,
  65};
  66
  67/* Mode of operation */
  68enum adv7842_mode {
  69        ADV7842_MODE_SDP,
  70        ADV7842_MODE_COMP,
  71        ADV7842_MODE_RGB,
  72        ADV7842_MODE_HDMI
  73};
  74
  75/* Video standard select (IO register 0x00, [5:0]) */
  76enum adv7842_vid_std_select {
  77        /* SDP */
  78        ADV7842_SDP_VID_STD_CVBS_SD_4x1 = 0x01,
  79        ADV7842_SDP_VID_STD_YC_SD4_x1 = 0x09,
  80        /* RGB */
  81        ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE = 0x07,
  82        /* HDMI GR */
  83        ADV7842_HDMI_GR_VID_STD_AUTO_GRAPH_MODE = 0x02,
  84        /* HDMI COMP */
  85        ADV7842_HDMI_COMP_VID_STD_HD_1250P = 0x1e,
  86};
  87
  88enum adv7842_select_input {
  89        ADV7842_SELECT_HDMI_PORT_A,
  90        ADV7842_SELECT_HDMI_PORT_B,
  91        ADV7842_SELECT_VGA_RGB,
  92        ADV7842_SELECT_VGA_COMP,
  93        ADV7842_SELECT_SDP_CVBS,
  94        ADV7842_SELECT_SDP_YC,
  95};
  96
  97enum adv7842_drive_strength {
  98        ADV7842_DR_STR_LOW = 0,
  99        ADV7842_DR_STR_MEDIUM_LOW = 1,
 100        ADV7842_DR_STR_MEDIUM_HIGH = 2,
 101        ADV7842_DR_STR_HIGH = 3,
 102};
 103
 104struct adv7842_sdp_csc_coeff {
 105        bool manual;
 106        u16 scaling;
 107        u16 A1;
 108        u16 A2;
 109        u16 A3;
 110        u16 A4;
 111        u16 B1;
 112        u16 B2;
 113        u16 B3;
 114        u16 B4;
 115        u16 C1;
 116        u16 C2;
 117        u16 C3;
 118        u16 C4;
 119};
 120
 121struct adv7842_sdp_io_sync_adjustment {
 122        bool adjust;
 123        u16 hs_beg;
 124        u16 hs_width;
 125        u16 de_beg;
 126        u16 de_end;
 127        u8 vs_beg_o;
 128        u8 vs_beg_e;
 129        u8 vs_end_o;
 130        u8 vs_end_e;
 131        u8 de_v_beg_o;
 132        u8 de_v_beg_e;
 133        u8 de_v_end_o;
 134        u8 de_v_end_e;
 135};
 136
 137/* Platform dependent definition */
 138struct adv7842_platform_data {
 139        /* chip reset during probe */
 140        unsigned chip_reset:1;
 141
 142        /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
 143        unsigned disable_pwrdnb:1;
 144
 145        /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
 146        unsigned disable_cable_det_rst:1;
 147
 148        /* Analog input muxing mode */
 149        enum adv7842_ain_sel ain_sel;
 150
 151        /* Bus rotation and reordering */
 152        enum adv7842_bus_order bus_order;
 153
 154        /* Select output format mode */
 155        enum adv7842_op_format_mode_sel op_format_mode_sel;
 156
 157        /* Default mode */
 158        enum adv7842_mode mode;
 159
 160        /* Default input */
 161        unsigned input;
 162
 163        /* Video standard */
 164        enum adv7842_vid_std_select vid_std_select;
 165
 166        /* IO register 0x02 */
 167        unsigned alt_gamma:1;
 168        unsigned op_656_range:1;
 169        unsigned alt_data_sat:1;
 170
 171        /* IO register 0x05 */
 172        unsigned blank_data:1;
 173        unsigned insert_av_codes:1;
 174        unsigned replicate_av_codes:1;
 175
 176        /* IO register 0x30 */
 177        unsigned output_bus_lsb_to_msb:1;
 178
 179        /* IO register 0x14 */
 180        enum adv7842_drive_strength dr_str_data;
 181        enum adv7842_drive_strength dr_str_clk;
 182        enum adv7842_drive_strength dr_str_sync;
 183
 184        /*
 185         * IO register 0x19: Adjustment to the LLC DLL phase in
 186         * increments of 1/32 of a clock period.
 187         */
 188        unsigned llc_dll_phase:5;
 189
 190        /* External RAM for 3-D comb or frame synchronizer */
 191        unsigned sd_ram_size; /* ram size in MB */
 192        unsigned sd_ram_ddr:1; /* ddr or sdr sdram */
 193
 194        /* HDMI free run, CP-reg 0xBA */
 195        unsigned hdmi_free_run_enable:1;
 196        /* 0 = Mode 0: run when there is no TMDS clock
 197           1 = Mode 1: run when there is no TMDS clock or the
 198               video resolution does not match programmed one. */
 199        unsigned hdmi_free_run_mode:1;
 200
 201        /* SDP free run, CP-reg 0xDD */
 202        unsigned sdp_free_run_auto:1;
 203        unsigned sdp_free_run_man_col_en:1;
 204        unsigned sdp_free_run_cbar_en:1;
 205        unsigned sdp_free_run_force:1;
 206
 207        /* HPA manual (0) or auto (1), affects HDMI register 0x69 */
 208        unsigned hpa_auto:1;
 209
 210        struct adv7842_sdp_csc_coeff sdp_csc_coeff;
 211
 212        struct adv7842_sdp_io_sync_adjustment sdp_io_sync_625;
 213        struct adv7842_sdp_io_sync_adjustment sdp_io_sync_525;
 214
 215        /* i2c addresses */
 216        u8 i2c_sdp_io;
 217        u8 i2c_sdp;
 218        u8 i2c_cp;
 219        u8 i2c_vdp;
 220        u8 i2c_afe;
 221        u8 i2c_hdmi;
 222        u8 i2c_repeater;
 223        u8 i2c_edid;
 224        u8 i2c_infoframe;
 225        u8 i2c_cec;
 226        u8 i2c_avlink;
 227};
 228
 229#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE   (V4L2_CID_DV_CLASS_BASE + 0x1000)
 230#define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL   (V4L2_CID_DV_CLASS_BASE + 0x1001)
 231#define V4L2_CID_ADV_RX_FREE_RUN_COLOR          (V4L2_CID_DV_CLASS_BASE + 0x1002)
 232
 233/* custom ioctl, used to test the external RAM that's used by the
 234 * deinterlacer. */
 235#define ADV7842_CMD_RAM_TEST _IO('V', BASE_VIDIOC_PRIVATE)
 236
 237#define ADV7842_EDID_PORT_A   0
 238#define ADV7842_EDID_PORT_B   1
 239#define ADV7842_EDID_PORT_VGA 2
 240#define ADV7842_PAD_SOURCE    3
 241
 242#endif
 243