LXR linux/include/soc/fsl/qe/qe.h

   1/*
   2 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
   3 *
   4 * Authors:     Shlomi Gridish <gridish@freescale.com>
   5 *              Li Yang <leoli@freescale.com>
   6 *
   7 * Description:
   8 * QUICC Engine (QE) external definitions and structure.
   9 *
  10 * This program is free software; you can redistribute  it and/or modify it
  11 * under  the terms of  the GNU General  Public License as published by the
  12 * Free Software Foundation;  either version 2 of the  License, or (at your
  13 * option) any later version.
  14 */
  15#ifndef _ASM_POWERPC_QE_H
  16#define _ASM_POWERPC_QE_H
  17#ifdef __KERNEL__
  18
  19#include <linux/compiler.h>
  20#include <linux/genalloc.h>
  21#include <linux/spinlock.h>
  22#include <linux/errno.h>
  23#include <linux/err.h>
  24#include <asm/cpm.h>
  25#include <soc/fsl/qe/immap_qe.h>
  26#include <linux/of.h>
  27#include <linux/of_address.h>
  28#include <linux/types.h>
  29
  30#define QE_NUM_OF_SNUM  256     /* There are 256 serial number in QE */
  31#define QE_NUM_OF_BRGS  16
  32#define QE_NUM_OF_PORTS 1024
  33
  34/* Memory partitions
  35*/
  36#define MEM_PART_SYSTEM         0
  37#define MEM_PART_SECONDARY      1
  38#define MEM_PART_MURAM          2
  39
  40/* Clocks and BRGs */
  41enum qe_clock {
  42        QE_CLK_NONE = 0,
  43        QE_BRG1,                /* Baud Rate Generator 1 */
  44        QE_BRG2,                /* Baud Rate Generator 2 */
  45        QE_BRG3,                /* Baud Rate Generator 3 */
  46        QE_BRG4,                /* Baud Rate Generator 4 */
  47        QE_BRG5,                /* Baud Rate Generator 5 */
  48        QE_BRG6,                /* Baud Rate Generator 6 */
  49        QE_BRG7,                /* Baud Rate Generator 7 */
  50        QE_BRG8,                /* Baud Rate Generator 8 */
  51        QE_BRG9,                /* Baud Rate Generator 9 */
  52        QE_BRG10,               /* Baud Rate Generator 10 */
  53        QE_BRG11,               /* Baud Rate Generator 11 */
  54        QE_BRG12,               /* Baud Rate Generator 12 */
  55        QE_BRG13,               /* Baud Rate Generator 13 */
  56        QE_BRG14,               /* Baud Rate Generator 14 */
  57        QE_BRG15,               /* Baud Rate Generator 15 */
  58        QE_BRG16,               /* Baud Rate Generator 16 */
  59        QE_CLK1,                /* Clock 1 */
  60        QE_CLK2,                /* Clock 2 */
  61        QE_CLK3,                /* Clock 3 */
  62        QE_CLK4,                /* Clock 4 */
  63        QE_CLK5,                /* Clock 5 */
  64        QE_CLK6,                /* Clock 6 */
  65        QE_CLK7,                /* Clock 7 */
  66        QE_CLK8,                /* Clock 8 */
  67        QE_CLK9,                /* Clock 9 */
  68        QE_CLK10,               /* Clock 10 */
  69        QE_CLK11,               /* Clock 11 */
  70        QE_CLK12,               /* Clock 12 */
  71        QE_CLK13,               /* Clock 13 */
  72        QE_CLK14,               /* Clock 14 */
  73        QE_CLK15,               /* Clock 15 */
  74        QE_CLK16,               /* Clock 16 */
  75        QE_CLK17,               /* Clock 17 */
  76        QE_CLK18,               /* Clock 18 */
  77        QE_CLK19,               /* Clock 19 */
  78        QE_CLK20,               /* Clock 20 */
  79        QE_CLK21,               /* Clock 21 */
  80        QE_CLK22,               /* Clock 22 */
  81        QE_CLK23,               /* Clock 23 */
  82        QE_CLK24,               /* Clock 24 */
  83        QE_CLK_DUMMY
  84};
  85
  86static inline bool qe_clock_is_brg(enum qe_clock clk)
  87{
  88        return clk >= QE_BRG1 && clk <= QE_BRG16;
  89}
  90
  91extern spinlock_t cmxgcr_lock;
  92
  93/* Export QE common operations */
  94#ifdef CONFIG_QUICC_ENGINE
  95extern void qe_reset(void);
  96#else
  97static inline void qe_reset(void) {}
  98#endif
  99
 100int cpm_muram_init(void);
 101
 102#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
 103unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
 104int cpm_muram_free(unsigned long offset);
 105unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
 106void __iomem *cpm_muram_addr(unsigned long offset);
 107unsigned long cpm_muram_offset(void __iomem *addr);
 108dma_addr_t cpm_muram_dma(void __iomem *addr);
 109#else
 110static inline unsigned long cpm_muram_alloc(unsigned long size,
 111                                            unsigned long align)
 112{
 113        return -ENOSYS;
 114}
 115
 116static inline int cpm_muram_free(unsigned long offset)
 117{
 118        return -ENOSYS;
 119}
 120
 121static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset,
 122                                                  unsigned long size)
 123{
 124        return -ENOSYS;
 125}
 126
 127static inline void __iomem *cpm_muram_addr(unsigned long offset)
 128{
 129        return NULL;
 130}
 131
 132static inline unsigned long cpm_muram_offset(void __iomem *addr)
 133{
 134        return -ENOSYS;
 135}
 136
 137static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
 138{
 139        return 0;
 140}
 141#endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */
 142
 143/* QE PIO */
 144#define QE_PIO_PINS 32
 145
 146struct qe_pio_regs {
 147        __be32  cpodr;          /* Open drain register */
 148        __be32  cpdata;         /* Data register */
 149        __be32  cpdir1;         /* Direction register */
 150        __be32  cpdir2;         /* Direction register */
 151        __be32  cppar1;         /* Pin assignment register */
 152        __be32  cppar2;         /* Pin assignment register */
 153#ifdef CONFIG_PPC_85xx
 154        u8      pad[8];
 155#endif
 156};
 157
 158#define QE_PIO_DIR_IN   2
 159#define QE_PIO_DIR_OUT  1
 160extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
 161                                int dir, int open_drain, int assignment,
 162                                int has_irq);
 163#ifdef CONFIG_QUICC_ENGINE
 164extern int par_io_init(struct device_node *np);
 165extern int par_io_of_config(struct device_node *np);
 166extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
 167                             int assignment, int has_irq);
 168extern int par_io_data_set(u8 port, u8 pin, u8 val);
 169#else
 170static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
 171static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
 172static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
 173                int assignment, int has_irq) { return -ENOSYS; }
 174static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
 175#endif /* CONFIG_QUICC_ENGINE */
 176
 177/*
 178 * Pin multiplexing functions.
 179 */
 180struct qe_pin;
 181#ifdef CONFIG_QE_GPIO
 182extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
 183extern void qe_pin_free(struct qe_pin *qe_pin);
 184extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
 185extern void qe_pin_set_dedicated(struct qe_pin *pin);
 186#else
 187static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
 188{
 189        return ERR_PTR(-ENOSYS);
 190}
 191static inline void qe_pin_free(struct qe_pin *qe_pin) {}
 192static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
 193static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
 194#endif /* CONFIG_QE_GPIO */
 195
 196#ifdef CONFIG_QUICC_ENGINE
 197int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
 198#else
 199static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
 200                               u32 cmd_input)
 201{
 202        return -ENOSYS;
 203}
 204#endif /* CONFIG_QUICC_ENGINE */
 205
 206/* QE internal API */
 207enum qe_clock qe_clock_source(const char *source);
 208unsigned int qe_get_brg_clk(void);
 209int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
 210int qe_get_snum(void);
 211void qe_put_snum(u8 snum);
 212unsigned int qe_get_num_of_risc(void);
 213unsigned int qe_get_num_of_snums(void);
 214
 215static inline int qe_alive_during_sleep(void)
 216{
 217        /*
 218         * MPC8568E reference manual says:
 219         *
 220         * "...power down sequence waits for all I/O interfaces to become idle.
 221         *  In some applications this may happen eventually without actively
 222         *  shutting down interfaces, but most likely, software will have to
 223         *  take steps to shut down the eTSEC, QUICC Engine Block, and PCI
 224         *  interfaces before issuing the command (either the write to the core
 225         *  MSR[WE] as described above or writing to POWMGTCSR) to put the
 226         *  device into sleep state."
 227         *
 228         * MPC8569E reference manual has a similar paragraph.
 229         */
 230#ifdef CONFIG_PPC_85xx
 231        return 0;
 232#else
 233        return 1;
 234#endif
 235}
 236
 237/* we actually use cpm_muram implementation, define this for convenience */
 238#define qe_muram_init cpm_muram_init
 239#define qe_muram_alloc cpm_muram_alloc
 240#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
 241#define qe_muram_free cpm_muram_free
 242#define qe_muram_addr cpm_muram_addr
 243#define qe_muram_offset cpm_muram_offset
 244
 245/* Structure that defines QE firmware binary files.
 246 *
 247 * See Documentation/powerpc/qe_firmware.txt for a description of these
 248 * fields.
 249 */
 250struct qe_firmware {
 251        struct qe_header {
 252                __be32 length;  /* Length of the entire structure, in bytes */
 253                u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
 254                u8 version;     /* Version of this layout. First ver is '1' */
 255        } header;
 256        u8 id[62];      /* Null-terminated identifier string */
 257        u8 split;       /* 0 = shared I-RAM, 1 = split I-RAM */
 258        u8 count;       /* Number of microcode[] structures */
 259        struct {
 260                __be16 model;           /* The SOC model  */
 261                u8 major;               /* The SOC revision major */
 262                u8 minor;               /* The SOC revision minor */
 263        } __attribute__ ((packed)) soc;
 264        u8 padding[4];                  /* Reserved, for alignment */
 265        __be64 extended_modes;          /* Extended modes */
 266        __be32 vtraps[8];               /* Virtual trap addresses */
 267        u8 reserved[4];                 /* Reserved, for future expansion */
 268        struct qe_microcode {
 269                u8 id[32];              /* Null-terminated identifier */
 270                __be32 traps[16];       /* Trap addresses, 0 == ignore */
 271                __be32 eccr;            /* The value for the ECCR register */
 272                __be32 iram_offset;     /* Offset into I-RAM for the code */
 273                __be32 count;           /* Number of 32-bit words of the code */
 274                __be32 code_offset;     /* Offset of the actual microcode */
 275                u8 major;               /* The microcode version major */
 276                u8 minor;               /* The microcode version minor */
 277                u8 revision;            /* The microcode version revision */
 278                u8 padding;             /* Reserved, for alignment */
 279                u8 reserved[4];         /* Reserved, for future expansion */
 280        } __attribute__ ((packed)) microcode[1];
 281        /* All microcode binaries should be located here */
 282        /* CRC32 should be located here, after the microcode binaries */
 283} __attribute__ ((packed));
 284
 285struct qe_firmware_info {
 286        char id[64];            /* Firmware name */
 287        u32 vtraps[8];          /* Virtual trap addresses */
 288        u64 extended_modes;     /* Extended modes */
 289};
 290
 291#ifdef CONFIG_QUICC_ENGINE
 292/* Upload a firmware to the QE */
 293int qe_upload_firmware(const struct qe_firmware *firmware);
 294#else
 295static inline int qe_upload_firmware(const struct qe_firmware *firmware)
 296{
 297        return -ENOSYS;
 298}
 299#endif /* CONFIG_QUICC_ENGINE */
 300
 301/* Obtain information on the uploaded firmware */
 302struct qe_firmware_info *qe_get_firmware_info(void);
 303
 304/* QE USB */
 305int qe_usb_clock_set(enum qe_clock clk, int rate);
 306
 307/* Buffer descriptors */
 308struct qe_bd {
 309        __be16 status;
 310        __be16 length;
 311        __be32 buf;
 312} __attribute__ ((packed));
 313
 314#define BD_STATUS_MASK  0xffff0000
 315#define BD_LENGTH_MASK  0x0000ffff
 316
 317/* Alignment */
 318#define QE_INTR_TABLE_ALIGN     16      /* ??? */
 319#define QE_ALIGNMENT_OF_BD      8
 320#define QE_ALIGNMENT_OF_PRAM    64
 321
 322/* RISC allocation */
 323#define QE_RISC_ALLOCATION_RISC1        0x1  /* RISC 1 */
 324#define QE_RISC_ALLOCATION_RISC2        0x2  /* RISC 2 */
 325#define QE_RISC_ALLOCATION_RISC3        0x4  /* RISC 3 */
 326#define QE_RISC_ALLOCATION_RISC4        0x8  /* RISC 4 */
 327#define QE_RISC_ALLOCATION_RISC1_AND_RISC2      (QE_RISC_ALLOCATION_RISC1 | \
 328                                                 QE_RISC_ALLOCATION_RISC2)
 329#define QE_RISC_ALLOCATION_FOUR_RISCS   (QE_RISC_ALLOCATION_RISC1 | \
 330                                         QE_RISC_ALLOCATION_RISC2 | \
 331                                         QE_RISC_ALLOCATION_RISC3 | \
 332                                         QE_RISC_ALLOCATION_RISC4)
 333
 334/* QE extended filtering Table Lookup Key Size */
 335enum qe_fltr_tbl_lookup_key_size {
 336        QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
 337                = 0x3f,         /* LookupKey parsed by the Generate LookupKey
 338                                   CMD is truncated to 8 bytes */
 339        QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
 340                = 0x5f,         /* LookupKey parsed by the Generate LookupKey
 341                                   CMD is truncated to 16 bytes */
 342};
 343
 344/* QE FLTR extended filtering Largest External Table Lookup Key Size */
 345enum qe_fltr_largest_external_tbl_lookup_key_size {
 346        QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
 347                = 0x0,/* not used */
 348        QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
 349                = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES,        /* 8 bytes */
 350        QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
 351                = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES,       /* 16 bytes */
 352};
 353
 354/* structure representing QE parameter RAM */
 355struct qe_timer_tables {
 356        u16 tm_base;            /* QE timer table base adr */
 357        u16 tm_ptr;             /* QE timer table pointer */
 358        u16 r_tmr;              /* QE timer mode register */
 359        u16 r_tmv;              /* QE timer valid register */
 360        u32 tm_cmd;             /* QE timer cmd register */
 361        u32 tm_cnt;             /* QE timer internal cnt */
 362} __attribute__ ((packed));
 363
 364#define QE_FLTR_TAD_SIZE        8
 365
 366/* QE extended filtering Termination Action Descriptor (TAD) */
 367struct qe_fltr_tad {
 368        u8 serialized[QE_FLTR_TAD_SIZE];
 369} __attribute__ ((packed));
 370
 371/* Communication Direction */
 372enum comm_dir {
 373        COMM_DIR_NONE = 0,
 374        COMM_DIR_RX = 1,
 375        COMM_DIR_TX = 2,
 376        COMM_DIR_RX_AND_TX = 3
 377};
 378
 379/* QE CMXUCR Registers.
 380 * There are two UCCs represented in each of the four CMXUCR registers.
 381 * These values are for the UCC in the LSBs
 382 */
 383#define QE_CMXUCR_MII_ENET_MNG          0x00007000
 384#define QE_CMXUCR_MII_ENET_MNG_SHIFT    12
 385#define QE_CMXUCR_GRANT                 0x00008000
 386#define QE_CMXUCR_TSA                   0x00004000
 387#define QE_CMXUCR_BKPT                  0x00000100
 388#define QE_CMXUCR_TX_CLK_SRC_MASK       0x0000000F
 389
 390/* QE CMXGCR Registers.
 391*/
 392#define QE_CMXGCR_MII_ENET_MNG          0x00007000
 393#define QE_CMXGCR_MII_ENET_MNG_SHIFT    12
 394#define QE_CMXGCR_USBCS                 0x0000000f
 395#define QE_CMXGCR_USBCS_CLK3            0x1
 396#define QE_CMXGCR_USBCS_CLK5            0x2
 397#define QE_CMXGCR_USBCS_CLK7            0x3
 398#define QE_CMXGCR_USBCS_CLK9            0x4
 399#define QE_CMXGCR_USBCS_CLK13           0x5
 400#define QE_CMXGCR_USBCS_CLK17           0x6
 401#define QE_CMXGCR_USBCS_CLK19           0x7
 402#define QE_CMXGCR_USBCS_CLK21           0x8
 403#define QE_CMXGCR_USBCS_BRG9            0x9
 404#define QE_CMXGCR_USBCS_BRG10           0xa
 405
 406/* QE CECR Commands.
 407*/
 408#define QE_CR_FLG                       0x00010000
 409#define QE_RESET                        0x80000000
 410#define QE_INIT_TX_RX                   0x00000000
 411#define QE_INIT_RX                      0x00000001
 412#define QE_INIT_TX                      0x00000002
 413#define QE_ENTER_HUNT_MODE              0x00000003
 414#define QE_STOP_TX                      0x00000004
 415#define QE_GRACEFUL_STOP_TX             0x00000005
 416#define QE_RESTART_TX                   0x00000006
 417#define QE_CLOSE_RX_BD                  0x00000007
 418#define QE_SWITCH_COMMAND               0x00000007
 419#define QE_SET_GROUP_ADDRESS            0x00000008
 420#define QE_START_IDMA                   0x00000009
 421#define QE_MCC_STOP_RX                  0x00000009
 422#define QE_ATM_TRANSMIT                 0x0000000a
 423#define QE_HPAC_CLEAR_ALL               0x0000000b
 424#define QE_GRACEFUL_STOP_RX             0x0000001a
 425#define QE_RESTART_RX                   0x0000001b
 426#define QE_HPAC_SET_PRIORITY            0x0000010b
 427#define QE_HPAC_STOP_TX                 0x0000020b
 428#define QE_HPAC_STOP_RX                 0x0000030b
 429#define QE_HPAC_GRACEFUL_STOP_TX        0x0000040b
 430#define QE_HPAC_GRACEFUL_STOP_RX        0x0000050b
 431#define QE_HPAC_START_TX                0x0000060b
 432#define QE_HPAC_START_RX                0x0000070b
 433#define QE_USB_STOP_TX                  0x0000000a
 434#define QE_USB_RESTART_TX               0x0000000c
 435#define QE_QMC_STOP_TX                  0x0000000c
 436#define QE_QMC_STOP_RX                  0x0000000d
 437#define QE_SS7_SU_FIL_RESET             0x0000000e
 438/* jonathbr added from here down for 83xx */
 439#define QE_RESET_BCS                    0x0000000a
 440#define QE_MCC_INIT_TX_RX_16            0x00000003
 441#define QE_MCC_STOP_TX                  0x00000004
 442#define QE_MCC_INIT_TX_1                0x00000005
 443#define QE_MCC_INIT_RX_1                0x00000006
 444#define QE_MCC_RESET                    0x00000007
 445#define QE_SET_TIMER                    0x00000008
 446#define QE_RANDOM_NUMBER                0x0000000c
 447#define QE_ATM_MULTI_THREAD_INIT        0x00000011
 448#define QE_ASSIGN_PAGE                  0x00000012
 449#define QE_ADD_REMOVE_HASH_ENTRY        0x00000013
 450#define QE_START_FLOW_CONTROL           0x00000014
 451#define QE_STOP_FLOW_CONTROL            0x00000015
 452#define QE_ASSIGN_PAGE_TO_DEVICE        0x00000016
 453
 454#define QE_ASSIGN_RISC                  0x00000010
 455#define QE_CR_MCN_NORMAL_SHIFT          6
 456#define QE_CR_MCN_USB_SHIFT             4
 457#define QE_CR_MCN_RISC_ASSIGN_SHIFT     8
 458#define QE_CR_SNUM_SHIFT                17
 459
 460/* QE CECR Sub Block - sub block of QE command.
 461*/
 462#define QE_CR_SUBBLOCK_INVALID          0x00000000
 463#define QE_CR_SUBBLOCK_USB              0x03200000
 464#define QE_CR_SUBBLOCK_UCCFAST1         0x02000000
 465#define QE_CR_SUBBLOCK_UCCFAST2         0x02200000
 466#define QE_CR_SUBBLOCK_UCCFAST3         0x02400000
 467#define QE_CR_SUBBLOCK_UCCFAST4         0x02600000
 468#define QE_CR_SUBBLOCK_UCCFAST5         0x02800000
 469#define QE_CR_SUBBLOCK_UCCFAST6         0x02a00000
 470#define QE_CR_SUBBLOCK_UCCFAST7         0x02c00000
 471#define QE_CR_SUBBLOCK_UCCFAST8         0x02e00000
 472#define QE_CR_SUBBLOCK_UCCSLOW1         0x00000000
 473#define QE_CR_SUBBLOCK_UCCSLOW2         0x00200000
 474#define QE_CR_SUBBLOCK_UCCSLOW3         0x00400000
 475#define QE_CR_SUBBLOCK_UCCSLOW4         0x00600000
 476#define QE_CR_SUBBLOCK_UCCSLOW5         0x00800000
 477#define QE_CR_SUBBLOCK_UCCSLOW6         0x00a00000
 478#define QE_CR_SUBBLOCK_UCCSLOW7         0x00c00000
 479#define QE_CR_SUBBLOCK_UCCSLOW8         0x00e00000
 480#define QE_CR_SUBBLOCK_MCC1             0x03800000
 481#define QE_CR_SUBBLOCK_MCC2             0x03a00000
 482#define QE_CR_SUBBLOCK_MCC3             0x03000000
 483#define QE_CR_SUBBLOCK_IDMA1            0x02800000
 484#define QE_CR_SUBBLOCK_IDMA2            0x02a00000
 485#define QE_CR_SUBBLOCK_IDMA3            0x02c00000
 486#define QE_CR_SUBBLOCK_IDMA4            0x02e00000
 487#define QE_CR_SUBBLOCK_HPAC             0x01e00000
 488#define QE_CR_SUBBLOCK_SPI1             0x01400000
 489#define QE_CR_SUBBLOCK_SPI2             0x01600000
 490#define QE_CR_SUBBLOCK_RAND             0x01c00000
 491#define QE_CR_SUBBLOCK_TIMER            0x01e00000
 492#define QE_CR_SUBBLOCK_GENERAL          0x03c00000
 493
 494/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
 495#define QE_CR_PROTOCOL_UNSPECIFIED      0x00    /* For all other protocols */
 496#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
 497#define QE_CR_PROTOCOL_QMC              0x02
 498#define QE_CR_PROTOCOL_UART             0x04
 499#define QE_CR_PROTOCOL_ATM_POS          0x0A
 500#define QE_CR_PROTOCOL_ETHERNET         0x0C
 501#define QE_CR_PROTOCOL_L2_SWITCH        0x0D
 502
 503/* BRG configuration register */
 504#define QE_BRGC_ENABLE          0x00010000
 505#define QE_BRGC_DIVISOR_SHIFT   1
 506#define QE_BRGC_DIVISOR_MAX     0xFFF
 507#define QE_BRGC_DIV16           1
 508
 509/* QE Timers registers */
 510#define QE_GTCFR1_PCAS  0x80
 511#define QE_GTCFR1_STP2  0x20
 512#define QE_GTCFR1_RST2  0x10
 513#define QE_GTCFR1_GM2   0x08
 514#define QE_GTCFR1_GM1   0x04
 515#define QE_GTCFR1_STP1  0x02
 516#define QE_GTCFR1_RST1  0x01
 517
 518/* SDMA registers */
 519#define QE_SDSR_BER1    0x02000000
 520#define QE_SDSR_BER2    0x01000000
 521
 522#define QE_SDMR_GLB_1_MSK       0x80000000
 523#define QE_SDMR_ADR_SEL         0x20000000
 524#define QE_SDMR_BER1_MSK        0x02000000
 525#define QE_SDMR_BER2_MSK        0x01000000
 526#define QE_SDMR_EB1_MSK         0x00800000
 527#define QE_SDMR_ER1_MSK         0x00080000
 528#define QE_SDMR_ER2_MSK         0x00040000
 529#define QE_SDMR_CEN_MASK        0x0000E000
 530#define QE_SDMR_SBER_1          0x00000200
 531#define QE_SDMR_SBER_2          0x00000200
 532#define QE_SDMR_EB1_PR_MASK     0x000000C0
 533#define QE_SDMR_ER1_PR          0x00000008
 534
 535#define QE_SDMR_CEN_SHIFT       13
 536#define QE_SDMR_EB1_PR_SHIFT    6
 537
 538#define QE_SDTM_MSNUM_SHIFT     24
 539
 540#define QE_SDEBCR_BA_MASK       0x01FFFFFF
 541
 542/* Communication Processor */
 543#define QE_CP_CERCR_MEE         0x8000  /* Multi-user RAM ECC enable */
 544#define QE_CP_CERCR_IEE         0x4000  /* Instruction RAM ECC enable */
 545#define QE_CP_CERCR_CIR         0x0800  /* Common instruction RAM */
 546
 547/* I-RAM */
 548#define QE_IRAM_IADD_AIE        0x80000000      /* Auto Increment Enable */
 549#define QE_IRAM_IADD_BADDR      0x00080000      /* Base Address */
 550#define QE_IRAM_READY           0x80000000      /* Ready */
 551
 552/* UPC */
 553#define UPGCR_PROTOCOL  0x80000000      /* protocol ul2 or pl2 */
 554#define UPGCR_TMS       0x40000000      /* Transmit master/slave mode */
 555#define UPGCR_RMS       0x20000000      /* Receive master/slave mode */
 556#define UPGCR_ADDR      0x10000000      /* Master MPHY Addr multiplexing */
 557#define UPGCR_DIAG      0x01000000      /* Diagnostic mode */
 558
 559/* UCC GUEMR register */
 560#define UCC_GUEMR_MODE_MASK_RX  0x02
 561#define UCC_GUEMR_MODE_FAST_RX  0x02
 562#define UCC_GUEMR_MODE_SLOW_RX  0x00
 563#define UCC_GUEMR_MODE_MASK_TX  0x01
 564#define UCC_GUEMR_MODE_FAST_TX  0x01
 565#define UCC_GUEMR_MODE_SLOW_TX  0x00
 566#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
 567#define UCC_GUEMR_SET_RESERVED3 0x10    /* Bit 3 in the guemr is reserved but
 568                                           must be set 1 */
 569
 570/* structure representing UCC SLOW parameter RAM */
 571struct ucc_slow_pram {
 572        __be16 rbase;           /* RX BD base address */
 573        __be16 tbase;           /* TX BD base address */
 574        u8 rbmr;                /* RX bus mode register (same as CPM's RFCR) */
 575        u8 tbmr;                /* TX bus mode register (same as CPM's TFCR) */
 576        __be16 mrblr;           /* Rx buffer length */
 577        __be32 rstate;          /* Rx internal state */
 578        __be32 rptr;            /* Rx internal data pointer */
 579        __be16 rbptr;           /* rb BD Pointer */
 580        __be16 rcount;          /* Rx internal byte count */
 581        __be32 rtemp;           /* Rx temp */
 582        __be32 tstate;          /* Tx internal state */
 583        __be32 tptr;            /* Tx internal data pointer */
 584        __be16 tbptr;           /* Tx BD pointer */
 585        __be16 tcount;          /* Tx byte count */
 586        __be32 ttemp;           /* Tx temp */
 587        __be32 rcrc;            /* temp receive CRC */
 588        __be32 tcrc;            /* temp transmit CRC */
 589} __attribute__ ((packed));
 590
 591/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
 592#define UCC_SLOW_GUMR_H_SAM_QMC         0x00000000
 593#define UCC_SLOW_GUMR_H_SAM_SATM        0x00008000
 594#define UCC_SLOW_GUMR_H_REVD            0x00002000
 595#define UCC_SLOW_GUMR_H_TRX             0x00001000
 596#define UCC_SLOW_GUMR_H_TTX             0x00000800
 597#define UCC_SLOW_GUMR_H_CDP             0x00000400
 598#define UCC_SLOW_GUMR_H_CTSP            0x00000200
 599#define UCC_SLOW_GUMR_H_CDS             0x00000100
 600#define UCC_SLOW_GUMR_H_CTSS            0x00000080
 601#define UCC_SLOW_GUMR_H_TFL             0x00000040
 602#define UCC_SLOW_GUMR_H_RFW             0x00000020
 603#define UCC_SLOW_GUMR_H_TXSY            0x00000010
 604#define UCC_SLOW_GUMR_H_4SYNC           0x00000004
 605#define UCC_SLOW_GUMR_H_8SYNC           0x00000008
 606#define UCC_SLOW_GUMR_H_16SYNC          0x0000000c
 607#define UCC_SLOW_GUMR_H_RTSM            0x00000002
 608#define UCC_SLOW_GUMR_H_RSYN            0x00000001
 609
 610#define UCC_SLOW_GUMR_L_TCI             0x10000000
 611#define UCC_SLOW_GUMR_L_RINV            0x02000000
 612#define UCC_SLOW_GUMR_L_TINV            0x01000000
 613#define UCC_SLOW_GUMR_L_TEND            0x00040000
 614#define UCC_SLOW_GUMR_L_TDCR_MASK       0x00030000
 615#define UCC_SLOW_GUMR_L_TDCR_32         0x00030000
 616#define UCC_SLOW_GUMR_L_TDCR_16         0x00020000
 617#define UCC_SLOW_GUMR_L_TDCR_8          0x00010000
 618#define UCC_SLOW_GUMR_L_TDCR_1          0x00000000
 619#define UCC_SLOW_GUMR_L_RDCR_MASK       0x0000c000
 620#define UCC_SLOW_GUMR_L_RDCR_32         0x0000c000
 621#define UCC_SLOW_GUMR_L_RDCR_16         0x00008000
 622#define UCC_SLOW_GUMR_L_RDCR_8          0x00004000
 623#define UCC_SLOW_GUMR_L_RDCR_1          0x00000000
 624#define UCC_SLOW_GUMR_L_RENC_NRZI       0x00000800
 625#define UCC_SLOW_GUMR_L_RENC_NRZ        0x00000000
 626#define UCC_SLOW_GUMR_L_TENC_NRZI       0x00000100
 627#define UCC_SLOW_GUMR_L_TENC_NRZ        0x00000000
 628#define UCC_SLOW_GUMR_L_DIAG_MASK       0x000000c0
 629#define UCC_SLOW_GUMR_L_DIAG_LE         0x000000c0
 630#define UCC_SLOW_GUMR_L_DIAG_ECHO       0x00000080
 631#define UCC_SLOW_GUMR_L_DIAG_LOOP       0x00000040
 632#define UCC_SLOW_GUMR_L_DIAG_NORM       0x00000000
 633#define UCC_SLOW_GUMR_L_ENR             0x00000020
 634#define UCC_SLOW_GUMR_L_ENT             0x00000010
 635#define UCC_SLOW_GUMR_L_MODE_MASK       0x0000000F
 636#define UCC_SLOW_GUMR_L_MODE_BISYNC     0x00000008
 637#define UCC_SLOW_GUMR_L_MODE_AHDLC      0x00000006
 638#define UCC_SLOW_GUMR_L_MODE_UART       0x00000004
 639#define UCC_SLOW_GUMR_L_MODE_QMC        0x00000002
 640
 641/* General UCC FAST Mode Register */
 642#define UCC_FAST_GUMR_TCI       0x20000000
 643#define UCC_FAST_GUMR_TRX       0x10000000
 644#define UCC_FAST_GUMR_TTX       0x08000000
 645#define UCC_FAST_GUMR_CDP       0x04000000
 646#define UCC_FAST_GUMR_CTSP      0x02000000
 647#define UCC_FAST_GUMR_CDS       0x01000000
 648#define UCC_FAST_GUMR_CTSS      0x00800000
 649#define UCC_FAST_GUMR_TXSY      0x00020000
 650#define UCC_FAST_GUMR_RSYN      0x00010000
 651#define UCC_FAST_GUMR_RTSM      0x00002000
 652#define UCC_FAST_GUMR_REVD      0x00000400
 653#define UCC_FAST_GUMR_ENR       0x00000020
 654#define UCC_FAST_GUMR_ENT       0x00000010
 655
 656/* UART Slow UCC Event Register (UCCE) */
 657#define UCC_UART_UCCE_AB        0x0200
 658#define UCC_UART_UCCE_IDLE      0x0100
 659#define UCC_UART_UCCE_GRA       0x0080
 660#define UCC_UART_UCCE_BRKE      0x0040
 661#define UCC_UART_UCCE_BRKS      0x0020
 662#define UCC_UART_UCCE_CCR       0x0008
 663#define UCC_UART_UCCE_BSY       0x0004
 664#define UCC_UART_UCCE_TX        0x0002
 665#define UCC_UART_UCCE_RX        0x0001
 666
 667/* HDLC Slow UCC Event Register (UCCE) */
 668#define UCC_HDLC_UCCE_GLR       0x1000
 669#define UCC_HDLC_UCCE_GLT       0x0800
 670#define UCC_HDLC_UCCE_IDLE      0x0100
 671#define UCC_HDLC_UCCE_BRKE      0x0040
 672#define UCC_HDLC_UCCE_BRKS      0x0020
 673#define UCC_HDLC_UCCE_TXE       0x0010
 674#define UCC_HDLC_UCCE_RXF       0x0008
 675#define UCC_HDLC_UCCE_BSY       0x0004
 676#define UCC_HDLC_UCCE_TXB       0x0002
 677#define UCC_HDLC_UCCE_RXB       0x0001
 678
 679/* BISYNC Slow UCC Event Register (UCCE) */
 680#define UCC_BISYNC_UCCE_GRA     0x0080
 681#define UCC_BISYNC_UCCE_TXE     0x0010
 682#define UCC_BISYNC_UCCE_RCH     0x0008
 683#define UCC_BISYNC_UCCE_BSY     0x0004
 684#define UCC_BISYNC_UCCE_TXB     0x0002
 685#define UCC_BISYNC_UCCE_RXB     0x0001
 686
 687/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
 688#define UCC_GETH_UCCE_MPD       0x80000000
 689#define UCC_GETH_UCCE_SCAR      0x40000000
 690#define UCC_GETH_UCCE_GRA       0x20000000
 691#define UCC_GETH_UCCE_CBPR      0x10000000
 692#define UCC_GETH_UCCE_BSY       0x08000000
 693#define UCC_GETH_UCCE_RXC       0x04000000
 694#define UCC_GETH_UCCE_TXC       0x02000000
 695#define UCC_GETH_UCCE_TXE       0x01000000
 696#define UCC_GETH_UCCE_TXB7      0x00800000
 697#define UCC_GETH_UCCE_TXB6      0x00400000
 698#define UCC_GETH_UCCE_TXB5      0x00200000
 699#define UCC_GETH_UCCE_TXB4      0x00100000
 700#define UCC_GETH_UCCE_TXB3      0x00080000
 701#define UCC_GETH_UCCE_TXB2      0x00040000
 702#define UCC_GETH_UCCE_TXB1      0x00020000
 703#define UCC_GETH_UCCE_TXB0      0x00010000
 704#define UCC_GETH_UCCE_RXB7      0x00008000
 705#define UCC_GETH_UCCE_RXB6      0x00004000
 706#define UCC_GETH_UCCE_RXB5      0x00002000
 707#define UCC_GETH_UCCE_RXB4      0x00001000
 708#define UCC_GETH_UCCE_RXB3      0x00000800
 709#define UCC_GETH_UCCE_RXB2      0x00000400
 710#define UCC_GETH_UCCE_RXB1      0x00000200
 711#define UCC_GETH_UCCE_RXB0      0x00000100
 712#define UCC_GETH_UCCE_RXF7      0x00000080
 713#define UCC_GETH_UCCE_RXF6      0x00000040
 714#define UCC_GETH_UCCE_RXF5      0x00000020
 715#define UCC_GETH_UCCE_RXF4      0x00000010
 716#define UCC_GETH_UCCE_RXF3      0x00000008
 717#define UCC_GETH_UCCE_RXF2      0x00000004
 718#define UCC_GETH_UCCE_RXF1      0x00000002
 719#define UCC_GETH_UCCE_RXF0      0x00000001
 720
 721/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
 722#define UCC_UART_UPSMR_FLC              0x8000
 723#define UCC_UART_UPSMR_SL               0x4000
 724#define UCC_UART_UPSMR_CL_MASK          0x3000
 725#define UCC_UART_UPSMR_CL_8             0x3000
 726#define UCC_UART_UPSMR_CL_7             0x2000
 727#define UCC_UART_UPSMR_CL_6             0x1000
 728#define UCC_UART_UPSMR_CL_5             0x0000
 729#define UCC_UART_UPSMR_UM_MASK          0x0c00
 730#define UCC_UART_UPSMR_UM_NORMAL        0x0000
 731#define UCC_UART_UPSMR_UM_MAN_MULTI     0x0400
 732#define UCC_UART_UPSMR_UM_AUTO_MULTI    0x0c00
 733#define UCC_UART_UPSMR_FRZ              0x0200
 734#define UCC_UART_UPSMR_RZS              0x0100
 735#define UCC_UART_UPSMR_SYN              0x0080
 736#define UCC_UART_UPSMR_DRT              0x0040
 737#define UCC_UART_UPSMR_PEN              0x0010
 738#define UCC_UART_UPSMR_RPM_MASK         0x000c
 739#define UCC_UART_UPSMR_RPM_ODD          0x0000
 740#define UCC_UART_UPSMR_RPM_LOW          0x0004
 741#define UCC_UART_UPSMR_RPM_EVEN         0x0008
 742#define UCC_UART_UPSMR_RPM_HIGH         0x000C
 743#define UCC_UART_UPSMR_TPM_MASK         0x0003
 744#define UCC_UART_UPSMR_TPM_ODD          0x0000
 745#define UCC_UART_UPSMR_TPM_LOW          0x0001
 746#define UCC_UART_UPSMR_TPM_EVEN         0x0002
 747#define UCC_UART_UPSMR_TPM_HIGH         0x0003
 748
 749/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
 750#define UCC_GETH_UPSMR_FTFE     0x80000000
 751#define UCC_GETH_UPSMR_PTPE     0x40000000
 752#define UCC_GETH_UPSMR_ECM      0x04000000
 753#define UCC_GETH_UPSMR_HSE      0x02000000
 754#define UCC_GETH_UPSMR_PRO      0x00400000
 755#define UCC_GETH_UPSMR_CAP      0x00200000
 756#define UCC_GETH_UPSMR_RSH      0x00100000
 757#define UCC_GETH_UPSMR_RPM      0x00080000
 758#define UCC_GETH_UPSMR_R10M     0x00040000
 759#define UCC_GETH_UPSMR_RLPB     0x00020000
 760#define UCC_GETH_UPSMR_TBIM     0x00010000
 761#define UCC_GETH_UPSMR_RES1     0x00002000
 762#define UCC_GETH_UPSMR_RMM      0x00001000
 763#define UCC_GETH_UPSMR_CAM      0x00000400
 764#define UCC_GETH_UPSMR_BRO      0x00000200
 765#define UCC_GETH_UPSMR_SMM      0x00000080
 766#define UCC_GETH_UPSMR_SGMM     0x00000020
 767
 768/* UCC Transmit On Demand Register (UTODR) */
 769#define UCC_SLOW_TOD    0x8000
 770#define UCC_FAST_TOD    0x8000
 771
 772/* UCC Bus Mode Register masks */
 773/* Not to be confused with the Bundle Mode Register */
 774#define UCC_BMR_GBL             0x20
 775#define UCC_BMR_BO_BE           0x10
 776#define UCC_BMR_CETM            0x04
 777#define UCC_BMR_DTB             0x02
 778#define UCC_BMR_BDB             0x01
 779
 780/* Function code masks */
 781#define FC_GBL                          0x20
 782#define FC_DTB_LCL                      0x02
 783#define UCC_FAST_FUNCTION_CODE_GBL      0x20
 784#define UCC_FAST_FUNCTION_CODE_DTB_LCL  0x02
 785#define UCC_FAST_FUNCTION_CODE_BDB_LCL  0x01
 786
 787#endif /* __KERNEL__ */
 788#endif /* _ASM_POWERPC_QE_H */
 789