1
2
3
4
5
6
7
8#ifndef _ASM_ASMMACRO_H
9#define _ASM_ASMMACRO_H
10
11#include <asm/hazards.h>
12#include <asm/asm-offsets.h>
13#include <asm/msa.h>
14
15#ifdef CONFIG_32BIT
16#include <asm/asmmacro-32.h>
17#endif
18#ifdef CONFIG_64BIT
19#include <asm/asmmacro-64.h>
20#endif
21
22
23
24
25#ifdef CONFIG_CPU_MICROMIPS
26 .macro insn32_if_mm enc
27 .insn
28 .hword ((\enc) >> 16)
29 .hword ((\enc) & 0xffff)
30 .endm
31
32 .macro insn_if_mips enc
33 .endm
34#else
35 .macro insn32_if_mm enc
36 .endm
37
38 .macro insn_if_mips enc
39 .insn
40 .word (\enc)
41 .endm
42#endif
43
44#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
45 .macro local_irq_enable reg=t0
46 ei
47 irq_enable_hazard
48 .endm
49
50 .macro local_irq_disable reg=t0
51 di
52 irq_disable_hazard
53 .endm
54#else
55 .macro local_irq_enable reg=t0
56 mfc0 \reg, CP0_STATUS
57 ori \reg, \reg, 1
58 mtc0 \reg, CP0_STATUS
59 irq_enable_hazard
60 .endm
61
62 .macro local_irq_disable reg=t0
63#ifdef CONFIG_PREEMPT
64 lw \reg, TI_PRE_COUNT($28)
65 addi \reg, \reg, 1
66 sw \reg, TI_PRE_COUNT($28)
67#endif
68 mfc0 \reg, CP0_STATUS
69 ori \reg, \reg, 1
70 xori \reg, \reg, 1
71 mtc0 \reg, CP0_STATUS
72 irq_disable_hazard
73#ifdef CONFIG_PREEMPT
74 lw \reg, TI_PRE_COUNT($28)
75 addi \reg, \reg, -1
76 sw \reg, TI_PRE_COUNT($28)
77#endif
78 .endm
79#endif
80
81 .macro fpu_save_16even thread tmp=t0
82 .set push
83 SET_HARDFLOAT
84 cfc1 \tmp, fcr31
85 sdc1 $f0, THREAD_FPR0(\thread)
86 sdc1 $f2, THREAD_FPR2(\thread)
87 sdc1 $f4, THREAD_FPR4(\thread)
88 sdc1 $f6, THREAD_FPR6(\thread)
89 sdc1 $f8, THREAD_FPR8(\thread)
90 sdc1 $f10, THREAD_FPR10(\thread)
91 sdc1 $f12, THREAD_FPR12(\thread)
92 sdc1 $f14, THREAD_FPR14(\thread)
93 sdc1 $f16, THREAD_FPR16(\thread)
94 sdc1 $f18, THREAD_FPR18(\thread)
95 sdc1 $f20, THREAD_FPR20(\thread)
96 sdc1 $f22, THREAD_FPR22(\thread)
97 sdc1 $f24, THREAD_FPR24(\thread)
98 sdc1 $f26, THREAD_FPR26(\thread)
99 sdc1 $f28, THREAD_FPR28(\thread)
100 sdc1 $f30, THREAD_FPR30(\thread)
101 sw \tmp, THREAD_FCR31(\thread)
102 .set pop
103 .endm
104
105 .macro fpu_save_16odd thread
106 .set push
107 .set mips64r2
108 SET_HARDFLOAT
109 sdc1 $f1, THREAD_FPR1(\thread)
110 sdc1 $f3, THREAD_FPR3(\thread)
111 sdc1 $f5, THREAD_FPR5(\thread)
112 sdc1 $f7, THREAD_FPR7(\thread)
113 sdc1 $f9, THREAD_FPR9(\thread)
114 sdc1 $f11, THREAD_FPR11(\thread)
115 sdc1 $f13, THREAD_FPR13(\thread)
116 sdc1 $f15, THREAD_FPR15(\thread)
117 sdc1 $f17, THREAD_FPR17(\thread)
118 sdc1 $f19, THREAD_FPR19(\thread)
119 sdc1 $f21, THREAD_FPR21(\thread)
120 sdc1 $f23, THREAD_FPR23(\thread)
121 sdc1 $f25, THREAD_FPR25(\thread)
122 sdc1 $f27, THREAD_FPR27(\thread)
123 sdc1 $f29, THREAD_FPR29(\thread)
124 sdc1 $f31, THREAD_FPR31(\thread)
125 .set pop
126 .endm
127
128 .macro fpu_save_double thread status tmp
129#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
130 defined(CONFIG_CPU_MIPS32_R6)
131 sll \tmp, \status, 5
132 bgez \tmp, 10f
133 fpu_save_16odd \thread
13410:
135#endif
136 fpu_save_16even \thread \tmp
137 .endm
138
139 .macro fpu_restore_16even thread tmp=t0
140 .set push
141 SET_HARDFLOAT
142 lw \tmp, THREAD_FCR31(\thread)
143 ldc1 $f0, THREAD_FPR0(\thread)
144 ldc1 $f2, THREAD_FPR2(\thread)
145 ldc1 $f4, THREAD_FPR4(\thread)
146 ldc1 $f6, THREAD_FPR6(\thread)
147 ldc1 $f8, THREAD_FPR8(\thread)
148 ldc1 $f10, THREAD_FPR10(\thread)
149 ldc1 $f12, THREAD_FPR12(\thread)
150 ldc1 $f14, THREAD_FPR14(\thread)
151 ldc1 $f16, THREAD_FPR16(\thread)
152 ldc1 $f18, THREAD_FPR18(\thread)
153 ldc1 $f20, THREAD_FPR20(\thread)
154 ldc1 $f22, THREAD_FPR22(\thread)
155 ldc1 $f24, THREAD_FPR24(\thread)
156 ldc1 $f26, THREAD_FPR26(\thread)
157 ldc1 $f28, THREAD_FPR28(\thread)
158 ldc1 $f30, THREAD_FPR30(\thread)
159 ctc1 \tmp, fcr31
160 .endm
161
162 .macro fpu_restore_16odd thread
163 .set push
164 .set mips64r2
165 SET_HARDFLOAT
166 ldc1 $f1, THREAD_FPR1(\thread)
167 ldc1 $f3, THREAD_FPR3(\thread)
168 ldc1 $f5, THREAD_FPR5(\thread)
169 ldc1 $f7, THREAD_FPR7(\thread)
170 ldc1 $f9, THREAD_FPR9(\thread)
171 ldc1 $f11, THREAD_FPR11(\thread)
172 ldc1 $f13, THREAD_FPR13(\thread)
173 ldc1 $f15, THREAD_FPR15(\thread)
174 ldc1 $f17, THREAD_FPR17(\thread)
175 ldc1 $f19, THREAD_FPR19(\thread)
176 ldc1 $f21, THREAD_FPR21(\thread)
177 ldc1 $f23, THREAD_FPR23(\thread)
178 ldc1 $f25, THREAD_FPR25(\thread)
179 ldc1 $f27, THREAD_FPR27(\thread)
180 ldc1 $f29, THREAD_FPR29(\thread)
181 ldc1 $f31, THREAD_FPR31(\thread)
182 .set pop
183 .endm
184
185 .macro fpu_restore_double thread status tmp
186#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
187 defined(CONFIG_CPU_MIPS32_R6)
188 sll \tmp, \status, 5
189 bgez \tmp, 10f # 16 register mode?
190
191 fpu_restore_16odd \thread
19210:
193#endif
194 fpu_restore_16even \thread \tmp
195 .endm
196
197#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
198 .macro _EXT rd, rs, p, s
199 ext \rd, \rs, \p, \s
200 .endm
201#else
202 .macro _EXT rd, rs, p, s
203 srl \rd, \rs, \p
204 andi \rd, \rd, (1 << \s) - 1
205 .endm
206#endif
207
208
209
210
211 .macro DMT reg=0
212 .word 0x41600bc1 | (\reg << 16)
213 .endm
214
215 .macro EMT reg=0
216 .word 0x41600be1 | (\reg << 16)
217 .endm
218
219 .macro DVPE reg=0
220 .word 0x41600001 | (\reg << 16)
221 .endm
222
223 .macro EVPE reg=0
224 .word 0x41600021 | (\reg << 16)
225 .endm
226
227 .macro MFTR rt=0, rd=0, u=0, sel=0
228 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
229 .endm
230
231 .macro MTTR rt=0, rd=0, u=0, sel=0
232 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
233 .endm
234
235#ifdef TOOLCHAIN_SUPPORTS_MSA
236
237#undef fp
238
239 .macro _cfcmsa rd, cs
240 .set push
241 .set mips32r2
242 .set fp=64
243 .set msa
244 cfcmsa \rd, $\cs
245 .set pop
246 .endm
247
248 .macro _ctcmsa cd, rs
249 .set push
250 .set mips32r2
251 .set fp=64
252 .set msa
253 ctcmsa $\cd, \rs
254 .set pop
255 .endm
256
257 .macro ld_b wd, off, base
258 .set push
259 .set mips32r2
260 .set fp=64
261 .set msa
262 ld.b $w\wd, \off(\base)
263 .set pop
264 .endm
265
266 .macro ld_h wd, off, base
267 .set push
268 .set mips32r2
269 .set fp=64
270 .set msa
271 ld.h $w\wd, \off(\base)
272 .set pop
273 .endm
274
275 .macro ld_w wd, off, base
276 .set push
277 .set mips32r2
278 .set fp=64
279 .set msa
280 ld.w $w\wd, \off(\base)
281 .set pop
282 .endm
283
284 .macro ld_d wd, off, base
285 .set push
286 .set mips32r2
287 .set fp=64
288 .set msa
289 ld.d $w\wd, \off(\base)
290 .set pop
291 .endm
292
293 .macro st_b wd, off, base
294 .set push
295 .set mips32r2
296 .set fp=64
297 .set msa
298 st.b $w\wd, \off(\base)
299 .set pop
300 .endm
301
302 .macro st_h wd, off, base
303 .set push
304 .set mips32r2
305 .set fp=64
306 .set msa
307 st.h $w\wd, \off(\base)
308 .set pop
309 .endm
310
311 .macro st_w wd, off, base
312 .set push
313 .set mips32r2
314 .set fp=64
315 .set msa
316 st.w $w\wd, \off(\base)
317 .set pop
318 .endm
319
320 .macro st_d wd, off, base
321 .set push
322 .set mips32r2
323 .set fp=64
324 .set msa
325 st.d $w\wd, \off(\base)
326 .set pop
327 .endm
328
329 .macro copy_s_w ws, n
330 .set push
331 .set mips32r2
332 .set fp=64
333 .set msa
334 copy_s.w $1, $w\ws[\n]
335 .set pop
336 .endm
337
338 .macro copy_s_d ws, n
339 .set push
340 .set mips64r2
341 .set fp=64
342 .set msa
343 copy_s.d $1, $w\ws[\n]
344 .set pop
345 .endm
346
347 .macro insert_w wd, n
348 .set push
349 .set mips32r2
350 .set fp=64
351 .set msa
352 insert.w $w\wd[\n], $1
353 .set pop
354 .endm
355
356 .macro insert_d wd, n
357 .set push
358 .set mips64r2
359 .set fp=64
360 .set msa
361 insert.d $w\wd[\n], $1
362 .set pop
363 .endm
364#else
365
366
367
368
369 .macro _cfcmsa rd, cs
370 .set push
371 .set noat
372 SET_HARDFLOAT
373 insn_if_mips 0x787e0059 | (\cs << 11)
374 insn32_if_mm 0x587e0056 | (\cs << 11)
375 move \rd, $1
376 .set pop
377 .endm
378
379 .macro _ctcmsa cd, rs
380 .set push
381 .set noat
382 SET_HARDFLOAT
383 move $1, \rs
384 insn_if_mips 0x783e0819 | (\cd << 6)
385 insn32_if_mm 0x583e0816 | (\cd << 6)
386 .set pop
387 .endm
388
389 .macro ld_b wd, off, base
390 .set push
391 .set noat
392 SET_HARDFLOAT
393 PTR_ADDU $1, \base, \off
394 insn_if_mips 0x78000820 | (\wd << 6)
395 insn32_if_mm 0x58000807 | (\wd << 6)
396 .set pop
397 .endm
398
399 .macro ld_h wd, off, base
400 .set push
401 .set noat
402 SET_HARDFLOAT
403 PTR_ADDU $1, \base, \off
404 insn_if_mips 0x78000821 | (\wd << 6)
405 insn32_if_mm 0x58000817 | (\wd << 6)
406 .set pop
407 .endm
408
409 .macro ld_w wd, off, base
410 .set push
411 .set noat
412 SET_HARDFLOAT
413 PTR_ADDU $1, \base, \off
414 insn_if_mips 0x78000822 | (\wd << 6)
415 insn32_if_mm 0x58000827 | (\wd << 6)
416 .set pop
417 .endm
418
419 .macro ld_d wd, off, base
420 .set push
421 .set noat
422 SET_HARDFLOAT
423 PTR_ADDU $1, \base, \off
424 insn_if_mips 0x78000823 | (\wd << 6)
425 insn32_if_mm 0x58000837 | (\wd << 6)
426 .set pop
427 .endm
428
429 .macro st_b wd, off, base
430 .set push
431 .set noat
432 SET_HARDFLOAT
433 PTR_ADDU $1, \base, \off
434 insn_if_mips 0x78000824 | (\wd << 6)
435 insn32_if_mm 0x5800080f | (\wd << 6)
436 .set pop
437 .endm
438
439 .macro st_h wd, off, base
440 .set push
441 .set noat
442 SET_HARDFLOAT
443 PTR_ADDU $1, \base, \off
444 insn_if_mips 0x78000825 | (\wd << 6)
445 insn32_if_mm 0x5800081f | (\wd << 6)
446 .set pop
447 .endm
448
449 .macro st_w wd, off, base
450 .set push
451 .set noat
452 SET_HARDFLOAT
453 PTR_ADDU $1, \base, \off
454 insn_if_mips 0x78000826 | (\wd << 6)
455 insn32_if_mm 0x5800082f | (\wd << 6)
456 .set pop
457 .endm
458
459 .macro st_d wd, off, base
460 .set push
461 .set noat
462 SET_HARDFLOAT
463 PTR_ADDU $1, \base, \off
464 insn_if_mips 0x78000827 | (\wd << 6)
465 insn32_if_mm 0x5800083f | (\wd << 6)
466 .set pop
467 .endm
468
469 .macro copy_s_w ws, n
470 .set push
471 .set noat
472 SET_HARDFLOAT
473 insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
474 insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
475 .set pop
476 .endm
477
478 .macro copy_s_d ws, n
479 .set push
480 .set noat
481 SET_HARDFLOAT
482 insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
483 insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
484 .set pop
485 .endm
486
487 .macro insert_w wd, n
488 .set push
489 .set noat
490 SET_HARDFLOAT
491 insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
492 insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
493 .set pop
494 .endm
495
496 .macro insert_d wd, n
497 .set push
498 .set noat
499 SET_HARDFLOAT
500 insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
501 insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
502 .set pop
503 .endm
504#endif
505
506#ifdef TOOLCHAIN_SUPPORTS_MSA
507#define FPR_BASE_OFFS THREAD_FPR0
508#define FPR_BASE $1
509#else
510#define FPR_BASE_OFFS 0
511#define FPR_BASE \thread
512#endif
513
514 .macro msa_save_all thread
515 .set push
516 .set noat
517#ifdef TOOLCHAIN_SUPPORTS_MSA
518 PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
519#endif
520 st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
521 st_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
522 st_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
523 st_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
524 st_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
525 st_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
526 st_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
527 st_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
528 st_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
529 st_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
530 st_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
531 st_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
532 st_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
533 st_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
534 st_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
535 st_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
536 st_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
537 st_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
538 st_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
539 st_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
540 st_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
541 st_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
542 st_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
543 st_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
544 st_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
545 st_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
546 st_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
547 st_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
548 st_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
549 st_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
550 st_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
551 st_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
552 SET_HARDFLOAT
553 _cfcmsa $1, MSA_CSR
554 sw $1, THREAD_MSA_CSR(\thread)
555 .set pop
556 .endm
557
558 .macro msa_restore_all thread
559 .set push
560 .set noat
561 SET_HARDFLOAT
562 lw $1, THREAD_MSA_CSR(\thread)
563 _ctcmsa MSA_CSR, $1
564#ifdef TOOLCHAIN_SUPPORTS_MSA
565 PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
566#endif
567 ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
568 ld_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
569 ld_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
570 ld_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
571 ld_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
572 ld_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
573 ld_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
574 ld_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
575 ld_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
576 ld_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
577 ld_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
578 ld_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
579 ld_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
580 ld_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
581 ld_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
582 ld_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
583 ld_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
584 ld_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
585 ld_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
586 ld_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
587 ld_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
588 ld_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
589 ld_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
590 ld_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
591 ld_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
592 ld_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
593 ld_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
594 ld_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
595 ld_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
596 ld_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
597 ld_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
598 ld_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
599 .set pop
600 .endm
601
602#undef FPR_BASE_OFFS
603#undef FPR_BASE
604
605 .macro msa_init_upper wd
606#ifdef CONFIG_64BIT
607 insert_d \wd, 1
608#else
609 insert_w \wd, 2
610 insert_w \wd, 3
611#endif
612 .endm
613
614 .macro msa_init_all_upper
615 .set push
616 .set noat
617 SET_HARDFLOAT
618 not $1, zero
619 msa_init_upper 0
620 msa_init_upper 1
621 msa_init_upper 2
622 msa_init_upper 3
623 msa_init_upper 4
624 msa_init_upper 5
625 msa_init_upper 6
626 msa_init_upper 7
627 msa_init_upper 8
628 msa_init_upper 9
629 msa_init_upper 10
630 msa_init_upper 11
631 msa_init_upper 12
632 msa_init_upper 13
633 msa_init_upper 14
634 msa_init_upper 15
635 msa_init_upper 16
636 msa_init_upper 17
637 msa_init_upper 18
638 msa_init_upper 19
639 msa_init_upper 20
640 msa_init_upper 21
641 msa_init_upper 22
642 msa_init_upper 23
643 msa_init_upper 24
644 msa_init_upper 25
645 msa_init_upper 26
646 msa_init_upper 27
647 msa_init_upper 28
648 msa_init_upper 29
649 msa_init_upper 30
650 msa_init_upper 31
651 .set pop
652 .endm
653
654#endif
655
