LXR linux/arch/mips/include/uapi/asm/inst.h

   1/*
   2 * Format of an instruction in memory.
   3 *
   4 * This file is subject to the terms and conditions of the GNU General Public
   5 * License.  See the file "COPYING" in the main directory of this archive
   6 * for more details.
   7 *
   8 * Copyright (C) 1996, 2000 by Ralf Baechle
   9 * Copyright (C) 2006 by Thiemo Seufer
  10 * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
  11 * Copyright (C) 2014 Imagination Technologies Ltd.
  12 */
  13#ifndef _UAPI_ASM_INST_H
  14#define _UAPI_ASM_INST_H
  15
  16#include <asm/bitfield.h>
  17
  18/*
  19 * Major opcodes; before MIPS IV cop1x was called cop3.
  20 */
  21enum major_op {
  22        spec_op, bcond_op, j_op, jal_op,
  23        beq_op, bne_op, blez_op, bgtz_op,
  24        addi_op, cbcond0_op = addi_op, addiu_op, slti_op, sltiu_op,
  25        andi_op, ori_op, xori_op, lui_op,
  26        cop0_op, cop1_op, cop2_op, cop1x_op,
  27        beql_op, bnel_op, blezl_op, bgtzl_op,
  28        daddi_op, cbcond1_op = daddi_op, daddiu_op, ldl_op, ldr_op,
  29        spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op,
  30        lb_op, lh_op, lwl_op, lw_op,
  31        lbu_op, lhu_op, lwr_op, lwu_op,
  32        sb_op, sh_op, swl_op, sw_op,
  33        sdl_op, sdr_op, swr_op, cache_op,
  34        ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
  35        lld_op, ldc1_op, ldc2_op, beqzcjic_op = ldc2_op, ld_op,
  36        sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
  37        scd_op, sdc1_op, sdc2_op, bnezcjialc_op = sdc2_op, sd_op
  38};
  39
  40/*
  41 * func field of spec opcode.
  42 */
  43enum spec_op {
  44        sll_op, movc_op, srl_op, sra_op,
  45        sllv_op, pmon_op, srlv_op, srav_op,
  46        jr_op, jalr_op, movz_op, movn_op,
  47        syscall_op, break_op, spim_op, sync_op,
  48        mfhi_op, mthi_op, mflo_op, mtlo_op,
  49        dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
  50        mult_op, multu_op, div_op, divu_op,
  51        dmult_op, dmultu_op, ddiv_op, ddivu_op,
  52        add_op, addu_op, sub_op, subu_op,
  53        and_op, or_op, xor_op, nor_op,
  54        spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
  55        dadd_op, daddu_op, dsub_op, dsubu_op,
  56        tge_op, tgeu_op, tlt_op, tltu_op,
  57        teq_op, spec5_unused_op, tne_op, spec6_unused_op,
  58        dsll_op, spec7_unused_op, dsrl_op, dsra_op,
  59        dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
  60};
  61
  62/*
  63 * func field of spec2 opcode.
  64 */
  65enum spec2_op {
  66        madd_op, maddu_op, mul_op, spec2_3_unused_op,
  67        msub_op, msubu_op, /* more unused ops */
  68        clz_op = 0x20, clo_op,
  69        dclz_op = 0x24, dclo_op,
  70        sdbpp_op = 0x3f
  71};
  72
  73/*
  74 * func field of spec3 opcode.
  75 */
  76enum spec3_op {
  77        ext_op, dextm_op, dextu_op, dext_op,
  78        ins_op, dinsm_op, dinsu_op, dins_op,
  79        yield_op  = 0x09, lx_op     = 0x0a,
  80        lwle_op   = 0x19, lwre_op   = 0x1a,
  81        cachee_op = 0x1b, sbe_op    = 0x1c,
  82        she_op    = 0x1d, sce_op    = 0x1e,
  83        swe_op    = 0x1f, bshfl_op  = 0x20,
  84        swle_op   = 0x21, swre_op   = 0x22,
  85        prefe_op  = 0x23, dbshfl_op = 0x24,
  86        cache6_op = 0x25, sc6_op    = 0x26,
  87        scd6_op   = 0x27, lbue_op   = 0x28,
  88        lhue_op   = 0x29, lbe_op    = 0x2c,
  89        lhe_op    = 0x2d, lle_op    = 0x2e,
  90        lwe_op    = 0x2f, pref6_op  = 0x35,
  91        ll6_op    = 0x36, lld6_op   = 0x37,
  92        rdhwr_op  = 0x3b
  93};
  94
  95/*
  96 * rt field of bcond opcodes.
  97 */
  98enum rt_op {
  99        bltz_op, bgez_op, bltzl_op, bgezl_op,
 100        spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
 101        tgei_op, tgeiu_op, tlti_op, tltiu_op,
 102        teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
 103        bltzal_op, bgezal_op, bltzall_op, bgezall_op,
 104        rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
 105        rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
 106        bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
 107};
 108
 109/*
 110 * rs field of cop opcodes.
 111 */
 112enum cop_op {
 113        mfc_op        = 0x00, dmfc_op       = 0x01,
 114        cfc_op        = 0x02, mfhc0_op      = 0x02,
 115        mfhc_op       = 0x03, mtc_op        = 0x04,
 116        dmtc_op       = 0x05, ctc_op        = 0x06,
 117        mthc0_op      = 0x06, mthc_op       = 0x07,
 118        bc_op         = 0x08, bc1eqz_op     = 0x09,
 119        mfmc0_op      = 0x0b, bc1nez_op     = 0x0d,
 120        wrpgpr_op     = 0x0e, cop_op        = 0x10,
 121        copm_op       = 0x18
 122};
 123
 124/*
 125 * rt field of cop.bc_op opcodes
 126 */
 127enum bcop_op {
 128        bcf_op, bct_op, bcfl_op, bctl_op
 129};
 130
 131/*
 132 * func field of cop0 coi opcodes.
 133 */
 134enum cop0_coi_func {
 135        tlbr_op       = 0x01, tlbwi_op      = 0x02,
 136        tlbwr_op      = 0x06, tlbp_op       = 0x08,
 137        rfe_op        = 0x10, eret_op       = 0x18,
 138        wait_op       = 0x20,
 139};
 140
 141/*
 142 * func field of cop0 com opcodes.
 143 */
 144enum cop0_com_func {
 145        tlbr1_op      = 0x01, tlbw_op       = 0x02,
 146        tlbp1_op      = 0x08, dctr_op       = 0x09,
 147        dctw_op       = 0x0a
 148};
 149
 150/*
 151 * fmt field of cop1 opcodes.
 152 */
 153enum cop1_fmt {
 154        s_fmt, d_fmt, e_fmt, q_fmt,
 155        w_fmt, l_fmt
 156};
 157
 158/*
 159 * func field of cop1 instructions using d, s or w format.
 160 */
 161enum cop1_sdw_func {
 162        fadd_op      =  0x00, fsub_op      =  0x01,
 163        fmul_op      =  0x02, fdiv_op      =  0x03,
 164        fsqrt_op     =  0x04, fabs_op      =  0x05,
 165        fmov_op      =  0x06, fneg_op      =  0x07,
 166        froundl_op   =  0x08, ftruncl_op   =  0x09,
 167        fceill_op    =  0x0a, ffloorl_op   =  0x0b,
 168        fround_op    =  0x0c, ftrunc_op    =  0x0d,
 169        fceil_op     =  0x0e, ffloor_op    =  0x0f,
 170        fsel_op      =  0x10,
 171        fmovc_op     =  0x11, fmovz_op     =  0x12,
 172        fmovn_op     =  0x13, fseleqz_op   =  0x14,
 173        frecip_op    =  0x15, frsqrt_op    =  0x16,
 174        fselnez_op   =  0x17, fmaddf_op    =  0x18,
 175        fmsubf_op    =  0x19, frint_op     =  0x1a,
 176        fclass_op    =  0x1b, fmin_op      =  0x1c,
 177        fmina_op     =  0x1d, fmax_op      =  0x1e,
 178        fmaxa_op     =  0x1f, fcvts_op     =  0x20,
 179        fcvtd_op     =  0x21, fcvte_op     =  0x22,
 180        fcvtw_op     =  0x24, fcvtl_op     =  0x25,
 181        fcmp_op      =  0x30
 182};
 183
 184/*
 185 * func field of cop1x opcodes (MIPS IV).
 186 */
 187enum cop1x_func {
 188        lwxc1_op     =  0x00, ldxc1_op     =  0x01,
 189        swxc1_op     =  0x08, sdxc1_op     =  0x09,
 190        pfetch_op    =  0x0f, madd_s_op    =  0x20,
 191        madd_d_op    =  0x21, madd_e_op    =  0x22,
 192        msub_s_op    =  0x28, msub_d_op    =  0x29,
 193        msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
 194        nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
 195        nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
 196        nmsub_e_op   =  0x3a
 197};
 198
 199/*
 200 * func field for mad opcodes (MIPS IV).
 201 */
 202enum mad_func {
 203        madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
 204        nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
 205};
 206
 207/*
 208 * func field for page table walker (Loongson-3).
 209 */
 210enum ptw_func {
 211        lwdir_op = 0x00,
 212        lwpte_op = 0x01,
 213        lddir_op = 0x02,
 214        ldpte_op = 0x03,
 215};
 216
 217/*
 218 * func field for special3 lx opcodes (Cavium Octeon).
 219 */
 220enum lx_func {
 221        lwx_op  = 0x00,
 222        lhx_op  = 0x04,
 223        lbux_op = 0x06,
 224        ldx_op  = 0x08,
 225        lwux_op = 0x10,
 226        lhux_op = 0x14,
 227        lbx_op  = 0x16,
 228};
 229
 230/*
 231 * BSHFL opcodes
 232 */
 233enum bshfl_func {
 234        wsbh_op = 0x2,
 235        dshd_op = 0x5,
 236        seb_op  = 0x10,
 237        seh_op  = 0x18,
 238};
 239
 240/*
 241 * func field for MSA MI10 format.
 242 */
 243enum msa_mi10_func {
 244        msa_ld_op = 8,
 245        msa_st_op = 9,
 246};
 247
 248/*
 249 * MSA 2 bit format fields.
 250 */
 251enum msa_2b_fmt {
 252        msa_fmt_b = 0,
 253        msa_fmt_h = 1,
 254        msa_fmt_w = 2,
 255        msa_fmt_d = 3,
 256};
 257
 258/*
 259 * (microMIPS) Major opcodes.
 260 */
 261enum mm_major_op {
 262        mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
 263        mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
 264        mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
 265        mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
 266        mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
 267        mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
 268        mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
 269        mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
 270        mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
 271        mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
 272        mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
 273        mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
 274        mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
 275        mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
 276        mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
 277        mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
 278};
 279
 280/*
 281 * (microMIPS) POOL32I minor opcodes.
 282 */
 283enum mm_32i_minor_op {
 284        mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
 285        mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
 286        mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
 287        mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
 288        mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
 289        mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
 290        mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
 291        mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
 292        mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
 293};
 294
 295/*
 296 * (microMIPS) POOL32A minor opcodes.
 297 */
 298enum mm_32a_minor_op {
 299        mm_sll32_op = 0x000,
 300        mm_ins_op = 0x00c,
 301        mm_sllv32_op = 0x010,
 302        mm_ext_op = 0x02c,
 303        mm_pool32axf_op = 0x03c,
 304        mm_srl32_op = 0x040,
 305        mm_sra_op = 0x080,
 306        mm_srlv32_op = 0x090,
 307        mm_rotr_op = 0x0c0,
 308        mm_lwxs_op = 0x118,
 309        mm_addu32_op = 0x150,
 310        mm_subu32_op = 0x1d0,
 311        mm_wsbh_op = 0x1ec,
 312        mm_mul_op = 0x210,
 313        mm_and_op = 0x250,
 314        mm_or32_op = 0x290,
 315        mm_xor32_op = 0x310,
 316        mm_slt_op = 0x350,
 317        mm_sltu_op = 0x390,
 318};
 319
 320/*
 321 * (microMIPS) POOL32B functions.
 322 */
 323enum mm_32b_func {
 324        mm_lwc2_func = 0x0,
 325        mm_lwp_func = 0x1,
 326        mm_ldc2_func = 0x2,
 327        mm_ldp_func = 0x4,
 328        mm_lwm32_func = 0x5,
 329        mm_cache_func = 0x6,
 330        mm_ldm_func = 0x7,
 331        mm_swc2_func = 0x8,
 332        mm_swp_func = 0x9,
 333        mm_sdc2_func = 0xa,
 334        mm_sdp_func = 0xc,
 335        mm_swm32_func = 0xd,
 336        mm_sdm_func = 0xf,
 337};
 338
 339/*
 340 * (microMIPS) POOL32C functions.
 341 */
 342enum mm_32c_func {
 343        mm_pref_func = 0x2,
 344        mm_ll_func = 0x3,
 345        mm_swr_func = 0x9,
 346        mm_sc_func = 0xb,
 347        mm_lwu_func = 0xe,
 348};
 349
 350/*
 351 * (microMIPS) POOL32AXF minor opcodes.
 352 */
 353enum mm_32axf_minor_op {
 354        mm_mfc0_op = 0x003,
 355        mm_mtc0_op = 0x00b,
 356        mm_tlbp_op = 0x00d,
 357        mm_mfhi32_op = 0x035,
 358        mm_jalr_op = 0x03c,
 359        mm_tlbr_op = 0x04d,
 360        mm_mflo32_op = 0x075,
 361        mm_jalrhb_op = 0x07c,
 362        mm_tlbwi_op = 0x08d,
 363        mm_tlbwr_op = 0x0cd,
 364        mm_jalrs_op = 0x13c,
 365        mm_jalrshb_op = 0x17c,
 366        mm_sync_op = 0x1ad,
 367        mm_syscall_op = 0x22d,
 368        mm_wait_op = 0x24d,
 369        mm_eret_op = 0x3cd,
 370        mm_divu_op = 0x5dc,
 371};
 372
 373/*
 374 * (microMIPS) POOL32F minor opcodes.
 375 */
 376enum mm_32f_minor_op {
 377        mm_32f_00_op = 0x00,
 378        mm_32f_01_op = 0x01,
 379        mm_32f_02_op = 0x02,
 380        mm_32f_10_op = 0x08,
 381        mm_32f_11_op = 0x09,
 382        mm_32f_12_op = 0x0a,
 383        mm_32f_20_op = 0x10,
 384        mm_32f_30_op = 0x18,
 385        mm_32f_40_op = 0x20,
 386        mm_32f_41_op = 0x21,
 387        mm_32f_42_op = 0x22,
 388        mm_32f_50_op = 0x28,
 389        mm_32f_51_op = 0x29,
 390        mm_32f_52_op = 0x2a,
 391        mm_32f_60_op = 0x30,
 392        mm_32f_70_op = 0x38,
 393        mm_32f_73_op = 0x3b,
 394        mm_32f_74_op = 0x3c,
 395};
 396
 397/*
 398 * (microMIPS) POOL32F secondary minor opcodes.
 399 */
 400enum mm_32f_10_minor_op {
 401        mm_lwxc1_op = 0x1,
 402        mm_swxc1_op,
 403        mm_ldxc1_op,
 404        mm_sdxc1_op,
 405        mm_luxc1_op,
 406        mm_suxc1_op,
 407};
 408
 409enum mm_32f_func {
 410        mm_lwxc1_func = 0x048,
 411        mm_swxc1_func = 0x088,
 412        mm_ldxc1_func = 0x0c8,
 413        mm_sdxc1_func = 0x108,
 414};
 415
 416/*
 417 * (microMIPS) POOL32F secondary minor opcodes.
 418 */
 419enum mm_32f_40_minor_op {
 420        mm_fmovf_op,
 421        mm_fmovt_op,
 422};
 423
 424/*
 425 * (microMIPS) POOL32F secondary minor opcodes.
 426 */
 427enum mm_32f_60_minor_op {
 428        mm_fadd_op,
 429        mm_fsub_op,
 430        mm_fmul_op,
 431        mm_fdiv_op,
 432};
 433
 434/*
 435 * (microMIPS) POOL32F secondary minor opcodes.
 436 */
 437enum mm_32f_70_minor_op {
 438        mm_fmovn_op,
 439        mm_fmovz_op,
 440};
 441
 442/*
 443 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
 444 */
 445enum mm_32f_73_minor_op {
 446        mm_fmov0_op = 0x01,
 447        mm_fcvtl_op = 0x04,
 448        mm_movf0_op = 0x05,
 449        mm_frsqrt_op = 0x08,
 450        mm_ffloorl_op = 0x0c,
 451        mm_fabs0_op = 0x0d,
 452        mm_fcvtw_op = 0x24,
 453        mm_movt0_op = 0x25,
 454        mm_fsqrt_op = 0x28,
 455        mm_ffloorw_op = 0x2c,
 456        mm_fneg0_op = 0x2d,
 457        mm_cfc1_op = 0x40,
 458        mm_frecip_op = 0x48,
 459        mm_fceill_op = 0x4c,
 460        mm_fcvtd0_op = 0x4d,
 461        mm_ctc1_op = 0x60,
 462        mm_fceilw_op = 0x6c,
 463        mm_fcvts0_op = 0x6d,
 464        mm_mfc1_op = 0x80,
 465        mm_fmov1_op = 0x81,
 466        mm_movf1_op = 0x85,
 467        mm_ftruncl_op = 0x8c,
 468        mm_fabs1_op = 0x8d,
 469        mm_mtc1_op = 0xa0,
 470        mm_movt1_op = 0xa5,
 471        mm_ftruncw_op = 0xac,
 472        mm_fneg1_op = 0xad,
 473        mm_mfhc1_op = 0xc0,
 474        mm_froundl_op = 0xcc,
 475        mm_fcvtd1_op = 0xcd,
 476        mm_mthc1_op = 0xe0,
 477        mm_froundw_op = 0xec,
 478        mm_fcvts1_op = 0xed,
 479};
 480
 481/*
 482 * (microMIPS) POOL16C minor opcodes.
 483 */
 484enum mm_16c_minor_op {
 485        mm_lwm16_op = 0x04,
 486        mm_swm16_op = 0x05,
 487        mm_jr16_op = 0x0c,
 488        mm_jrc_op = 0x0d,
 489        mm_jalr16_op = 0x0e,
 490        mm_jalrs16_op = 0x0f,
 491        mm_jraddiusp_op = 0x18,
 492};
 493
 494/*
 495 * (microMIPS) POOL16D minor opcodes.
 496 */
 497enum mm_16d_minor_op {
 498        mm_addius5_func,
 499        mm_addiusp_func,
 500};
 501
 502/*
 503 * (MIPS16e) opcodes.
 504 */
 505enum MIPS16e_ops {
 506        MIPS16e_jal_op = 003,
 507        MIPS16e_ld_op = 007,
 508        MIPS16e_i8_op = 014,
 509        MIPS16e_sd_op = 017,
 510        MIPS16e_lb_op = 020,
 511        MIPS16e_lh_op = 021,
 512        MIPS16e_lwsp_op = 022,
 513        MIPS16e_lw_op = 023,
 514        MIPS16e_lbu_op = 024,
 515        MIPS16e_lhu_op = 025,
 516        MIPS16e_lwpc_op = 026,
 517        MIPS16e_lwu_op = 027,
 518        MIPS16e_sb_op = 030,
 519        MIPS16e_sh_op = 031,
 520        MIPS16e_swsp_op = 032,
 521        MIPS16e_sw_op = 033,
 522        MIPS16e_rr_op = 035,
 523        MIPS16e_extend_op = 036,
 524        MIPS16e_i64_op = 037,
 525};
 526
 527enum MIPS16e_i64_func {
 528        MIPS16e_ldsp_func,
 529        MIPS16e_sdsp_func,
 530        MIPS16e_sdrasp_func,
 531        MIPS16e_dadjsp_func,
 532        MIPS16e_ldpc_func,
 533};
 534
 535enum MIPS16e_rr_func {
 536        MIPS16e_jr_func,
 537};
 538
 539enum MIPS6e_i8_func {
 540        MIPS16e_swrasp_func = 02,
 541};
 542
 543/*
 544 * (microMIPS) NOP instruction.
 545 */
 546#define MM_NOP16        0x0c00
 547
 548struct j_format {
 549        __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
 550        __BITFIELD_FIELD(unsigned int target : 26,
 551        ;))
 552};
 553
 554struct i_format {                       /* signed immediate format */
 555        __BITFIELD_FIELD(unsigned int opcode : 6,
 556        __BITFIELD_FIELD(unsigned int rs : 5,
 557        __BITFIELD_FIELD(unsigned int rt : 5,
 558        __BITFIELD_FIELD(signed int simmediate : 16,
 559        ;))))
 560};
 561
 562struct u_format {                       /* unsigned immediate format */
 563        __BITFIELD_FIELD(unsigned int opcode : 6,
 564        __BITFIELD_FIELD(unsigned int rs : 5,
 565        __BITFIELD_FIELD(unsigned int rt : 5,
 566        __BITFIELD_FIELD(unsigned int uimmediate : 16,
 567        ;))))
 568};
 569
 570struct c_format {                       /* Cache (>= R6000) format */
 571        __BITFIELD_FIELD(unsigned int opcode : 6,
 572        __BITFIELD_FIELD(unsigned int rs : 5,
 573        __BITFIELD_FIELD(unsigned int c_op : 3,
 574        __BITFIELD_FIELD(unsigned int cache : 2,
 575        __BITFIELD_FIELD(unsigned int simmediate : 16,
 576        ;)))))
 577};
 578
 579struct r_format {                       /* Register format */
 580        __BITFIELD_FIELD(unsigned int opcode : 6,
 581        __BITFIELD_FIELD(unsigned int rs : 5,
 582        __BITFIELD_FIELD(unsigned int rt : 5,
 583        __BITFIELD_FIELD(unsigned int rd : 5,
 584        __BITFIELD_FIELD(unsigned int re : 5,
 585        __BITFIELD_FIELD(unsigned int func : 6,
 586        ;))))))
 587};
 588
 589struct p_format {               /* Performance counter format (R10000) */
 590        __BITFIELD_FIELD(unsigned int opcode : 6,
 591        __BITFIELD_FIELD(unsigned int rs : 5,
 592        __BITFIELD_FIELD(unsigned int rt : 5,
 593        __BITFIELD_FIELD(unsigned int rd : 5,
 594        __BITFIELD_FIELD(unsigned int re : 5,
 595        __BITFIELD_FIELD(unsigned int func : 6,
 596        ;))))))
 597};
 598
 599struct f_format {                       /* FPU register format */
 600        __BITFIELD_FIELD(unsigned int opcode : 6,
 601        __BITFIELD_FIELD(unsigned int : 1,
 602        __BITFIELD_FIELD(unsigned int fmt : 4,
 603        __BITFIELD_FIELD(unsigned int rt : 5,
 604        __BITFIELD_FIELD(unsigned int rd : 5,
 605        __BITFIELD_FIELD(unsigned int re : 5,
 606        __BITFIELD_FIELD(unsigned int func : 6,
 607        ;)))))))
 608};
 609
 610struct ma_format {              /* FPU multiply and add format (MIPS IV) */
 611        __BITFIELD_FIELD(unsigned int opcode : 6,
 612        __BITFIELD_FIELD(unsigned int fr : 5,
 613        __BITFIELD_FIELD(unsigned int ft : 5,
 614        __BITFIELD_FIELD(unsigned int fs : 5,
 615        __BITFIELD_FIELD(unsigned int fd : 5,
 616        __BITFIELD_FIELD(unsigned int func : 4,
 617        __BITFIELD_FIELD(unsigned int fmt : 2,
 618        ;)))))))
 619};
 620
 621struct b_format {                       /* BREAK and SYSCALL */
 622        __BITFIELD_FIELD(unsigned int opcode : 6,
 623        __BITFIELD_FIELD(unsigned int code : 20,
 624        __BITFIELD_FIELD(unsigned int func : 6,
 625        ;)))
 626};
 627
 628struct ps_format {                      /* MIPS-3D / paired single format */
 629        __BITFIELD_FIELD(unsigned int opcode : 6,
 630        __BITFIELD_FIELD(unsigned int rs : 5,
 631        __BITFIELD_FIELD(unsigned int ft : 5,
 632        __BITFIELD_FIELD(unsigned int fs : 5,
 633        __BITFIELD_FIELD(unsigned int fd : 5,
 634        __BITFIELD_FIELD(unsigned int func : 6,
 635        ;))))))
 636};
 637
 638struct v_format {                               /* MDMX vector format */
 639        __BITFIELD_FIELD(unsigned int opcode : 6,
 640        __BITFIELD_FIELD(unsigned int sel : 4,
 641        __BITFIELD_FIELD(unsigned int fmt : 1,
 642        __BITFIELD_FIELD(unsigned int vt : 5,
 643        __BITFIELD_FIELD(unsigned int vs : 5,
 644        __BITFIELD_FIELD(unsigned int vd : 5,
 645        __BITFIELD_FIELD(unsigned int func : 6,
 646        ;)))))))
 647};
 648
 649struct msa_mi10_format {                /* MSA MI10 */
 650        __BITFIELD_FIELD(unsigned int opcode : 6,
 651        __BITFIELD_FIELD(signed int s10 : 10,
 652        __BITFIELD_FIELD(unsigned int rs : 5,
 653        __BITFIELD_FIELD(unsigned int wd : 5,
 654        __BITFIELD_FIELD(unsigned int func : 4,
 655        __BITFIELD_FIELD(unsigned int df : 2,
 656        ;))))))
 657};
 658
 659struct spec3_format {   /* SPEC3 */
 660        __BITFIELD_FIELD(unsigned int opcode:6,
 661        __BITFIELD_FIELD(unsigned int rs:5,
 662        __BITFIELD_FIELD(unsigned int rt:5,
 663        __BITFIELD_FIELD(signed int simmediate:9,
 664        __BITFIELD_FIELD(unsigned int func:7,
 665        ;)))))
 666};
 667
 668/*
 669 * microMIPS instruction formats (32-bit length)
 670 *
 671 * NOTE:
 672 *      Parenthesis denote whether the format is a microMIPS instruction or
 673 *      if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
 674 */
 675struct fb_format {              /* FPU branch format (MIPS32) */
 676        __BITFIELD_FIELD(unsigned int opcode : 6,
 677        __BITFIELD_FIELD(unsigned int bc : 5,
 678        __BITFIELD_FIELD(unsigned int cc : 3,
 679        __BITFIELD_FIELD(unsigned int flag : 2,
 680        __BITFIELD_FIELD(signed int simmediate : 16,
 681        ;)))))
 682};
 683
 684struct fp0_format {             /* FPU multiply and add format (MIPS32) */
 685        __BITFIELD_FIELD(unsigned int opcode : 6,
 686        __BITFIELD_FIELD(unsigned int fmt : 5,
 687        __BITFIELD_FIELD(unsigned int ft : 5,
 688        __BITFIELD_FIELD(unsigned int fs : 5,
 689        __BITFIELD_FIELD(unsigned int fd : 5,
 690        __BITFIELD_FIELD(unsigned int func : 6,
 691        ;))))))
 692};
 693
 694struct mm_fp0_format {          /* FPU multiply and add format (microMIPS) */
 695        __BITFIELD_FIELD(unsigned int opcode : 6,
 696        __BITFIELD_FIELD(unsigned int ft : 5,
 697        __BITFIELD_FIELD(unsigned int fs : 5,
 698        __BITFIELD_FIELD(unsigned int fd : 5,
 699        __BITFIELD_FIELD(unsigned int fmt : 3,
 700        __BITFIELD_FIELD(unsigned int op : 2,
 701        __BITFIELD_FIELD(unsigned int func : 6,
 702        ;)))))))
 703};
 704
 705struct fp1_format {             /* FPU mfc1 and cfc1 format (MIPS32) */
 706        __BITFIELD_FIELD(unsigned int opcode : 6,
 707        __BITFIELD_FIELD(unsigned int op : 5,
 708        __BITFIELD_FIELD(unsigned int rt : 5,
 709        __BITFIELD_FIELD(unsigned int fs : 5,
 710        __BITFIELD_FIELD(unsigned int fd : 5,
 711        __BITFIELD_FIELD(unsigned int func : 6,
 712        ;))))))
 713};
 714
 715struct mm_fp1_format {          /* FPU mfc1 and cfc1 format (microMIPS) */
 716        __BITFIELD_FIELD(unsigned int opcode : 6,
 717        __BITFIELD_FIELD(unsigned int rt : 5,
 718        __BITFIELD_FIELD(unsigned int fs : 5,
 719        __BITFIELD_FIELD(unsigned int fmt : 2,
 720        __BITFIELD_FIELD(unsigned int op : 8,
 721        __BITFIELD_FIELD(unsigned int func : 6,
 722        ;))))))
 723};
 724
 725struct mm_fp2_format {          /* FPU movt and movf format (microMIPS) */
 726        __BITFIELD_FIELD(unsigned int opcode : 6,
 727        __BITFIELD_FIELD(unsigned int fd : 5,
 728        __BITFIELD_FIELD(unsigned int fs : 5,
 729        __BITFIELD_FIELD(unsigned int cc : 3,
 730        __BITFIELD_FIELD(unsigned int zero : 2,
 731        __BITFIELD_FIELD(unsigned int fmt : 2,
 732        __BITFIELD_FIELD(unsigned int op : 3,
 733        __BITFIELD_FIELD(unsigned int func : 6,
 734        ;))))))))
 735};
 736
 737struct mm_fp3_format {          /* FPU abs and neg format (microMIPS) */
 738        __BITFIELD_FIELD(unsigned int opcode : 6,
 739        __BITFIELD_FIELD(unsigned int rt : 5,
 740        __BITFIELD_FIELD(unsigned int fs : 5,
 741        __BITFIELD_FIELD(unsigned int fmt : 3,
 742        __BITFIELD_FIELD(unsigned int op : 7,
 743        __BITFIELD_FIELD(unsigned int func : 6,
 744        ;))))))
 745};
 746
 747struct mm_fp4_format {          /* FPU c.cond format (microMIPS) */
 748        __BITFIELD_FIELD(unsigned int opcode : 6,
 749        __BITFIELD_FIELD(unsigned int rt : 5,
 750        __BITFIELD_FIELD(unsigned int fs : 5,
 751        __BITFIELD_FIELD(unsigned int cc : 3,
 752        __BITFIELD_FIELD(unsigned int fmt : 3,
 753        __BITFIELD_FIELD(unsigned int cond : 4,
 754        __BITFIELD_FIELD(unsigned int func : 6,
 755        ;)))))))
 756};
 757
 758struct mm_fp5_format {          /* FPU lwxc1 and swxc1 format (microMIPS) */
 759        __BITFIELD_FIELD(unsigned int opcode : 6,
 760        __BITFIELD_FIELD(unsigned int index : 5,
 761        __BITFIELD_FIELD(unsigned int base : 5,
 762        __BITFIELD_FIELD(unsigned int fd : 5,
 763        __BITFIELD_FIELD(unsigned int op : 5,
 764        __BITFIELD_FIELD(unsigned int func : 6,
 765        ;))))))
 766};
 767
 768struct fp6_format {             /* FPU madd and msub format (MIPS IV) */
 769        __BITFIELD_FIELD(unsigned int opcode : 6,
 770        __BITFIELD_FIELD(unsigned int fr : 5,
 771        __BITFIELD_FIELD(unsigned int ft : 5,
 772        __BITFIELD_FIELD(unsigned int fs : 5,
 773        __BITFIELD_FIELD(unsigned int fd : 5,
 774        __BITFIELD_FIELD(unsigned int func : 6,
 775        ;))))))
 776};
 777
 778struct mm_fp6_format {          /* FPU madd and msub format (microMIPS) */
 779        __BITFIELD_FIELD(unsigned int opcode : 6,
 780        __BITFIELD_FIELD(unsigned int ft : 5,
 781        __BITFIELD_FIELD(unsigned int fs : 5,
 782        __BITFIELD_FIELD(unsigned int fd : 5,
 783        __BITFIELD_FIELD(unsigned int fr : 5,
 784        __BITFIELD_FIELD(unsigned int func : 6,
 785        ;))))))
 786};
 787
 788struct mm_i_format {            /* Immediate format (microMIPS) */
 789        __BITFIELD_FIELD(unsigned int opcode : 6,
 790        __BITFIELD_FIELD(unsigned int rt : 5,
 791        __BITFIELD_FIELD(unsigned int rs : 5,
 792        __BITFIELD_FIELD(signed int simmediate : 16,
 793        ;))))
 794};
 795
 796struct mm_m_format {            /* Multi-word load/store format (microMIPS) */
 797        __BITFIELD_FIELD(unsigned int opcode : 6,
 798        __BITFIELD_FIELD(unsigned int rd : 5,
 799        __BITFIELD_FIELD(unsigned int base : 5,
 800        __BITFIELD_FIELD(unsigned int func : 4,
 801        __BITFIELD_FIELD(signed int simmediate : 12,
 802        ;)))))
 803};
 804
 805struct mm_x_format {            /* Scaled indexed load format (microMIPS) */
 806        __BITFIELD_FIELD(unsigned int opcode : 6,
 807        __BITFIELD_FIELD(unsigned int index : 5,
 808        __BITFIELD_FIELD(unsigned int base : 5,
 809        __BITFIELD_FIELD(unsigned int rd : 5,
 810        __BITFIELD_FIELD(unsigned int func : 11,
 811        ;)))))
 812};
 813
 814struct mm_a_format {            /* ADDIUPC format (microMIPS) */
 815        __BITFIELD_FIELD(unsigned int opcode : 6,
 816        __BITFIELD_FIELD(unsigned int rs : 3,
 817        __BITFIELD_FIELD(signed int simmediate : 23,
 818        ;)))
 819};
 820
 821/*
 822 * microMIPS instruction formats (16-bit length)
 823 */
 824struct mm_b0_format {           /* Unconditional branch format (microMIPS) */
 825        __BITFIELD_FIELD(unsigned int opcode : 6,
 826        __BITFIELD_FIELD(signed int simmediate : 10,
 827        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 828        ;)))
 829};
 830
 831struct mm_b1_format {           /* Conditional branch format (microMIPS) */
 832        __BITFIELD_FIELD(unsigned int opcode : 6,
 833        __BITFIELD_FIELD(unsigned int rs : 3,
 834        __BITFIELD_FIELD(signed int simmediate : 7,
 835        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 836        ;))))
 837};
 838
 839struct mm16_m_format {          /* Multi-word load/store format */
 840        __BITFIELD_FIELD(unsigned int opcode : 6,
 841        __BITFIELD_FIELD(unsigned int func : 4,
 842        __BITFIELD_FIELD(unsigned int rlist : 2,
 843        __BITFIELD_FIELD(unsigned int imm : 4,
 844        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 845        ;)))))
 846};
 847
 848struct mm16_rb_format {         /* Signed immediate format */
 849        __BITFIELD_FIELD(unsigned int opcode : 6,
 850        __BITFIELD_FIELD(unsigned int rt : 3,
 851        __BITFIELD_FIELD(unsigned int base : 3,
 852        __BITFIELD_FIELD(signed int simmediate : 4,
 853        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 854        ;)))))
 855};
 856
 857struct mm16_r3_format {         /* Load from global pointer format */
 858        __BITFIELD_FIELD(unsigned int opcode : 6,
 859        __BITFIELD_FIELD(unsigned int rt : 3,
 860        __BITFIELD_FIELD(signed int simmediate : 7,
 861        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 862        ;))))
 863};
 864
 865struct mm16_r5_format {         /* Load/store from stack pointer format */
 866        __BITFIELD_FIELD(unsigned int opcode : 6,
 867        __BITFIELD_FIELD(unsigned int rt : 5,
 868        __BITFIELD_FIELD(signed int simmediate : 5,
 869        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 870        ;))))
 871};
 872
 873/*
 874 * MIPS16e instruction formats (16-bit length)
 875 */
 876struct m16e_rr {
 877        __BITFIELD_FIELD(unsigned int opcode : 5,
 878        __BITFIELD_FIELD(unsigned int rx : 3,
 879        __BITFIELD_FIELD(unsigned int nd : 1,
 880        __BITFIELD_FIELD(unsigned int l : 1,
 881        __BITFIELD_FIELD(unsigned int ra : 1,
 882        __BITFIELD_FIELD(unsigned int func : 5,
 883        ;))))))
 884};
 885
 886struct m16e_jal {
 887        __BITFIELD_FIELD(unsigned int opcode : 5,
 888        __BITFIELD_FIELD(unsigned int x : 1,
 889        __BITFIELD_FIELD(unsigned int imm20_16 : 5,
 890        __BITFIELD_FIELD(signed int imm25_21 : 5,
 891        ;))))
 892};
 893
 894struct m16e_i64 {
 895        __BITFIELD_FIELD(unsigned int opcode : 5,
 896        __BITFIELD_FIELD(unsigned int func : 3,
 897        __BITFIELD_FIELD(unsigned int imm : 8,
 898        ;)))
 899};
 900
 901struct m16e_ri64 {
 902        __BITFIELD_FIELD(unsigned int opcode : 5,
 903        __BITFIELD_FIELD(unsigned int func : 3,
 904        __BITFIELD_FIELD(unsigned int ry : 3,
 905        __BITFIELD_FIELD(unsigned int imm : 5,
 906        ;))))
 907};
 908
 909struct m16e_ri {
 910        __BITFIELD_FIELD(unsigned int opcode : 5,
 911        __BITFIELD_FIELD(unsigned int rx : 3,
 912        __BITFIELD_FIELD(unsigned int imm : 8,
 913        ;)))
 914};
 915
 916struct m16e_rri {
 917        __BITFIELD_FIELD(unsigned int opcode : 5,
 918        __BITFIELD_FIELD(unsigned int rx : 3,
 919        __BITFIELD_FIELD(unsigned int ry : 3,
 920        __BITFIELD_FIELD(unsigned int imm : 5,
 921        ;))))
 922};
 923
 924struct m16e_i8 {
 925        __BITFIELD_FIELD(unsigned int opcode : 5,
 926        __BITFIELD_FIELD(unsigned int func : 3,
 927        __BITFIELD_FIELD(unsigned int imm : 8,
 928        ;)))
 929};
 930
 931union mips_instruction {
 932        unsigned int word;
 933        unsigned short halfword[2];
 934        unsigned char byte[4];
 935        struct j_format j_format;
 936        struct i_format i_format;
 937        struct u_format u_format;
 938        struct c_format c_format;
 939        struct r_format r_format;
 940        struct p_format p_format;
 941        struct f_format f_format;
 942        struct ma_format ma_format;
 943        struct msa_mi10_format msa_mi10_format;
 944        struct b_format b_format;
 945        struct ps_format ps_format;
 946        struct v_format v_format;
 947        struct spec3_format spec3_format;
 948        struct fb_format fb_format;
 949        struct fp0_format fp0_format;
 950        struct mm_fp0_format mm_fp0_format;
 951        struct fp1_format fp1_format;
 952        struct mm_fp1_format mm_fp1_format;
 953        struct mm_fp2_format mm_fp2_format;
 954        struct mm_fp3_format mm_fp3_format;
 955        struct mm_fp4_format mm_fp4_format;
 956        struct mm_fp5_format mm_fp5_format;
 957        struct fp6_format fp6_format;
 958        struct mm_fp6_format mm_fp6_format;
 959        struct mm_i_format mm_i_format;
 960        struct mm_m_format mm_m_format;
 961        struct mm_x_format mm_x_format;
 962        struct mm_a_format mm_a_format;
 963        struct mm_b0_format mm_b0_format;
 964        struct mm_b1_format mm_b1_format;
 965        struct mm16_m_format mm16_m_format ;
 966        struct mm16_rb_format mm16_rb_format;
 967        struct mm16_r3_format mm16_r3_format;
 968        struct mm16_r5_format mm16_r5_format;
 969};
 970
 971union mips16e_instruction {
 972        unsigned int full : 16;
 973        struct m16e_rr rr;
 974        struct m16e_jal jal;
 975        struct m16e_i64 i64;
 976        struct m16e_ri64 ri64;
 977        struct m16e_ri ri;
 978        struct m16e_rri rri;
 979        struct m16e_i8 i8;
 980};
 981
 982#endif /* _UAPI_ASM_INST_H */
 983