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16enum fields {
17 RS = 0x001,
18 RT = 0x002,
19 RD = 0x004,
20 RE = 0x008,
21 SIMM = 0x010,
22 UIMM = 0x020,
23 BIMM = 0x040,
24 JIMM = 0x080,
25 FUNC = 0x100,
26 SET = 0x200,
27 SCIMM = 0x400,
28 SIMM9 = 0x800,
29};
30
31#define OP_MASK 0x3f
32#define OP_SH 26
33#define RD_MASK 0x1f
34#define RD_SH 11
35#define RE_MASK 0x1f
36#define RE_SH 6
37#define IMM_MASK 0xffff
38#define IMM_SH 0
39#define JIMM_MASK 0x3ffffff
40#define JIMM_SH 0
41#define FUNC_MASK 0x3f
42#define FUNC_SH 0
43#define SET_MASK 0x7
44#define SET_SH 0
45#define SIMM9_SH 7
46#define SIMM9_MASK 0x1ff
47
48enum opcode {
49 insn_invalid,
50 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
51 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
52 insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
53 insn_divu, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
54 insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
55 insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb,
56 insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,
57 insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0,
58 insn_mthc0, insn_mul, insn_or, insn_ori, insn_pref, insn_rfe,
59 insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_slt,
60 insn_sltiu, insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu,
61 insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi,
62 insn_tlbwr, insn_wait, insn_wsbh, insn_xor, insn_xori, insn_yield,
63 insn_lddir, insn_ldpte,
64};
65
66struct insn {
67 enum opcode opcode;
68 u32 match;
69 enum fields fields;
70};
71
72static inline u32 build_rs(u32 arg)
73{
74 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
75
76 return (arg & RS_MASK) << RS_SH;
77}
78
79static inline u32 build_rt(u32 arg)
80{
81 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
82
83 return (arg & RT_MASK) << RT_SH;
84}
85
86static inline u32 build_rd(u32 arg)
87{
88 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
89
90 return (arg & RD_MASK) << RD_SH;
91}
92
93static inline u32 build_re(u32 arg)
94{
95 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
96
97 return (arg & RE_MASK) << RE_SH;
98}
99
100static inline u32 build_simm(s32 arg)
101{
102 WARN(arg > 0x7fff || arg < -0x8000,
103 KERN_WARNING "Micro-assembler field overflow\n");
104
105 return arg & 0xffff;
106}
107
108static inline u32 build_uimm(u32 arg)
109{
110 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
111
112 return arg & IMM_MASK;
113}
114
115static inline u32 build_scimm(u32 arg)
116{
117 WARN(arg & ~SCIMM_MASK,
118 KERN_WARNING "Micro-assembler field overflow\n");
119
120 return (arg & SCIMM_MASK) << SCIMM_SH;
121}
122
123static inline u32 build_scimm9(s32 arg)
124{
125 WARN((arg > 0xff || arg < -0x100),
126 KERN_WARNING "Micro-assembler field overflow\n");
127
128 return (arg & SIMM9_MASK) << SIMM9_SH;
129}
130
131static inline u32 build_func(u32 arg)
132{
133 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
134
135 return arg & FUNC_MASK;
136}
137
138static inline u32 build_set(u32 arg)
139{
140 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
141
142 return arg & SET_MASK;
143}
144
145static void build_insn(u32 **buf, enum opcode opc, ...);
146
147#define I_u1u2u3(op) \
148Ip_u1u2u3(op) \
149{ \
150 build_insn(buf, insn##op, a, b, c); \
151} \
152UASM_EXPORT_SYMBOL(uasm_i##op);
153
154#define I_s3s1s2(op) \
155Ip_s3s1s2(op) \
156{ \
157 build_insn(buf, insn##op, b, c, a); \
158} \
159UASM_EXPORT_SYMBOL(uasm_i##op);
160
161#define I_u2u1u3(op) \
162Ip_u2u1u3(op) \
163{ \
164 build_insn(buf, insn##op, b, a, c); \
165} \
166UASM_EXPORT_SYMBOL(uasm_i##op);
167
168#define I_u3u2u1(op) \
169Ip_u3u2u1(op) \
170{ \
171 build_insn(buf, insn##op, c, b, a); \
172} \
173UASM_EXPORT_SYMBOL(uasm_i##op);
174
175#define I_u3u1u2(op) \
176Ip_u3u1u2(op) \
177{ \
178 build_insn(buf, insn##op, b, c, a); \
179} \
180UASM_EXPORT_SYMBOL(uasm_i##op);
181
182#define I_u1u2s3(op) \
183Ip_u1u2s3(op) \
184{ \
185 build_insn(buf, insn##op, a, b, c); \
186} \
187UASM_EXPORT_SYMBOL(uasm_i##op);
188
189#define I_u2s3u1(op) \
190Ip_u2s3u1(op) \
191{ \
192 build_insn(buf, insn##op, c, a, b); \
193} \
194UASM_EXPORT_SYMBOL(uasm_i##op);
195
196#define I_u2u1s3(op) \
197Ip_u2u1s3(op) \
198{ \
199 build_insn(buf, insn##op, b, a, c); \
200} \
201UASM_EXPORT_SYMBOL(uasm_i##op);
202
203#define I_u2u1msbu3(op) \
204Ip_u2u1msbu3(op) \
205{ \
206 build_insn(buf, insn##op, b, a, c+d-1, c); \
207} \
208UASM_EXPORT_SYMBOL(uasm_i##op);
209
210#define I_u2u1msb32u3(op) \
211Ip_u2u1msbu3(op) \
212{ \
213 build_insn(buf, insn##op, b, a, c+d-33, c); \
214} \
215UASM_EXPORT_SYMBOL(uasm_i##op);
216
217#define I_u2u1msbdu3(op) \
218Ip_u2u1msbu3(op) \
219{ \
220 build_insn(buf, insn##op, b, a, d-1, c); \
221} \
222UASM_EXPORT_SYMBOL(uasm_i##op);
223
224#define I_u1u2(op) \
225Ip_u1u2(op) \
226{ \
227 build_insn(buf, insn##op, a, b); \
228} \
229UASM_EXPORT_SYMBOL(uasm_i##op);
230
231#define I_u2u1(op) \
232Ip_u1u2(op) \
233{ \
234 build_insn(buf, insn##op, b, a); \
235} \
236UASM_EXPORT_SYMBOL(uasm_i##op);
237
238#define I_u1s2(op) \
239Ip_u1s2(op) \
240{ \
241 build_insn(buf, insn##op, a, b); \
242} \
243UASM_EXPORT_SYMBOL(uasm_i##op);
244
245#define I_u1(op) \
246Ip_u1(op) \
247{ \
248 build_insn(buf, insn##op, a); \
249} \
250UASM_EXPORT_SYMBOL(uasm_i##op);
251
252#define I_0(op) \
253Ip_0(op) \
254{ \
255 build_insn(buf, insn##op); \
256} \
257UASM_EXPORT_SYMBOL(uasm_i##op);
258
259I_u2u1s3(_addiu)
260I_u3u1u2(_addu)
261I_u2u1u3(_andi)
262I_u3u1u2(_and)
263I_u1u2s3(_beq)
264I_u1u2s3(_beql)
265I_u1s2(_bgez)
266I_u1s2(_bgezl)
267I_u1s2(_bltz)
268I_u1s2(_bltzl)
269I_u1u2s3(_bne)
270I_u2s3u1(_cache)
271I_u1u2u3(_dmfc0)
272I_u1u2u3(_dmtc0)
273I_u2u1s3(_daddiu)
274I_u3u1u2(_daddu)
275I_u1u2(_divu)
276I_u2u1u3(_dsll)
277I_u2u1u3(_dsll32)
278I_u2u1u3(_dsra)
279I_u2u1u3(_dsrl)
280I_u2u1u3(_dsrl32)
281I_u2u1u3(_drotr)
282I_u2u1u3(_drotr32)
283I_u3u1u2(_dsubu)
284I_0(_eret)
285I_u2u1msbdu3(_ext)
286I_u2u1msbu3(_ins)
287I_u1(_j)
288I_u1(_jal)
289I_u2u1(_jalr)
290I_u1(_jr)
291I_u2s3u1(_lb)
292I_u2s3u1(_ld)
293I_u2s3u1(_lh)
294I_u2s3u1(_ll)
295I_u2s3u1(_lld)
296I_u1s2(_lui)
297I_u2s3u1(_lw)
298I_u1u2u3(_mfc0)
299I_u1u2u3(_mfhc0)
300I_u1(_mfhi)
301I_u1(_mflo)
302I_u1u2u3(_mtc0)
303I_u1u2u3(_mthc0)
304I_u3u1u2(_mul)
305I_u2u1u3(_ori)
306I_u3u1u2(_or)
307I_0(_rfe)
308I_u2s3u1(_sc)
309I_u2s3u1(_scd)
310I_u2s3u1(_sd)
311I_u2u1u3(_sll)
312I_u3u2u1(_sllv)
313I_s3s1s2(_slt)
314I_u2u1s3(_sltiu)
315I_u3u1u2(_sltu)
316I_u2u1u3(_sra)
317I_u2u1u3(_srl)
318I_u3u2u1(_srlv)
319I_u2u1u3(_rotr)
320I_u3u1u2(_subu)
321I_u2s3u1(_sw)
322I_u1(_sync)
323I_0(_tlbp)
324I_0(_tlbr)
325I_0(_tlbwi)
326I_0(_tlbwr)
327I_u1(_wait);
328I_u2u1(_wsbh)
329I_u3u1u2(_xor)
330I_u2u1u3(_xori)
331I_u2u1(_yield)
332I_u2u1msbu3(_dins);
333I_u2u1msb32u3(_dinsm);
334I_u1(_syscall);
335I_u1u2s3(_bbit0);
336I_u1u2s3(_bbit1);
337I_u3u1u2(_lwx)
338I_u3u1u2(_ldx)
339I_u1u2(_ldpte)
340I_u2u1u3(_lddir)
341
342#ifdef CONFIG_CPU_CAVIUM_OCTEON
343#include <asm/octeon/octeon.h>
344void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
345 unsigned int c)
346{
347 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)
348
349
350
351
352 build_insn(buf, insn_pref, c, 28, b);
353 else
354 build_insn(buf, insn_pref, c, a, b);
355}
356UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
357#else
358I_u2s3u1(_pref)
359#endif
360
361
362void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
363{
364 (*lab)->addr = addr;
365 (*lab)->lab = lid;
366 (*lab)++;
367}
368UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
369
370int ISAFUNC(uasm_in_compat_space_p)(long addr)
371{
372
373#ifdef CONFIG_64BIT
374 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
375#else
376 return 1;
377#endif
378}
379UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
380
381static int uasm_rel_highest(long val)
382{
383#ifdef CONFIG_64BIT
384 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
385#else
386 return 0;
387#endif
388}
389
390static int uasm_rel_higher(long val)
391{
392#ifdef CONFIG_64BIT
393 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
394#else
395 return 0;
396#endif
397}
398
399int ISAFUNC(uasm_rel_hi)(long val)
400{
401 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
402}
403UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
404
405int ISAFUNC(uasm_rel_lo)(long val)
406{
407 return ((val & 0xffff) ^ 0x8000) - 0x8000;
408}
409UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
410
411void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
412{
413 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
414 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
415 if (uasm_rel_higher(addr))
416 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
417 if (ISAFUNC(uasm_rel_hi(addr))) {
418 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
419 ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
420 ISAFUNC(uasm_rel_hi)(addr));
421 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
422 } else
423 ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
424 } else
425 ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
426}
427UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
428
429void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
430{
431 ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
432 if (ISAFUNC(uasm_rel_lo(addr))) {
433 if (!ISAFUNC(uasm_in_compat_space_p)(addr))
434 ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
435 ISAFUNC(uasm_rel_lo(addr)));
436 else
437 ISAFUNC(uasm_i_addiu)(buf, rs, rs,
438 ISAFUNC(uasm_rel_lo(addr)));
439 }
440}
441UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
442
443
444void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
445{
446 (*rel)->addr = addr;
447 (*rel)->type = R_MIPS_PC16;
448 (*rel)->lab = lid;
449 (*rel)++;
450}
451UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
452
453static inline void __resolve_relocs(struct uasm_reloc *rel,
454 struct uasm_label *lab);
455
456void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
457 struct uasm_label *lab)
458{
459 struct uasm_label *l;
460
461 for (; rel->lab != UASM_LABEL_INVALID; rel++)
462 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
463 if (rel->lab == l->lab)
464 __resolve_relocs(rel, l);
465}
466UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
467
468void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
469 long off)
470{
471 for (; rel->lab != UASM_LABEL_INVALID; rel++)
472 if (rel->addr >= first && rel->addr < end)
473 rel->addr += off;
474}
475UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
476
477void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
478 long off)
479{
480 for (; lab->lab != UASM_LABEL_INVALID; lab++)
481 if (lab->addr >= first && lab->addr < end)
482 lab->addr += off;
483}
484UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
485
486void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
487 u32 *first, u32 *end, u32 *target)
488{
489 long off = (long)(target - first);
490
491 memcpy(target, first, (end - first) * sizeof(u32));
492
493 ISAFUNC(uasm_move_relocs(rel, first, end, off));
494 ISAFUNC(uasm_move_labels(lab, first, end, off));
495}
496UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
497
498int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
499{
500 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
501 if (rel->addr == addr
502 && (rel->type == R_MIPS_PC16
503 || rel->type == R_MIPS_26))
504 return 1;
505 }
506
507 return 0;
508}
509UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
510
511
512void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
513 int lid)
514{
515 uasm_r_mips_pc16(r, *p, lid);
516 ISAFUNC(uasm_i_bltz)(p, reg, 0);
517}
518UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
519
520void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
521{
522 uasm_r_mips_pc16(r, *p, lid);
523 ISAFUNC(uasm_i_b)(p, 0);
524}
525UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
526
527void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1,
528 unsigned int r2, int lid)
529{
530 uasm_r_mips_pc16(r, *p, lid);
531 ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
532}
533UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));
534
535void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
536 int lid)
537{
538 uasm_r_mips_pc16(r, *p, lid);
539 ISAFUNC(uasm_i_beqz)(p, reg, 0);
540}
541UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
542
543void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
544 int lid)
545{
546 uasm_r_mips_pc16(r, *p, lid);
547 ISAFUNC(uasm_i_beqzl)(p, reg, 0);
548}
549UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
550
551void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
552 unsigned int reg2, int lid)
553{
554 uasm_r_mips_pc16(r, *p, lid);
555 ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
556}
557UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
558
559void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
560 int lid)
561{
562 uasm_r_mips_pc16(r, *p, lid);
563 ISAFUNC(uasm_i_bnez)(p, reg, 0);
564}
565UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
566
567void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
568 int lid)
569{
570 uasm_r_mips_pc16(r, *p, lid);
571 ISAFUNC(uasm_i_bgezl)(p, reg, 0);
572}
573UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
574
575void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
576 int lid)
577{
578 uasm_r_mips_pc16(r, *p, lid);
579 ISAFUNC(uasm_i_bgez)(p, reg, 0);
580}
581UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
582
583void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
584 unsigned int bit, int lid)
585{
586 uasm_r_mips_pc16(r, *p, lid);
587 ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
588}
589UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
590
591void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
592 unsigned int bit, int lid)
593{
594 uasm_r_mips_pc16(r, *p, lid);
595 ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
596}
597UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));
598
