LXR linux/arch/powerpc/include/asm/mpc5121.h

   1/*
   2 * MPC5121 Prototypes and definitions
   3 *
   4 * This file is licensed under the terms of the GNU General Public
   5 * License version 2.
   6 */
   7
   8#ifndef __ASM_POWERPC_MPC5121_H__
   9#define __ASM_POWERPC_MPC5121_H__
  10
  11/* MPC512x Reset module registers */
  12struct mpc512x_reset_module {
  13        u32     rcwlr;  /* Reset Configuration Word Low Register */
  14        u32     rcwhr;  /* Reset Configuration Word High Register */
  15        u32     reserved1;
  16        u32     reserved2;
  17        u32     rsr;    /* Reset Status Register */
  18        u32     rmr;    /* Reset Mode Register */
  19        u32     rpr;    /* Reset Protection Register */
  20        u32     rcr;    /* Reset Control Register */
  21        u32     rcer;   /* Reset Control Enable Register */
  22};
  23
  24/*
  25 * Clock Control Module
  26 */
  27struct mpc512x_ccm {
  28        u32     spmr;   /* System PLL Mode Register */
  29        u32     sccr1;  /* System Clock Control Register 1 */
  30        u32     sccr2;  /* System Clock Control Register 2 */
  31        u32     scfr1;  /* System Clock Frequency Register 1 */
  32        u32     scfr2;  /* System Clock Frequency Register 2 */
  33        u32     scfr2s; /* System Clock Frequency Shadow Register 2 */
  34        u32     bcr;    /* Bread Crumb Register */
  35        u32     psc_ccr[12];    /* PSC Clock Control Registers */
  36        u32     spccr;  /* SPDIF Clock Control Register */
  37        u32     cccr;   /* CFM Clock Control Register */
  38        u32     dccr;   /* DIU Clock Control Register */
  39        u32     mscan_ccr[4];   /* MSCAN Clock Control Registers */
  40        u32     out_ccr[4];     /* OUT CLK Configure Registers */
  41        u32     rsv0[2];        /* Reserved */
  42        u32     scfr3;          /* System Clock Frequency Register 3 */
  43        u32     rsv1[3];        /* Reserved */
  44        u32     spll_lock_cnt;  /* System PLL Lock Counter */
  45        u8      res[0x6c];      /* Reserved */
  46};
  47
  48/*
  49 * LPC Module
  50 */
  51struct mpc512x_lpc {
  52        u32     cs_cfg[8];      /* CS config */
  53        u32     cs_ctrl;        /* CS Control Register */
  54        u32     cs_status;      /* CS Status Register */
  55        u32     burst_ctrl;     /* CS Burst Control Register */
  56        u32     deadcycle_ctrl; /* CS Deadcycle Control Register */
  57        u32     holdcycle_ctrl; /* CS Holdcycle Control Register */
  58        u32     alt;            /* Address Latch Timing Register */
  59};
  60
  61int mpc512x_cs_config(unsigned int cs, u32 val);
  62
  63/*
  64 * SCLPC Module (LPB FIFO)
  65 */
  66struct mpc512x_lpbfifo {
  67        u32     pkt_size;       /* SCLPC Packet Size Register */
  68        u32     start_addr;     /* SCLPC Start Address Register */
  69        u32     ctrl;           /* SCLPC Control Register */
  70        u32     enable;         /* SCLPC Enable Register */
  71        u32     reserved1;
  72        u32     status;         /* SCLPC Status Register */
  73        u32     bytes_done;     /* SCLPC Bytes Done Register */
  74        u32     emb_sc;         /* EMB Share Counter Register */
  75        u32     emb_pc;         /* EMB Pause Control Register */
  76        u32     reserved2[7];
  77        u32     data_word;      /* LPC RX/TX FIFO Data Word Register */
  78        u32     fifo_status;    /* LPC RX/TX FIFO Status Register */
  79        u32     fifo_ctrl;      /* LPC RX/TX FIFO Control Register */
  80        u32     fifo_alarm;     /* LPC RX/TX FIFO Alarm Register */
  81};
  82
  83#define MPC512X_SCLPC_START             (1 << 31)
  84#define MPC512X_SCLPC_CS(x)             (((x) & 0x7) << 24)
  85#define MPC512X_SCLPC_FLUSH             (1 << 17)
  86#define MPC512X_SCLPC_READ              (1 << 16)
  87#define MPC512X_SCLPC_DAI               (1 << 8)
  88#define MPC512X_SCLPC_BPT(x)            ((x) & 0x3f)
  89#define MPC512X_SCLPC_RESET             (1 << 24)
  90#define MPC512X_SCLPC_FIFO_RESET        (1 << 16)
  91#define MPC512X_SCLPC_ABORT_INT_ENABLE  (1 << 9)
  92#define MPC512X_SCLPC_NORM_INT_ENABLE   (1 << 8)
  93#define MPC512X_SCLPC_ENABLE            (1 << 0)
  94#define MPC512X_SCLPC_SUCCESS           (1 << 24)
  95#define MPC512X_SCLPC_FIFO_CTRL(x)      (((x) & 0x7) << 24)
  96#define MPC512X_SCLPC_FIFO_ALARM(x)     ((x) & 0x3ff)
  97
  98enum lpb_dev_portsize {
  99        LPB_DEV_PORTSIZE_UNDEFINED = 0,
 100        LPB_DEV_PORTSIZE_1_BYTE = 1,
 101        LPB_DEV_PORTSIZE_2_BYTES = 2,
 102        LPB_DEV_PORTSIZE_4_BYTES = 4,
 103        LPB_DEV_PORTSIZE_8_BYTES = 8
 104};
 105
 106enum mpc512x_lpbfifo_req_dir {
 107        MPC512X_LPBFIFO_REQ_DIR_READ,
 108        MPC512X_LPBFIFO_REQ_DIR_WRITE
 109};
 110
 111struct mpc512x_lpbfifo_request {
 112        phys_addr_t dev_phys_addr; /* physical address of some device on LPB */
 113        void *ram_virt_addr; /* virtual address of some region in RAM */
 114        u32 size;
 115        enum lpb_dev_portsize portsize;
 116        enum mpc512x_lpbfifo_req_dir dir;
 117        void (*callback)(struct mpc512x_lpbfifo_request *);
 118};
 119
 120int mpc512x_lpbfifo_submit(struct mpc512x_lpbfifo_request *req);
 121
 122#endif /* __ASM_POWERPC_MPC5121_H__ */
 123