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22#include <linux/sched.h>
23#include <linux/mm.h>
24
25#include <asm/spu.h>
26#include <asm/spu_csa.h>
27
28#include "spufs.h"
29
30
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32
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34
35
36static void spufs_handle_event(struct spu_context *ctx,
37 unsigned long ea, int type)
38{
39 siginfo_t info;
40
41 if (ctx->flags & SPU_CREATE_EVENTS_ENABLED) {
42 ctx->event_return |= type;
43 wake_up_all(&ctx->stop_wq);
44 return;
45 }
46
47 memset(&info, 0, sizeof(info));
48
49 switch (type) {
50 case SPE_EVENT_INVALID_DMA:
51 info.si_signo = SIGBUS;
52 info.si_code = BUS_OBJERR;
53 break;
54 case SPE_EVENT_SPE_DATA_STORAGE:
55 info.si_signo = SIGSEGV;
56 info.si_addr = (void __user *)ea;
57 info.si_code = SEGV_ACCERR;
58 ctx->ops->restart_dma(ctx);
59 break;
60 case SPE_EVENT_DMA_ALIGNMENT:
61 info.si_signo = SIGBUS;
62
63 info.si_code = BUS_ADRALN;
64 break;
65 case SPE_EVENT_SPE_ERROR:
66 info.si_signo = SIGILL;
67 info.si_addr = (void __user *)(unsigned long)
68 ctx->ops->npc_read(ctx) - 4;
69 info.si_code = ILL_ILLOPC;
70 break;
71 }
72
73 if (info.si_signo)
74 force_sig_info(info.si_signo, &info, current);
75}
76
77int spufs_handle_class0(struct spu_context *ctx)
78{
79 unsigned long stat = ctx->csa.class_0_pending & CLASS0_INTR_MASK;
80
81 if (likely(!stat))
82 return 0;
83
84 if (stat & CLASS0_DMA_ALIGNMENT_INTR)
85 spufs_handle_event(ctx, ctx->csa.class_0_dar,
86 SPE_EVENT_DMA_ALIGNMENT);
87
88 if (stat & CLASS0_INVALID_DMA_COMMAND_INTR)
89 spufs_handle_event(ctx, ctx->csa.class_0_dar,
90 SPE_EVENT_INVALID_DMA);
91
92 if (stat & CLASS0_SPU_ERROR_INTR)
93 spufs_handle_event(ctx, ctx->csa.class_0_dar,
94 SPE_EVENT_SPE_ERROR);
95
96 ctx->csa.class_0_pending = 0;
97
98 return -EIO;
99}
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109
110int spufs_handle_class1(struct spu_context *ctx)
111{
112 u64 ea, dsisr, access;
113 unsigned long flags;
114 unsigned flt = 0;
115 int ret;
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125
126 ea = ctx->csa.class_1_dar;
127 dsisr = ctx->csa.class_1_dsisr;
128
129 if (!(dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED)))
130 return 0;
131
132 spuctx_switch_state(ctx, SPU_UTIL_IOWAIT);
133
134 pr_debug("ctx %p: ea %016llx, dsisr %016llx state %d\n", ctx, ea,
135 dsisr, ctx->state);
136
137 ctx->stats.hash_flt++;
138 if (ctx->state == SPU_STATE_RUNNABLE)
139 ctx->spu->stats.hash_flt++;
140
141
142 spu_release(ctx);
143
144 access = (_PAGE_PRESENT | _PAGE_READ);
145 access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_WRITE : 0UL;
146 local_irq_save(flags);
147 ret = hash_page(ea, access, 0x300, dsisr);
148 local_irq_restore(flags);
149
150
151 if (ret)
152 ret = copro_handle_mm_fault(current->mm, ea, dsisr, &flt);
153
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158 mutex_lock(&ctx->state_mutex);
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165 ctx->csa.class_1_dar = ctx->csa.class_1_dsisr = 0;
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172 if (!ret) {
173 if (flt & VM_FAULT_MAJOR)
174 ctx->stats.maj_flt++;
175 else
176 ctx->stats.min_flt++;
177 if (ctx->state == SPU_STATE_RUNNABLE) {
178 if (flt & VM_FAULT_MAJOR)
179 ctx->spu->stats.maj_flt++;
180 else
181 ctx->spu->stats.min_flt++;
182 }
183
184 if (ctx->spu)
185 ctx->ops->restart_dma(ctx);
186 } else
187 spufs_handle_event(ctx, ea, SPE_EVENT_SPE_DATA_STORAGE);
188
189 spuctx_switch_state(ctx, SPU_UTIL_SYSTEM);
190 return ret;
191}
192