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15#ifndef _ASM_TILE_PROCESSOR_H
16#define _ASM_TILE_PROCESSOR_H
17
18#include <arch/chip.h>
19
20#ifndef __ASSEMBLY__
21
22
23
24
25
26#include <linux/types.h>
27#include <asm/ptrace.h>
28#include <asm/percpu.h>
29
30#include <arch/spr_def.h>
31
32struct task_struct;
33struct thread_struct;
34
35typedef struct {
36 unsigned long seg;
37} mm_segment_t;
38
39
40
41
42
43void *current_text_addr(void);
44
45#if CHIP_HAS_TILE_DMA()
46
47struct tile_dma_state {
48 int enabled;
49 unsigned long src;
50 unsigned long dest;
51 unsigned long strides;
52 unsigned long chunk_size;
53 unsigned long src_chunk;
54 unsigned long dest_chunk;
55 unsigned long byte;
56 unsigned long status;
57};
58
59
60
61
62
63#define DMA_STATUS_MASK \
64 (SPR_DMA_STATUS__RUNNING_MASK | SPR_DMA_STATUS__DONE_MASK)
65#endif
66
67
68
69
70
71struct async_tlb {
72 short fault_num;
73 char is_fault;
74 char is_write;
75 unsigned long address;
76};
77
78#ifdef CONFIG_HARDWALL
79struct hardwall_info;
80struct hardwall_task {
81
82 struct hardwall_info *info;
83
84 struct list_head list;
85};
86#ifdef __tilepro__
87#define HARDWALL_TYPES 1
88#else
89#define HARDWALL_TYPES 3
90#endif
91#endif
92
93struct thread_struct {
94
95 unsigned long ksp;
96
97 unsigned long pc;
98
99 unsigned long usp0;
100
101 pid_t creator_pid;
102#if CHIP_HAS_TILE_DMA()
103
104 struct tile_dma_state tile_dma_state;
105#endif
106
107 unsigned long ex_context[2];
108
109 unsigned long system_save[4];
110
111 unsigned long long interrupt_mask;
112
113 unsigned long intctrl_0;
114
115 unsigned long proc_status;
116#if !CHIP_HAS_FIXED_INTVEC_BASE()
117
118 unsigned long interrupt_vector_base;
119#endif
120
121 unsigned long tile_rtf_hwm;
122#if CHIP_HAS_DSTREAM_PF()
123
124 unsigned long dstream_pf;
125#endif
126#ifdef CONFIG_HARDWALL
127
128 struct hardwall_task hardwall[HARDWALL_TYPES];
129#endif
130#if CHIP_HAS_TILE_DMA()
131
132 struct async_tlb dma_async_tlb;
133#endif
134};
135
136#endif
137
138
139
140
141
142
143#define STACK_TOP_DELTA 64
144
145
146
147
148
149
150#ifdef __tilegx__
151#define KSTK_PTREGS_GAP 48
152#else
153#define KSTK_PTREGS_GAP 56
154#endif
155
156#ifndef __ASSEMBLY__
157
158#ifdef __tilegx__
159#define TASK_SIZE_MAX (_AC(1, UL) << (MAX_VA_WIDTH - 1))
160#else
161#define TASK_SIZE_MAX PAGE_OFFSET
162#endif
163
164
165#ifdef CONFIG_COMPAT
166#define COMPAT_TASK_SIZE (1UL << 31)
167#define TASK_SIZE ((current_thread_info()->status & TS_COMPAT) ?\
168 COMPAT_TASK_SIZE : TASK_SIZE_MAX)
169#else
170#define TASK_SIZE TASK_SIZE_MAX
171#endif
172
173#define VDSO_BASE ((unsigned long)current->active_mm->context.vdso_base)
174#define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x))
175
176#define STACK_TOP TASK_SIZE
177
178
179#define STACK_TOP_MAX TASK_SIZE_MAX
180
181
182
183
184
185#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
186
187#define HAVE_ARCH_PICK_MMAP_LAYOUT
188
189#define INIT_THREAD { \
190 .ksp = (unsigned long)init_stack + THREAD_SIZE - STACK_TOP_DELTA, \
191 .interrupt_mask = -1ULL \
192}
193
194
195DECLARE_PER_CPU(unsigned long, boot_sp);
196
197
198DECLARE_PER_CPU(unsigned long, boot_pc);
199
200
201static inline void start_thread(struct pt_regs *regs,
202 unsigned long pc, unsigned long usp)
203{
204 regs->pc = pc;
205 regs->sp = usp;
206 single_step_execve();
207}
208
209
210static inline void release_thread(struct task_struct *dead_task)
211{
212
213}
214
215extern void prepare_exit_to_usermode(struct pt_regs *regs, u32 flags);
216
217
218
219
220
221
222#define thread_saved_pc(t) ((t)->thread.pc)
223
224unsigned long get_wchan(struct task_struct *p);
225
226
227#define task_ksp0(task) \
228 ((unsigned long)(task)->stack + THREAD_SIZE - STACK_TOP_DELTA)
229
230
231#define task_pt_regs(task) \
232 ((struct pt_regs *)(task_ksp0(task) - KSTK_PTREGS_GAP) - 1)
233#define current_pt_regs() \
234 ((struct pt_regs *)((stack_pointer | (THREAD_SIZE - 1)) - \
235 STACK_TOP_DELTA - (KSTK_PTREGS_GAP - 1)) - 1)
236#define task_sp(task) (task_pt_regs(task)->sp)
237#define task_pc(task) (task_pt_regs(task)->pc)
238
239#define KSTK_EIP(task) task_pc(task)
240#define KSTK_ESP(task) task_sp(task)
241
242
243#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
244#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
245
246extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
247extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
248
249
250#ifdef __tilegx__
251# define REGFMT "0x%016lx"
252#else
253# define REGFMT "0x%08lx"
254#endif
255
256
257
258
259
260
261static inline void cpu_relax(void)
262{
263 __insn_mfspr(SPR_PASS);
264 barrier();
265}
266
267#define cpu_relax_lowlatency() cpu_relax()
268
269
270struct seq_operations;
271extern const struct seq_operations cpuinfo_op;
272
273
274extern char chip_model[64];
275
276
277extern int node_controller[];
278
279
280extern int hash_default;
281
282
283extern int kstack_hash;
284
285
286#define uheap_hash hash_default
287
288
289
290extern int kdata_huge;
291
292
293#define ARCH_HAS_PREFETCH
294#define prefetch(x) __builtin_prefetch(x)
295#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE()
296
297
298#ifdef __tilegx__
299#define prefetch_L1(x) __insn_prefetch_l1_fault((void *)(x))
300#else
301#define prefetch_L1(x) __insn_prefetch_L1((void *)(x))
302#endif
303
304#else
305
306
307#define CPU_RELAX mfspr zero, SPR_PASS
308
309#endif
310
311
312#if SPR_EX_CONTEXT_1_1__PL_SHIFT != 0
313# error Fix assembly assumptions about PL
314#endif
315
316
317#if SPR_EX_CONTEXT_1_1__PL_SHIFT != SPR_EX_CONTEXT_0_1__PL_SHIFT || \
318 SPR_EX_CONTEXT_1_1__PL_RMASK != SPR_EX_CONTEXT_0_1__PL_RMASK || \
319 SPR_EX_CONTEXT_1_1__ICS_SHIFT != SPR_EX_CONTEXT_0_1__ICS_SHIFT || \
320 SPR_EX_CONTEXT_1_1__ICS_RMASK != SPR_EX_CONTEXT_0_1__ICS_RMASK
321# error Fix assumptions that EX1 macros work for both PL0 and PL1
322#endif
323
324
325#define EX1_PL(ex1) \
326 (((ex1) >> SPR_EX_CONTEXT_1_1__PL_SHIFT) & SPR_EX_CONTEXT_1_1__PL_RMASK)
327#define EX1_ICS(ex1) \
328 (((ex1) >> SPR_EX_CONTEXT_1_1__ICS_SHIFT) & SPR_EX_CONTEXT_1_1__ICS_RMASK)
329#define PL_ICS_EX1(pl, ics) \
330 (((pl) << SPR_EX_CONTEXT_1_1__PL_SHIFT) | \
331 ((ics) << SPR_EX_CONTEXT_1_1__ICS_SHIFT))
332
333
334
335
336#define USER_PL 0
337#if CONFIG_KERNEL_PL == 2
338#define GUEST_PL 1
339#endif
340#define KERNEL_PL CONFIG_KERNEL_PL
341
342
343#ifdef __tilegx__
344#define CPU_SHIFT 48
345#if CHIP_VA_WIDTH() > CPU_SHIFT
346# error Too many VA bits!
347#endif
348#define MAX_CPU_ID ((1 << (64 - CPU_SHIFT)) - 1)
349#define raw_smp_processor_id() \
350 ((int)(__insn_mfspr(SPR_SYSTEM_SAVE_K_0) >> CPU_SHIFT))
351#define get_current_ksp0() \
352 ((unsigned long)(((long)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) << \
353 (64 - CPU_SHIFT)) >> (64 - CPU_SHIFT)))
354#define next_current_ksp0(task) ({ \
355 unsigned long __ksp0 = task_ksp0(task) & ((1UL << CPU_SHIFT) - 1); \
356 unsigned long __cpu = (long)raw_smp_processor_id() << CPU_SHIFT; \
357 __ksp0 | __cpu; \
358})
359#else
360#define LOG2_NR_CPU_IDS 6
361#define MAX_CPU_ID ((1 << LOG2_NR_CPU_IDS) - 1)
362#define raw_smp_processor_id() \
363 ((int)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & MAX_CPU_ID)
364#define get_current_ksp0() \
365 (__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & ~MAX_CPU_ID)
366#define next_current_ksp0(task) ({ \
367 unsigned long __ksp0 = task_ksp0(task); \
368 int __cpu = raw_smp_processor_id(); \
369 BUG_ON(__ksp0 & MAX_CPU_ID); \
370 __ksp0 | __cpu; \
371})
372#endif
373#if CONFIG_NR_CPUS > (MAX_CPU_ID + 1)
374# error Too many cpus!
375#endif
376
377#endif
378