1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36#include <linux/err.h>
37#include <linux/init.h>
38#include <linux/gpio.h>
39#include <linux/irq.h>
40#include <linux/slab.h>
41#include <linux/irqdomain.h>
42#include <linux/io.h>
43#include <linux/of_irq.h>
44#include <linux/of_device.h>
45#include <linux/clk.h>
46#include <linux/pinctrl/consumer.h>
47#include <linux/irqchip/chained_irq.h>
48
49
50
51
52#define GPIO_OUT_OFF 0x0000
53#define GPIO_IO_CONF_OFF 0x0004
54#define GPIO_BLINK_EN_OFF 0x0008
55#define GPIO_IN_POL_OFF 0x000c
56#define GPIO_DATA_IN_OFF 0x0010
57#define GPIO_EDGE_CAUSE_OFF 0x0014
58#define GPIO_EDGE_MASK_OFF 0x0018
59#define GPIO_LEVEL_MASK_OFF 0x001c
60
61
62#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
63#define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
64
65
66
67
68#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
69#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
70#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
71
72#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
73#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
74#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
75
76#define MVEBU_MAX_GPIO_PER_BANK 32
77
78struct mvebu_gpio_chip {
79 struct gpio_chip chip;
80 spinlock_t lock;
81 void __iomem *membase;
82 void __iomem *percpu_membase;
83 int irqbase;
84 struct irq_domain *domain;
85 int soc_variant;
86
87
88 u32 out_reg;
89 u32 io_conf_reg;
90 u32 blink_en_reg;
91 u32 in_pol_reg;
92 u32 edge_mask_regs[4];
93 u32 level_mask_regs[4];
94};
95
96
97
98
99
100static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
101{
102 return mvchip->membase + GPIO_OUT_OFF;
103}
104
105static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
106{
107 return mvchip->membase + GPIO_BLINK_EN_OFF;
108}
109
110static inline void __iomem *
111mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
112{
113 return mvchip->membase + GPIO_IO_CONF_OFF;
114}
115
116static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
117{
118 return mvchip->membase + GPIO_IN_POL_OFF;
119}
120
121static inline void __iomem *
122mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
123{
124 return mvchip->membase + GPIO_DATA_IN_OFF;
125}
126
127static inline void __iomem *
128mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
129{
130 int cpu;
131
132 switch (mvchip->soc_variant) {
133 case MVEBU_GPIO_SOC_VARIANT_ORION:
134 case MVEBU_GPIO_SOC_VARIANT_MV78200:
135 return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
136 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
137 cpu = smp_processor_id();
138 return mvchip->percpu_membase +
139 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
140 default:
141 BUG();
142 }
143}
144
145static inline void __iomem *
146mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
147{
148 int cpu;
149
150 switch (mvchip->soc_variant) {
151 case MVEBU_GPIO_SOC_VARIANT_ORION:
152 return mvchip->membase + GPIO_EDGE_MASK_OFF;
153 case MVEBU_GPIO_SOC_VARIANT_MV78200:
154 cpu = smp_processor_id();
155 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
156 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
157 cpu = smp_processor_id();
158 return mvchip->percpu_membase +
159 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
160 default:
161 BUG();
162 }
163}
164
165static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
166{
167 int cpu;
168
169 switch (mvchip->soc_variant) {
170 case MVEBU_GPIO_SOC_VARIANT_ORION:
171 return mvchip->membase + GPIO_LEVEL_MASK_OFF;
172 case MVEBU_GPIO_SOC_VARIANT_MV78200:
173 cpu = smp_processor_id();
174 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
175 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
176 cpu = smp_processor_id();
177 return mvchip->percpu_membase +
178 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
179 default:
180 BUG();
181 }
182}
183
184
185
186
187
188static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
189{
190 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
191 unsigned long flags;
192 u32 u;
193
194 spin_lock_irqsave(&mvchip->lock, flags);
195 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
196 if (value)
197 u |= 1 << pin;
198 else
199 u &= ~(1 << pin);
200 writel_relaxed(u, mvebu_gpioreg_out(mvchip));
201 spin_unlock_irqrestore(&mvchip->lock, flags);
202}
203
204static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
205{
206 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
207 u32 u;
208
209 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
210 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
211 readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
212 } else {
213 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
214 }
215
216 return (u >> pin) & 1;
217}
218
219static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value)
220{
221 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
222 unsigned long flags;
223 u32 u;
224
225 spin_lock_irqsave(&mvchip->lock, flags);
226 u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
227 if (value)
228 u |= 1 << pin;
229 else
230 u &= ~(1 << pin);
231 writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
232 spin_unlock_irqrestore(&mvchip->lock, flags);
233}
234
235static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
236{
237 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
238 unsigned long flags;
239 int ret;
240 u32 u;
241
242
243
244 ret = pinctrl_gpio_direction_input(chip->base + pin);
245 if (ret)
246 return ret;
247
248 spin_lock_irqsave(&mvchip->lock, flags);
249 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
250 u |= 1 << pin;
251 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
252 spin_unlock_irqrestore(&mvchip->lock, flags);
253
254 return 0;
255}
256
257static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
258 int value)
259{
260 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
261 unsigned long flags;
262 int ret;
263 u32 u;
264
265
266
267 ret = pinctrl_gpio_direction_output(chip->base + pin);
268 if (ret)
269 return ret;
270
271 mvebu_gpio_blink(chip, pin, 0);
272 mvebu_gpio_set(chip, pin, value);
273
274 spin_lock_irqsave(&mvchip->lock, flags);
275 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
276 u &= ~(1 << pin);
277 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
278 spin_unlock_irqrestore(&mvchip->lock, flags);
279
280 return 0;
281}
282
283static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
284{
285 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
286 return irq_create_mapping(mvchip->domain, pin);
287}
288
289
290
291
292static void mvebu_gpio_irq_ack(struct irq_data *d)
293{
294 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
295 struct mvebu_gpio_chip *mvchip = gc->private;
296 u32 mask = ~(1 << (d->irq - gc->irq_base));
297
298 irq_gc_lock(gc);
299 writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
300 irq_gc_unlock(gc);
301}
302
303static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
304{
305 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
306 struct mvebu_gpio_chip *mvchip = gc->private;
307 struct irq_chip_type *ct = irq_data_get_chip_type(d);
308 u32 mask = 1 << (d->irq - gc->irq_base);
309
310 irq_gc_lock(gc);
311 ct->mask_cache_priv &= ~mask;
312
313 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
314 irq_gc_unlock(gc);
315}
316
317static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
318{
319 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
320 struct mvebu_gpio_chip *mvchip = gc->private;
321 struct irq_chip_type *ct = irq_data_get_chip_type(d);
322
323 u32 mask = 1 << (d->irq - gc->irq_base);
324
325 irq_gc_lock(gc);
326 ct->mask_cache_priv |= mask;
327 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
328 irq_gc_unlock(gc);
329}
330
331static void mvebu_gpio_level_irq_mask(struct irq_data *d)
332{
333 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
334 struct mvebu_gpio_chip *mvchip = gc->private;
335 struct irq_chip_type *ct = irq_data_get_chip_type(d);
336
337 u32 mask = 1 << (d->irq - gc->irq_base);
338
339 irq_gc_lock(gc);
340 ct->mask_cache_priv &= ~mask;
341 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
342 irq_gc_unlock(gc);
343}
344
345static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
346{
347 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
348 struct mvebu_gpio_chip *mvchip = gc->private;
349 struct irq_chip_type *ct = irq_data_get_chip_type(d);
350
351 u32 mask = 1 << (d->irq - gc->irq_base);
352
353 irq_gc_lock(gc);
354 ct->mask_cache_priv |= mask;
355 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
356 irq_gc_unlock(gc);
357}
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
386{
387 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
388 struct irq_chip_type *ct = irq_data_get_chip_type(d);
389 struct mvebu_gpio_chip *mvchip = gc->private;
390 int pin;
391 u32 u;
392
393 pin = d->hwirq;
394
395 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
396 if (!u)
397 return -EINVAL;
398
399 type &= IRQ_TYPE_SENSE_MASK;
400 if (type == IRQ_TYPE_NONE)
401 return -EINVAL;
402
403
404 if (!(ct->type & type))
405 if (irq_setup_alt_chip(d, type))
406 return -EINVAL;
407
408
409
410
411 switch (type) {
412 case IRQ_TYPE_EDGE_RISING:
413 case IRQ_TYPE_LEVEL_HIGH:
414 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
415 u &= ~(1 << pin);
416 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
417 break;
418 case IRQ_TYPE_EDGE_FALLING:
419 case IRQ_TYPE_LEVEL_LOW:
420 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
421 u |= 1 << pin;
422 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
423 break;
424 case IRQ_TYPE_EDGE_BOTH: {
425 u32 v;
426
427 v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
428 readl_relaxed(mvebu_gpioreg_data_in(mvchip));
429
430
431
432
433 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
434 if (v & (1 << pin))
435 u |= 1 << pin;
436 else
437 u &= ~(1 << pin);
438 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
439 break;
440 }
441 }
442 return 0;
443}
444
445static void mvebu_gpio_irq_handler(struct irq_desc *desc)
446{
447 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
448 struct irq_chip *chip = irq_desc_get_chip(desc);
449 u32 cause, type;
450 int i;
451
452 if (mvchip == NULL)
453 return;
454
455 chained_irq_enter(chip, desc);
456
457 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
458 readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
459 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
460 readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
461
462 for (i = 0; i < mvchip->chip.ngpio; i++) {
463 int irq;
464
465 irq = mvchip->irqbase + i;
466
467 if (!(cause & (1 << i)))
468 continue;
469
470 type = irq_get_trigger_type(irq);
471 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
472
473 u32 polarity;
474
475 polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
476 polarity ^= 1 << i;
477 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
478 }
479
480 generic_handle_irq(irq);
481 }
482
483 chained_irq_exit(chip, desc);
484}
485
486#ifdef CONFIG_DEBUG_FS
487#include <linux/seq_file.h>
488
489static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
490{
491 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
492 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
493 int i;
494
495 out = readl_relaxed(mvebu_gpioreg_out(mvchip));
496 io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
497 blink = readl_relaxed(mvebu_gpioreg_blink(mvchip));
498 in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
499 data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip));
500 cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip));
501 edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
502 lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
503
504 for (i = 0; i < chip->ngpio; i++) {
505 const char *label;
506 u32 msk;
507 bool is_out;
508
509 label = gpiochip_is_requested(chip, i);
510 if (!label)
511 continue;
512
513 msk = 1 << i;
514 is_out = !(io_conf & msk);
515
516 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
517
518 if (is_out) {
519 seq_printf(s, " out %s %s\n",
520 out & msk ? "hi" : "lo",
521 blink & msk ? "(blink )" : "");
522 continue;
523 }
524
525 seq_printf(s, " in %s (act %s) - IRQ",
526 (data_in ^ in_pol) & msk ? "hi" : "lo",
527 in_pol & msk ? "lo" : "hi");
528 if (!((edg_msk | lvl_msk) & msk)) {
529 seq_puts(s, " disabled\n");
530 continue;
531 }
532 if (edg_msk & msk)
533 seq_puts(s, " edge ");
534 if (lvl_msk & msk)
535 seq_puts(s, " level");
536 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
537 }
538}
539#else
540#define mvebu_gpio_dbg_show NULL
541#endif
542
543static const struct of_device_id mvebu_gpio_of_match[] = {
544 {
545 .compatible = "marvell,orion-gpio",
546 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
547 },
548 {
549 .compatible = "marvell,mv78200-gpio",
550 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
551 },
552 {
553 .compatible = "marvell,armadaxp-gpio",
554 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
555 },
556 {
557
558 },
559};
560
561static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
562{
563 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
564 int i;
565
566 mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip));
567 mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip));
568 mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip));
569 mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip));
570
571 switch (mvchip->soc_variant) {
572 case MVEBU_GPIO_SOC_VARIANT_ORION:
573 mvchip->edge_mask_regs[0] =
574 readl(mvchip->membase + GPIO_EDGE_MASK_OFF);
575 mvchip->level_mask_regs[0] =
576 readl(mvchip->membase + GPIO_LEVEL_MASK_OFF);
577 break;
578 case MVEBU_GPIO_SOC_VARIANT_MV78200:
579 for (i = 0; i < 2; i++) {
580 mvchip->edge_mask_regs[i] =
581 readl(mvchip->membase +
582 GPIO_EDGE_MASK_MV78200_OFF(i));
583 mvchip->level_mask_regs[i] =
584 readl(mvchip->membase +
585 GPIO_LEVEL_MASK_MV78200_OFF(i));
586 }
587 break;
588 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
589 for (i = 0; i < 4; i++) {
590 mvchip->edge_mask_regs[i] =
591 readl(mvchip->membase +
592 GPIO_EDGE_MASK_ARMADAXP_OFF(i));
593 mvchip->level_mask_regs[i] =
594 readl(mvchip->membase +
595 GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
596 }
597 break;
598 default:
599 BUG();
600 }
601
602 return 0;
603}
604
605static int mvebu_gpio_resume(struct platform_device *pdev)
606{
607 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
608 int i;
609
610 writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip));
611 writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip));
612 writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip));
613 writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip));
614
615 switch (mvchip->soc_variant) {
616 case MVEBU_GPIO_SOC_VARIANT_ORION:
617 writel(mvchip->edge_mask_regs[0],
618 mvchip->membase + GPIO_EDGE_MASK_OFF);
619 writel(mvchip->level_mask_regs[0],
620 mvchip->membase + GPIO_LEVEL_MASK_OFF);
621 break;
622 case MVEBU_GPIO_SOC_VARIANT_MV78200:
623 for (i = 0; i < 2; i++) {
624 writel(mvchip->edge_mask_regs[i],
625 mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i));
626 writel(mvchip->level_mask_regs[i],
627 mvchip->membase +
628 GPIO_LEVEL_MASK_MV78200_OFF(i));
629 }
630 break;
631 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
632 for (i = 0; i < 4; i++) {
633 writel(mvchip->edge_mask_regs[i],
634 mvchip->membase +
635 GPIO_EDGE_MASK_ARMADAXP_OFF(i));
636 writel(mvchip->level_mask_regs[i],
637 mvchip->membase +
638 GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
639 }
640 break;
641 default:
642 BUG();
643 }
644
645 return 0;
646}
647
648static int mvebu_gpio_probe(struct platform_device *pdev)
649{
650 struct mvebu_gpio_chip *mvchip;
651 const struct of_device_id *match;
652 struct device_node *np = pdev->dev.of_node;
653 struct resource *res;
654 struct irq_chip_generic *gc;
655 struct irq_chip_type *ct;
656 struct clk *clk;
657 unsigned int ngpios;
658 int soc_variant;
659 int i, cpu, id;
660 int err;
661
662 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
663 if (match)
664 soc_variant = (int) match->data;
665 else
666 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
667
668 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
669 GFP_KERNEL);
670 if (!mvchip)
671 return -ENOMEM;
672
673 platform_set_drvdata(pdev, mvchip);
674
675 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
676 dev_err(&pdev->dev, "Missing ngpios OF property\n");
677 return -ENODEV;
678 }
679
680 id = of_alias_get_id(pdev->dev.of_node, "gpio");
681 if (id < 0) {
682 dev_err(&pdev->dev, "Couldn't get OF id\n");
683 return id;
684 }
685
686 clk = devm_clk_get(&pdev->dev, NULL);
687
688 if (!IS_ERR(clk))
689 clk_prepare_enable(clk);
690
691 mvchip->soc_variant = soc_variant;
692 mvchip->chip.label = dev_name(&pdev->dev);
693 mvchip->chip.parent = &pdev->dev;
694 mvchip->chip.request = gpiochip_generic_request;
695 mvchip->chip.free = gpiochip_generic_free;
696 mvchip->chip.direction_input = mvebu_gpio_direction_input;
697 mvchip->chip.get = mvebu_gpio_get;
698 mvchip->chip.direction_output = mvebu_gpio_direction_output;
699 mvchip->chip.set = mvebu_gpio_set;
700 mvchip->chip.to_irq = mvebu_gpio_to_irq;
701 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
702 mvchip->chip.ngpio = ngpios;
703 mvchip->chip.can_sleep = false;
704 mvchip->chip.of_node = np;
705 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
706
707 spin_lock_init(&mvchip->lock);
708 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
709 mvchip->membase = devm_ioremap_resource(&pdev->dev, res);
710 if (IS_ERR(mvchip->membase))
711 return PTR_ERR(mvchip->membase);
712
713
714
715 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
716 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
717 mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev,
718 res);
719 if (IS_ERR(mvchip->percpu_membase))
720 return PTR_ERR(mvchip->percpu_membase);
721 }
722
723
724
725
726 switch (soc_variant) {
727 case MVEBU_GPIO_SOC_VARIANT_ORION:
728 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
729 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
730 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
731 break;
732 case MVEBU_GPIO_SOC_VARIANT_MV78200:
733 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
734 for (cpu = 0; cpu < 2; cpu++) {
735 writel_relaxed(0, mvchip->membase +
736 GPIO_EDGE_MASK_MV78200_OFF(cpu));
737 writel_relaxed(0, mvchip->membase +
738 GPIO_LEVEL_MASK_MV78200_OFF(cpu));
739 }
740 break;
741 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
742 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
743 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
744 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
745 for (cpu = 0; cpu < 4; cpu++) {
746 writel_relaxed(0, mvchip->percpu_membase +
747 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
748 writel_relaxed(0, mvchip->percpu_membase +
749 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
750 writel_relaxed(0, mvchip->percpu_membase +
751 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
752 }
753 break;
754 default:
755 BUG();
756 }
757
758 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
759
760
761 if (!of_irq_count(np))
762 return 0;
763
764
765
766
767 for (i = 0; i < 4; i++) {
768 int irq = platform_get_irq(pdev, i);
769
770 if (irq < 0)
771 continue;
772 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
773 mvchip);
774 }
775
776 mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
777 if (mvchip->irqbase < 0) {
778 dev_err(&pdev->dev, "no irqs\n");
779 return mvchip->irqbase;
780 }
781
782 gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
783 mvchip->membase, handle_level_irq);
784 if (!gc) {
785 dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
786 return -ENOMEM;
787 }
788
789 gc->private = mvchip;
790 ct = &gc->chip_types[0];
791 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
792 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
793 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
794 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
795 ct->chip.name = mvchip->chip.label;
796
797 ct = &gc->chip_types[1];
798 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
799 ct->chip.irq_ack = mvebu_gpio_irq_ack;
800 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
801 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
802 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
803 ct->handler = handle_edge_irq;
804 ct->chip.name = mvchip->chip.label;
805
806 irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
807 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
808
809
810 mvchip->domain = irq_domain_add_simple(np, mvchip->chip.ngpio,
811 mvchip->irqbase,
812 &irq_domain_simple_ops,
813 mvchip);
814 if (!mvchip->domain) {
815 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
816 mvchip->chip.label);
817 err = -ENODEV;
818 goto err_generic_chip;
819 }
820
821 return 0;
822
823err_generic_chip:
824 irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
825 IRQ_LEVEL | IRQ_NOPROBE);
826 kfree(gc);
827
828 return err;
829}
830
831static struct platform_driver mvebu_gpio_driver = {
832 .driver = {
833 .name = "mvebu-gpio",
834 .of_match_table = mvebu_gpio_of_match,
835 },
836 .probe = mvebu_gpio_probe,
837 .suspend = mvebu_gpio_suspend,
838 .resume = mvebu_gpio_resume,
839};
840builtin_platform_driver(mvebu_gpio_driver);
841