LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
   3 *                VA Linux Systems Inc., Fremont, California.
   4 * Copyright 2008 Red Hat Inc.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 *
  24 * Original Authors:
  25 *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
  26 *
  27 * Kernel port Author: Dave Airlie
  28 */
  29
  30#ifndef AMDGPU_MODE_H
  31#define AMDGPU_MODE_H
  32
  33#include <drm/drm_crtc.h>
  34#include <drm/drm_edid.h>
  35#include <drm/drm_dp_helper.h>
  36#include <drm/drm_fixed.h>
  37#include <drm/drm_crtc_helper.h>
  38#include <drm/drm_fb_helper.h>
  39#include <drm/drm_plane_helper.h>
  40#include <linux/i2c.h>
  41#include <linux/i2c-algo-bit.h>
  42
  43struct amdgpu_bo;
  44struct amdgpu_device;
  45struct amdgpu_encoder;
  46struct amdgpu_router;
  47struct amdgpu_hpd;
  48
  49#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
  50#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
  51#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
  52#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
  53
  54#define AMDGPU_MAX_HPD_PINS 6
  55#define AMDGPU_MAX_CRTCS 6
  56#define AMDGPU_MAX_AFMT_BLOCKS 9
  57
  58enum amdgpu_rmx_type {
  59        RMX_OFF,
  60        RMX_FULL,
  61        RMX_CENTER,
  62        RMX_ASPECT
  63};
  64
  65enum amdgpu_underscan_type {
  66        UNDERSCAN_OFF,
  67        UNDERSCAN_ON,
  68        UNDERSCAN_AUTO,
  69};
  70
  71#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
  72#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
  73
  74enum amdgpu_hpd_id {
  75        AMDGPU_HPD_1 = 0,
  76        AMDGPU_HPD_2,
  77        AMDGPU_HPD_3,
  78        AMDGPU_HPD_4,
  79        AMDGPU_HPD_5,
  80        AMDGPU_HPD_6,
  81        AMDGPU_HPD_LAST,
  82        AMDGPU_HPD_NONE = 0xff,
  83};
  84
  85enum amdgpu_crtc_irq {
  86        AMDGPU_CRTC_IRQ_VBLANK1 = 0,
  87        AMDGPU_CRTC_IRQ_VBLANK2,
  88        AMDGPU_CRTC_IRQ_VBLANK3,
  89        AMDGPU_CRTC_IRQ_VBLANK4,
  90        AMDGPU_CRTC_IRQ_VBLANK5,
  91        AMDGPU_CRTC_IRQ_VBLANK6,
  92        AMDGPU_CRTC_IRQ_VLINE1,
  93        AMDGPU_CRTC_IRQ_VLINE2,
  94        AMDGPU_CRTC_IRQ_VLINE3,
  95        AMDGPU_CRTC_IRQ_VLINE4,
  96        AMDGPU_CRTC_IRQ_VLINE5,
  97        AMDGPU_CRTC_IRQ_VLINE6,
  98        AMDGPU_CRTC_IRQ_LAST,
  99        AMDGPU_CRTC_IRQ_NONE = 0xff
 100};
 101
 102enum amdgpu_pageflip_irq {
 103        AMDGPU_PAGEFLIP_IRQ_D1 = 0,
 104        AMDGPU_PAGEFLIP_IRQ_D2,
 105        AMDGPU_PAGEFLIP_IRQ_D3,
 106        AMDGPU_PAGEFLIP_IRQ_D4,
 107        AMDGPU_PAGEFLIP_IRQ_D5,
 108        AMDGPU_PAGEFLIP_IRQ_D6,
 109        AMDGPU_PAGEFLIP_IRQ_LAST,
 110        AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
 111};
 112
 113enum amdgpu_flip_status {
 114        AMDGPU_FLIP_NONE,
 115        AMDGPU_FLIP_PENDING,
 116        AMDGPU_FLIP_SUBMITTED
 117};
 118
 119#define AMDGPU_MAX_I2C_BUS 16
 120
 121/* amdgpu gpio-based i2c
 122 * 1. "mask" reg and bits
 123 *    grabs the gpio pins for software use
 124 *    0=not held  1=held
 125 * 2. "a" reg and bits
 126 *    output pin value
 127 *    0=low 1=high
 128 * 3. "en" reg and bits
 129 *    sets the pin direction
 130 *    0=input 1=output
 131 * 4. "y" reg and bits
 132 *    input pin value
 133 *    0=low 1=high
 134 */
 135struct amdgpu_i2c_bus_rec {
 136        bool valid;
 137        /* id used by atom */
 138        uint8_t i2c_id;
 139        /* id used by atom */
 140        enum amdgpu_hpd_id hpd;
 141        /* can be used with hw i2c engine */
 142        bool hw_capable;
 143        /* uses multi-media i2c engine */
 144        bool mm_i2c;
 145        /* regs and bits */
 146        uint32_t mask_clk_reg;
 147        uint32_t mask_data_reg;
 148        uint32_t a_clk_reg;
 149        uint32_t a_data_reg;
 150        uint32_t en_clk_reg;
 151        uint32_t en_data_reg;
 152        uint32_t y_clk_reg;
 153        uint32_t y_data_reg;
 154        uint32_t mask_clk_mask;
 155        uint32_t mask_data_mask;
 156        uint32_t a_clk_mask;
 157        uint32_t a_data_mask;
 158        uint32_t en_clk_mask;
 159        uint32_t en_data_mask;
 160        uint32_t y_clk_mask;
 161        uint32_t y_data_mask;
 162};
 163
 164#define AMDGPU_MAX_BIOS_CONNECTOR 16
 165
 166/* pll flags */
 167#define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
 168#define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
 169#define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
 170#define AMDGPU_PLL_LEGACY               (1 << 3)
 171#define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
 172#define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
 173#define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
 174#define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
 175#define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
 176#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
 177#define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
 178#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
 179#define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
 180#define AMDGPU_PLL_IS_LCD               (1 << 13)
 181#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
 182
 183struct amdgpu_pll {
 184        /* reference frequency */
 185        uint32_t reference_freq;
 186
 187        /* fixed dividers */
 188        uint32_t reference_div;
 189        uint32_t post_div;
 190
 191        /* pll in/out limits */
 192        uint32_t pll_in_min;
 193        uint32_t pll_in_max;
 194        uint32_t pll_out_min;
 195        uint32_t pll_out_max;
 196        uint32_t lcd_pll_out_min;
 197        uint32_t lcd_pll_out_max;
 198        uint32_t best_vco;
 199
 200        /* divider limits */
 201        uint32_t min_ref_div;
 202        uint32_t max_ref_div;
 203        uint32_t min_post_div;
 204        uint32_t max_post_div;
 205        uint32_t min_feedback_div;
 206        uint32_t max_feedback_div;
 207        uint32_t min_frac_feedback_div;
 208        uint32_t max_frac_feedback_div;
 209
 210        /* flags for the current clock */
 211        uint32_t flags;
 212
 213        /* pll id */
 214        uint32_t id;
 215};
 216
 217struct amdgpu_i2c_chan {
 218        struct i2c_adapter adapter;
 219        struct drm_device *dev;
 220        struct i2c_algo_bit_data bit;
 221        struct amdgpu_i2c_bus_rec rec;
 222        struct drm_dp_aux aux;
 223        bool has_aux;
 224        struct mutex mutex;
 225};
 226
 227struct amdgpu_fbdev;
 228
 229struct amdgpu_afmt {
 230        bool enabled;
 231        int offset;
 232        bool last_buffer_filled_status;
 233        int id;
 234        struct amdgpu_audio_pin *pin;
 235};
 236
 237/*
 238 * Audio
 239 */
 240struct amdgpu_audio_pin {
 241        int                     channels;
 242        int                     rate;
 243        int                     bits_per_sample;
 244        u8                      status_bits;
 245        u8                      category_code;
 246        u32                     offset;
 247        bool                    connected;
 248        u32                     id;
 249};
 250
 251struct amdgpu_audio {
 252        bool enabled;
 253        struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
 254        int num_pins;
 255};
 256
 257struct amdgpu_mode_mc_save {
 258        u32 vga_render_control;
 259        u32 vga_hdp_control;
 260        bool crtc_enabled[AMDGPU_MAX_CRTCS];
 261};
 262
 263struct amdgpu_display_funcs {
 264        /* vga render */
 265        void (*set_vga_render_state)(struct amdgpu_device *adev, bool render);
 266        /* display watermarks */
 267        void (*bandwidth_update)(struct amdgpu_device *adev);
 268        /* get frame count */
 269        u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
 270        /* wait for vblank */
 271        void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
 272        /* is dce hung */
 273        bool (*is_display_hung)(struct amdgpu_device *adev);
 274        /* set backlight level */
 275        void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
 276                                    u8 level);
 277        /* get backlight level */
 278        u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
 279        /* hotplug detect */
 280        bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
 281        void (*hpd_set_polarity)(struct amdgpu_device *adev,
 282                                 enum amdgpu_hpd_id hpd);
 283        u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
 284        /* pageflipping */
 285        void (*page_flip)(struct amdgpu_device *adev,
 286                          int crtc_id, u64 crtc_base, bool async);
 287        int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
 288                                        u32 *vbl, u32 *position);
 289        /* display topology setup */
 290        void (*add_encoder)(struct amdgpu_device *adev,
 291                            uint32_t encoder_enum,
 292                            uint32_t supported_device,
 293                            u16 caps);
 294        void (*add_connector)(struct amdgpu_device *adev,
 295                              uint32_t connector_id,
 296                              uint32_t supported_device,
 297                              int connector_type,
 298                              struct amdgpu_i2c_bus_rec *i2c_bus,
 299                              uint16_t connector_object_id,
 300                              struct amdgpu_hpd *hpd,
 301                              struct amdgpu_router *router);
 302        void (*stop_mc_access)(struct amdgpu_device *adev,
 303                               struct amdgpu_mode_mc_save *save);
 304        void (*resume_mc_access)(struct amdgpu_device *adev,
 305                                 struct amdgpu_mode_mc_save *save);
 306};
 307
 308struct amdgpu_mode_info {
 309        struct atom_context *atom_context;
 310        struct card_info *atom_card_info;
 311        bool mode_config_initialized;
 312        struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
 313        struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
 314        /* DVI-I properties */
 315        struct drm_property *coherent_mode_property;
 316        /* DAC enable load detect */
 317        struct drm_property *load_detect_property;
 318        /* underscan */
 319        struct drm_property *underscan_property;
 320        struct drm_property *underscan_hborder_property;
 321        struct drm_property *underscan_vborder_property;
 322        /* audio */
 323        struct drm_property *audio_property;
 324        /* FMT dithering */
 325        struct drm_property *dither_property;
 326        /* hardcoded DFP edid from BIOS */
 327        struct edid *bios_hardcoded_edid;
 328        int bios_hardcoded_edid_size;
 329
 330        /* pointer to fbdev info structure */
 331        struct amdgpu_fbdev *rfbdev;
 332        /* firmware flags */
 333        u16 firmware_flags;
 334        /* pointer to backlight encoder */
 335        struct amdgpu_encoder *bl_encoder;
 336        struct amdgpu_audio     audio; /* audio stuff */
 337        int                     num_crtc; /* number of crtcs */
 338        int                     num_hpd; /* number of hpd pins */
 339        int                     num_dig; /* number of dig blocks */
 340        int                     disp_priority;
 341        const struct amdgpu_display_funcs *funcs;
 342};
 343
 344#define AMDGPU_MAX_BL_LEVEL 0xFF
 345
 346#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 347
 348struct amdgpu_backlight_privdata {
 349        struct amdgpu_encoder *encoder;
 350        uint8_t negative;
 351};
 352
 353#endif
 354
 355struct amdgpu_atom_ss {
 356        uint16_t percentage;
 357        uint16_t percentage_divider;
 358        uint8_t type;
 359        uint16_t step;
 360        uint8_t delay;
 361        uint8_t range;
 362        uint8_t refdiv;
 363        /* asic_ss */
 364        uint16_t rate;
 365        uint16_t amount;
 366};
 367
 368struct amdgpu_crtc {
 369        struct drm_crtc base;
 370        int crtc_id;
 371        u16 lut_r[256], lut_g[256], lut_b[256];
 372        bool enabled;
 373        bool can_tile;
 374        uint32_t crtc_offset;
 375        struct drm_gem_object *cursor_bo;
 376        uint64_t cursor_addr;
 377        int cursor_x;
 378        int cursor_y;
 379        int cursor_hot_x;
 380        int cursor_hot_y;
 381        int cursor_width;
 382        int cursor_height;
 383        int max_cursor_width;
 384        int max_cursor_height;
 385        enum amdgpu_rmx_type rmx_type;
 386        u8 h_border;
 387        u8 v_border;
 388        fixed20_12 vsc;
 389        fixed20_12 hsc;
 390        struct drm_display_mode native_mode;
 391        u32 pll_id;
 392        /* page flipping */
 393        struct amdgpu_flip_work *pflip_works;
 394        enum amdgpu_flip_status pflip_status;
 395        int deferred_flip_completion;
 396        /* pll sharing */
 397        struct amdgpu_atom_ss ss;
 398        bool ss_enabled;
 399        u32 adjusted_clock;
 400        int bpc;
 401        u32 pll_reference_div;
 402        u32 pll_post_div;
 403        u32 pll_flags;
 404        struct drm_encoder *encoder;
 405        struct drm_connector *connector;
 406        /* for dpm */
 407        u32 line_time;
 408        u32 wm_low;
 409        u32 wm_high;
 410        u32 lb_vblank_lead_lines;
 411        struct drm_display_mode hw_mode;
 412};
 413
 414struct amdgpu_encoder_atom_dig {
 415        bool linkb;
 416        /* atom dig */
 417        bool coherent_mode;
 418        int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
 419        /* atom lvds/edp */
 420        uint32_t lcd_misc;
 421        uint16_t panel_pwr_delay;
 422        uint32_t lcd_ss_id;
 423        /* panel mode */
 424        struct drm_display_mode native_mode;
 425        struct backlight_device *bl_dev;
 426        int dpms_mode;
 427        uint8_t backlight_level;
 428        int panel_mode;
 429        struct amdgpu_afmt *afmt;
 430};
 431
 432struct amdgpu_encoder {
 433        struct drm_encoder base;
 434        uint32_t encoder_enum;
 435        uint32_t encoder_id;
 436        uint32_t devices;
 437        uint32_t active_device;
 438        uint32_t flags;
 439        uint32_t pixel_clock;
 440        enum amdgpu_rmx_type rmx_type;
 441        enum amdgpu_underscan_type underscan_type;
 442        uint32_t underscan_hborder;
 443        uint32_t underscan_vborder;
 444        struct drm_display_mode native_mode;
 445        void *enc_priv;
 446        int audio_polling_active;
 447        bool is_ext_encoder;
 448        u16 caps;
 449};
 450
 451struct amdgpu_connector_atom_dig {
 452        /* displayport */
 453        u8 dpcd[DP_RECEIVER_CAP_SIZE];
 454        u8 dp_sink_type;
 455        int dp_clock;
 456        int dp_lane_count;
 457        bool edp_on;
 458};
 459
 460struct amdgpu_gpio_rec {
 461        bool valid;
 462        u8 id;
 463        u32 reg;
 464        u32 mask;
 465        u32 shift;
 466};
 467
 468struct amdgpu_hpd {
 469        enum amdgpu_hpd_id hpd;
 470        u8 plugged_state;
 471        struct amdgpu_gpio_rec gpio;
 472};
 473
 474struct amdgpu_router {
 475        u32 router_id;
 476        struct amdgpu_i2c_bus_rec i2c_info;
 477        u8 i2c_addr;
 478        /* i2c mux */
 479        bool ddc_valid;
 480        u8 ddc_mux_type;
 481        u8 ddc_mux_control_pin;
 482        u8 ddc_mux_state;
 483        /* clock/data mux */
 484        bool cd_valid;
 485        u8 cd_mux_type;
 486        u8 cd_mux_control_pin;
 487        u8 cd_mux_state;
 488};
 489
 490enum amdgpu_connector_audio {
 491        AMDGPU_AUDIO_DISABLE = 0,
 492        AMDGPU_AUDIO_ENABLE = 1,
 493        AMDGPU_AUDIO_AUTO = 2
 494};
 495
 496enum amdgpu_connector_dither {
 497        AMDGPU_FMT_DITHER_DISABLE = 0,
 498        AMDGPU_FMT_DITHER_ENABLE = 1,
 499};
 500
 501struct amdgpu_connector {
 502        struct drm_connector base;
 503        uint32_t connector_id;
 504        uint32_t devices;
 505        struct amdgpu_i2c_chan *ddc_bus;
 506        /* some systems have an hdmi and vga port with a shared ddc line */
 507        bool shared_ddc;
 508        bool use_digital;
 509        /* we need to mind the EDID between detect
 510           and get modes due to analog/digital/tvencoder */
 511        struct edid *edid;
 512        void *con_priv;
 513        bool dac_load_detect;
 514        bool detected_by_load; /* if the connection status was determined by load */
 515        uint16_t connector_object_id;
 516        struct amdgpu_hpd hpd;
 517        struct amdgpu_router router;
 518        struct amdgpu_i2c_chan *router_bus;
 519        enum amdgpu_connector_audio audio;
 520        enum amdgpu_connector_dither dither;
 521        unsigned pixelclock_for_modeset;
 522};
 523
 524struct amdgpu_framebuffer {
 525        struct drm_framebuffer base;
 526        struct drm_gem_object *obj;
 527};
 528
 529#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
 530                                ((em) == ATOM_ENCODER_MODE_DP_MST))
 531
 532/* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
 533#define USE_REAL_VBLANKSTART            (1 << 30)
 534#define GET_DISTANCE_TO_VBLANKSTART     (1 << 31)
 535
 536void amdgpu_link_encoder_connector(struct drm_device *dev);
 537
 538struct drm_connector *
 539amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
 540struct drm_connector *
 541amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
 542bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
 543                                    u32 pixel_clock);
 544
 545u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
 546struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
 547
 548bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
 549
 550void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
 551
 552int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 553                               unsigned int flags, int *vpos, int *hpos,
 554                               ktime_t *stime, ktime_t *etime,
 555                               const struct drm_display_mode *mode);
 556
 557int amdgpu_framebuffer_init(struct drm_device *dev,
 558                             struct amdgpu_framebuffer *rfb,
 559                             const struct drm_mode_fb_cmd2 *mode_cmd,
 560                             struct drm_gem_object *obj);
 561
 562int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
 563
 564void amdgpu_enc_destroy(struct drm_encoder *encoder);
 565void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
 566bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 567                                        const struct drm_display_mode *mode,
 568                                        struct drm_display_mode *adjusted_mode);
 569void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
 570                             struct drm_display_mode *adjusted_mode);
 571int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
 572
 573/* fbdev layer */
 574int amdgpu_fbdev_init(struct amdgpu_device *adev);
 575void amdgpu_fbdev_fini(struct amdgpu_device *adev);
 576void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
 577int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
 578bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
 579void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev);
 580
 581void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);
 582
 583
 584int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
 585
 586/* amdgpu_display.c */
 587void amdgpu_print_display_setup(struct drm_device *dev);
 588int amdgpu_modeset_create_props(struct amdgpu_device *adev);
 589int amdgpu_crtc_set_config(struct drm_mode_set *set);
 590int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
 591                          struct drm_framebuffer *fb,
 592                          struct drm_pending_vblank_event *event,
 593                          uint32_t page_flip_flags);
 594extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
 595
 596#endif
 597