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24#include <linux/firmware.h>
25#include "drmP.h"
26#include "amdgpu.h"
27#include "amdgpu_pm.h"
28#include "amdgpu_ucode.h"
29#include "cikd.h"
30#include "amdgpu_dpm.h"
31#include "ci_dpm.h"
32#include "gfx_v7_0.h"
33#include "atom.h"
34#include "amd_pcie.h"
35#include <linux/seq_file.h>
36
37#include "smu/smu_7_0_1_d.h"
38#include "smu/smu_7_0_1_sh_mask.h"
39
40#include "dce/dce_8_0_d.h"
41#include "dce/dce_8_0_sh_mask.h"
42
43#include "bif/bif_4_1_d.h"
44#include "bif/bif_4_1_sh_mask.h"
45
46#include "gca/gfx_7_2_d.h"
47#include "gca/gfx_7_2_sh_mask.h"
48
49#include "gmc/gmc_7_1_d.h"
50#include "gmc/gmc_7_1_sh_mask.h"
51
52MODULE_FIRMWARE("radeon/bonaire_smc.bin");
53MODULE_FIRMWARE("radeon/hawaii_smc.bin");
54
55#define MC_CG_ARB_FREQ_F0 0x0a
56#define MC_CG_ARB_FREQ_F1 0x0b
57#define MC_CG_ARB_FREQ_F2 0x0c
58#define MC_CG_ARB_FREQ_F3 0x0d
59
60#define SMC_RAM_END 0x40000
61
62#define VOLTAGE_SCALE 4
63#define VOLTAGE_VID_OFFSET_SCALE1 625
64#define VOLTAGE_VID_OFFSET_SCALE2 100
65
66static const struct ci_pt_defaults defaults_hawaii_xt =
67{
68 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
69 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
70 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
71};
72
73static const struct ci_pt_defaults defaults_hawaii_pro =
74{
75 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
76 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
77 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
78};
79
80static const struct ci_pt_defaults defaults_bonaire_xt =
81{
82 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
83 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
84 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
85};
86
87static const struct ci_pt_defaults defaults_bonaire_pro =
88{
89 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
90 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
91 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
92};
93
94static const struct ci_pt_defaults defaults_saturn_xt =
95{
96 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
97 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
98 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
99};
100
101static const struct ci_pt_defaults defaults_saturn_pro =
102{
103 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
104 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
105 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
106};
107
108static const struct ci_pt_config_reg didt_config_ci[] =
109{
110 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
162 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
163 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
164 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
165 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
166 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
167 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
168 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
169 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
170 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
171 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
172 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
173 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
174 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
175 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
176 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
177 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
178 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
179 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
180 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
181 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
182 { 0xFFFFFFFF }
183};
184
185static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
186{
187 return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
188}
189
190#define MC_CG_ARB_FREQ_F0 0x0a
191#define MC_CG_ARB_FREQ_F1 0x0b
192#define MC_CG_ARB_FREQ_F2 0x0c
193#define MC_CG_ARB_FREQ_F3 0x0d
194
195static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
196 u32 arb_freq_src, u32 arb_freq_dest)
197{
198 u32 mc_arb_dram_timing;
199 u32 mc_arb_dram_timing2;
200 u32 burst_time;
201 u32 mc_cg_config;
202
203 switch (arb_freq_src) {
204 case MC_CG_ARB_FREQ_F0:
205 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
206 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
207 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
208 MC_ARB_BURST_TIME__STATE0__SHIFT;
209 break;
210 case MC_CG_ARB_FREQ_F1:
211 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING_1);
212 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
213 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
214 MC_ARB_BURST_TIME__STATE1__SHIFT;
215 break;
216 default:
217 return -EINVAL;
218 }
219
220 switch (arb_freq_dest) {
221 case MC_CG_ARB_FREQ_F0:
222 WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
223 WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
224 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
225 ~MC_ARB_BURST_TIME__STATE0_MASK);
226 break;
227 case MC_CG_ARB_FREQ_F1:
228 WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
229 WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
230 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
231 ~MC_ARB_BURST_TIME__STATE1_MASK);
232 break;
233 default:
234 return -EINVAL;
235 }
236
237 mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
238 WREG32(mmMC_CG_CONFIG, mc_cg_config);
239 WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
240 ~MC_ARB_CG__CG_ARB_REQ_MASK);
241
242 return 0;
243}
244
245static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
246{
247 u8 mc_para_index;
248
249 if (memory_clock < 10000)
250 mc_para_index = 0;
251 else if (memory_clock >= 80000)
252 mc_para_index = 0x0f;
253 else
254 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
255 return mc_para_index;
256}
257
258static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
259{
260 u8 mc_para_index;
261
262 if (strobe_mode) {
263 if (memory_clock < 12500)
264 mc_para_index = 0x00;
265 else if (memory_clock > 47500)
266 mc_para_index = 0x0f;
267 else
268 mc_para_index = (u8)((memory_clock - 10000) / 2500);
269 } else {
270 if (memory_clock < 65000)
271 mc_para_index = 0x00;
272 else if (memory_clock > 135000)
273 mc_para_index = 0x0f;
274 else
275 mc_para_index = (u8)((memory_clock - 60000) / 5000);
276 }
277 return mc_para_index;
278}
279
280static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
281 u32 max_voltage_steps,
282 struct atom_voltage_table *voltage_table)
283{
284 unsigned int i, diff;
285
286 if (voltage_table->count <= max_voltage_steps)
287 return;
288
289 diff = voltage_table->count - max_voltage_steps;
290
291 for (i = 0; i < max_voltage_steps; i++)
292 voltage_table->entries[i] = voltage_table->entries[i + diff];
293
294 voltage_table->count = max_voltage_steps;
295}
296
297static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
298 struct atom_voltage_table_entry *voltage_table,
299 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
300static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
301static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
302 u32 target_tdp);
303static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
304static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
305static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
306
307static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
308 PPSMC_Msg msg, u32 parameter);
309static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
310static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
311
312static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
313{
314 struct ci_power_info *pi = adev->pm.dpm.priv;
315
316 return pi;
317}
318
319static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
320{
321 struct ci_ps *ps = rps->ps_priv;
322
323 return ps;
324}
325
326static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
327{
328 struct ci_power_info *pi = ci_get_pi(adev);
329
330 switch (adev->pdev->device) {
331 case 0x6649:
332 case 0x6650:
333 case 0x6651:
334 case 0x6658:
335 case 0x665C:
336 case 0x665D:
337 default:
338 pi->powertune_defaults = &defaults_bonaire_xt;
339 break;
340 case 0x6640:
341 case 0x6641:
342 case 0x6646:
343 case 0x6647:
344 pi->powertune_defaults = &defaults_saturn_xt;
345 break;
346 case 0x67B8:
347 case 0x67B0:
348 pi->powertune_defaults = &defaults_hawaii_xt;
349 break;
350 case 0x67BA:
351 case 0x67B1:
352 pi->powertune_defaults = &defaults_hawaii_pro;
353 break;
354 case 0x67A0:
355 case 0x67A1:
356 case 0x67A2:
357 case 0x67A8:
358 case 0x67A9:
359 case 0x67AA:
360 case 0x67B9:
361 case 0x67BE:
362 pi->powertune_defaults = &defaults_bonaire_xt;
363 break;
364 }
365
366 pi->dte_tj_offset = 0;
367
368 pi->caps_power_containment = true;
369 pi->caps_cac = false;
370 pi->caps_sq_ramping = false;
371 pi->caps_db_ramping = false;
372 pi->caps_td_ramping = false;
373 pi->caps_tcp_ramping = false;
374
375 if (pi->caps_power_containment) {
376 pi->caps_cac = true;
377 if (adev->asic_type == CHIP_HAWAII)
378 pi->enable_bapm_feature = false;
379 else
380 pi->enable_bapm_feature = true;
381 pi->enable_tdc_limit_feature = true;
382 pi->enable_pkg_pwr_tracking_feature = true;
383 }
384}
385
386static u8 ci_convert_to_vid(u16 vddc)
387{
388 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
389}
390
391static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
392{
393 struct ci_power_info *pi = ci_get_pi(adev);
394 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
395 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
396 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
397 u32 i;
398
399 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
400 return -EINVAL;
401 if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
402 return -EINVAL;
403 if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
404 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
405 return -EINVAL;
406
407 for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
408 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
409 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
410 hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
411 hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
412 } else {
413 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
414 hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
415 }
416 }
417 return 0;
418}
419
420static int ci_populate_vddc_vid(struct amdgpu_device *adev)
421{
422 struct ci_power_info *pi = ci_get_pi(adev);
423 u8 *vid = pi->smc_powertune_table.VddCVid;
424 u32 i;
425
426 if (pi->vddc_voltage_table.count > 8)
427 return -EINVAL;
428
429 for (i = 0; i < pi->vddc_voltage_table.count; i++)
430 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
431
432 return 0;
433}
434
435static int ci_populate_svi_load_line(struct amdgpu_device *adev)
436{
437 struct ci_power_info *pi = ci_get_pi(adev);
438 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
439
440 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
441 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
442 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
443 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
444
445 return 0;
446}
447
448static int ci_populate_tdc_limit(struct amdgpu_device *adev)
449{
450 struct ci_power_info *pi = ci_get_pi(adev);
451 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
452 u16 tdc_limit;
453
454 tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
455 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
456 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
457 pt_defaults->tdc_vddc_throttle_release_limit_perc;
458 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
459
460 return 0;
461}
462
463static int ci_populate_dw8(struct amdgpu_device *adev)
464{
465 struct ci_power_info *pi = ci_get_pi(adev);
466 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
467 int ret;
468
469 ret = amdgpu_ci_read_smc_sram_dword(adev,
470 SMU7_FIRMWARE_HEADER_LOCATION +
471 offsetof(SMU7_Firmware_Header, PmFuseTable) +
472 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
473 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
474 pi->sram_end);
475 if (ret)
476 return -EINVAL;
477 else
478 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
479
480 return 0;
481}
482
483static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
484{
485 struct ci_power_info *pi = ci_get_pi(adev);
486
487 if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
488 (adev->pm.dpm.fan.fan_output_sensitivity == 0))
489 adev->pm.dpm.fan.fan_output_sensitivity =
490 adev->pm.dpm.fan.default_fan_output_sensitivity;
491
492 pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
493 cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
494
495 return 0;
496}
497
498static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
499{
500 struct ci_power_info *pi = ci_get_pi(adev);
501 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
502 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
503 int i, min, max;
504
505 min = max = hi_vid[0];
506 for (i = 0; i < 8; i++) {
507 if (0 != hi_vid[i]) {
508 if (min > hi_vid[i])
509 min = hi_vid[i];
510 if (max < hi_vid[i])
511 max = hi_vid[i];
512 }
513
514 if (0 != lo_vid[i]) {
515 if (min > lo_vid[i])
516 min = lo_vid[i];
517 if (max < lo_vid[i])
518 max = lo_vid[i];
519 }
520 }
521
522 if ((min == 0) || (max == 0))
523 return -EINVAL;
524 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
525 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
526
527 return 0;
528}
529
530static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
531{
532 struct ci_power_info *pi = ci_get_pi(adev);
533 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
534 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
535 struct amdgpu_cac_tdp_table *cac_tdp_table =
536 adev->pm.dpm.dyn_state.cac_tdp_table;
537
538 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
539 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
540
541 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
542 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
543
544 return 0;
545}
546
547static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
548{
549 struct ci_power_info *pi = ci_get_pi(adev);
550 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
551 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
552 struct amdgpu_cac_tdp_table *cac_tdp_table =
553 adev->pm.dpm.dyn_state.cac_tdp_table;
554 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
555 int i, j, k;
556 const u16 *def1;
557 const u16 *def2;
558
559 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
560 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
561
562 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
563 dpm_table->GpuTjMax =
564 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
565 dpm_table->GpuTjHyst = 8;
566
567 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
568
569 if (ppm) {
570 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
571 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
572 } else {
573 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
574 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
575 }
576
577 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
578 def1 = pt_defaults->bapmti_r;
579 def2 = pt_defaults->bapmti_rc;
580
581 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
582 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
583 for (k = 0; k < SMU7_DTE_SINKS; k++) {
584 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
585 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
586 def1++;
587 def2++;
588 }
589 }
590 }
591
592 return 0;
593}
594
595static int ci_populate_pm_base(struct amdgpu_device *adev)
596{
597 struct ci_power_info *pi = ci_get_pi(adev);
598 u32 pm_fuse_table_offset;
599 int ret;
600
601 if (pi->caps_power_containment) {
602 ret = amdgpu_ci_read_smc_sram_dword(adev,
603 SMU7_FIRMWARE_HEADER_LOCATION +
604 offsetof(SMU7_Firmware_Header, PmFuseTable),
605 &pm_fuse_table_offset, pi->sram_end);
606 if (ret)
607 return ret;
608 ret = ci_populate_bapm_vddc_vid_sidd(adev);
609 if (ret)
610 return ret;
611 ret = ci_populate_vddc_vid(adev);
612 if (ret)
613 return ret;
614 ret = ci_populate_svi_load_line(adev);
615 if (ret)
616 return ret;
617 ret = ci_populate_tdc_limit(adev);
618 if (ret)
619 return ret;
620 ret = ci_populate_dw8(adev);
621 if (ret)
622 return ret;
623 ret = ci_populate_fuzzy_fan(adev);
624 if (ret)
625 return ret;
626 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
627 if (ret)
628 return ret;
629 ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
630 if (ret)
631 return ret;
632 ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
633 (u8 *)&pi->smc_powertune_table,
634 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
635 if (ret)
636 return ret;
637 }
638
639 return 0;
640}
641
642static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
643{
644 struct ci_power_info *pi = ci_get_pi(adev);
645 u32 data;
646
647 if (pi->caps_sq_ramping) {
648 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
649 if (enable)
650 data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
651 else
652 data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
653 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
654 }
655
656 if (pi->caps_db_ramping) {
657 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
658 if (enable)
659 data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
660 else
661 data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
662 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
663 }
664
665 if (pi->caps_td_ramping) {
666 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
667 if (enable)
668 data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
669 else
670 data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
671 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
672 }
673
674 if (pi->caps_tcp_ramping) {
675 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
676 if (enable)
677 data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
678 else
679 data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
680 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
681 }
682}
683
684static int ci_program_pt_config_registers(struct amdgpu_device *adev,
685 const struct ci_pt_config_reg *cac_config_regs)
686{
687 const struct ci_pt_config_reg *config_regs = cac_config_regs;
688 u32 data;
689 u32 cache = 0;
690
691 if (config_regs == NULL)
692 return -EINVAL;
693
694 while (config_regs->offset != 0xFFFFFFFF) {
695 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
696 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
697 } else {
698 switch (config_regs->type) {
699 case CISLANDS_CONFIGREG_SMC_IND:
700 data = RREG32_SMC(config_regs->offset);
701 break;
702 case CISLANDS_CONFIGREG_DIDT_IND:
703 data = RREG32_DIDT(config_regs->offset);
704 break;
705 default:
706 data = RREG32(config_regs->offset);
707 break;
708 }
709
710 data &= ~config_regs->mask;
711 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
712 data |= cache;
713
714 switch (config_regs->type) {
715 case CISLANDS_CONFIGREG_SMC_IND:
716 WREG32_SMC(config_regs->offset, data);
717 break;
718 case CISLANDS_CONFIGREG_DIDT_IND:
719 WREG32_DIDT(config_regs->offset, data);
720 break;
721 default:
722 WREG32(config_regs->offset, data);
723 break;
724 }
725 cache = 0;
726 }
727 config_regs++;
728 }
729 return 0;
730}
731
732static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
733{
734 struct ci_power_info *pi = ci_get_pi(adev);
735 int ret;
736
737 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
738 pi->caps_td_ramping || pi->caps_tcp_ramping) {
739 gfx_v7_0_enter_rlc_safe_mode(adev);
740
741 if (enable) {
742 ret = ci_program_pt_config_registers(adev, didt_config_ci);
743 if (ret) {
744 gfx_v7_0_exit_rlc_safe_mode(adev);
745 return ret;
746 }
747 }
748
749 ci_do_enable_didt(adev, enable);
750
751 gfx_v7_0_exit_rlc_safe_mode(adev);
752 }
753
754 return 0;
755}
756
757static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
758{
759 struct ci_power_info *pi = ci_get_pi(adev);
760 PPSMC_Result smc_result;
761 int ret = 0;
762
763 if (enable) {
764 pi->power_containment_features = 0;
765 if (pi->caps_power_containment) {
766 if (pi->enable_bapm_feature) {
767 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
768 if (smc_result != PPSMC_Result_OK)
769 ret = -EINVAL;
770 else
771 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
772 }
773
774 if (pi->enable_tdc_limit_feature) {
775 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
776 if (smc_result != PPSMC_Result_OK)
777 ret = -EINVAL;
778 else
779 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
780 }
781
782 if (pi->enable_pkg_pwr_tracking_feature) {
783 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
784 if (smc_result != PPSMC_Result_OK) {
785 ret = -EINVAL;
786 } else {
787 struct amdgpu_cac_tdp_table *cac_tdp_table =
788 adev->pm.dpm.dyn_state.cac_tdp_table;
789 u32 default_pwr_limit =
790 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
791
792 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
793
794 ci_set_power_limit(adev, default_pwr_limit);
795 }
796 }
797 }
798 } else {
799 if (pi->caps_power_containment && pi->power_containment_features) {
800 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
801 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
802
803 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
804 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
805
806 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
807 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
808 pi->power_containment_features = 0;
809 }
810 }
811
812 return ret;
813}
814
815static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
816{
817 struct ci_power_info *pi = ci_get_pi(adev);
818 PPSMC_Result smc_result;
819 int ret = 0;
820
821 if (pi->caps_cac) {
822 if (enable) {
823 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
824 if (smc_result != PPSMC_Result_OK) {
825 ret = -EINVAL;
826 pi->cac_enabled = false;
827 } else {
828 pi->cac_enabled = true;
829 }
830 } else if (pi->cac_enabled) {
831 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
832 pi->cac_enabled = false;
833 }
834 }
835
836 return ret;
837}
838
839static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
840 bool enable)
841{
842 struct ci_power_info *pi = ci_get_pi(adev);
843 PPSMC_Result smc_result = PPSMC_Result_OK;
844
845 if (pi->thermal_sclk_dpm_enabled) {
846 if (enable)
847 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
848 else
849 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
850 }
851
852 if (smc_result == PPSMC_Result_OK)
853 return 0;
854 else
855 return -EINVAL;
856}
857
858static int ci_power_control_set_level(struct amdgpu_device *adev)
859{
860 struct ci_power_info *pi = ci_get_pi(adev);
861 struct amdgpu_cac_tdp_table *cac_tdp_table =
862 adev->pm.dpm.dyn_state.cac_tdp_table;
863 s32 adjust_percent;
864 s32 target_tdp;
865 int ret = 0;
866 bool adjust_polarity = false;
867
868 if (pi->caps_power_containment) {
869 adjust_percent = adjust_polarity ?
870 adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
871 target_tdp = ((100 + adjust_percent) *
872 (s32)cac_tdp_table->configurable_tdp) / 100;
873
874 ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
875 }
876
877 return ret;
878}
879
880static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
881{
882 struct ci_power_info *pi = ci_get_pi(adev);
883
884 if (pi->uvd_power_gated == gate)
885 return;
886
887 pi->uvd_power_gated = gate;
888
889 ci_update_uvd_dpm(adev, gate);
890}
891
892static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
893{
894 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
895 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
896
897 if (vblank_time < switch_limit)
898 return true;
899 else
900 return false;
901
902}
903
904static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
905 struct amdgpu_ps *rps)
906{
907 struct ci_ps *ps = ci_get_ps(rps);
908 struct ci_power_info *pi = ci_get_pi(adev);
909 struct amdgpu_clock_and_voltage_limits *max_limits;
910 bool disable_mclk_switching;
911 u32 sclk, mclk;
912 int i;
913
914 if (rps->vce_active) {
915 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
916 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
917 } else {
918 rps->evclk = 0;
919 rps->ecclk = 0;
920 }
921
922 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
923 ci_dpm_vblank_too_short(adev))
924 disable_mclk_switching = true;
925 else
926 disable_mclk_switching = false;
927
928 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
929 pi->battery_state = true;
930 else
931 pi->battery_state = false;
932
933 if (adev->pm.dpm.ac_power)
934 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
935 else
936 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
937
938 if (adev->pm.dpm.ac_power == false) {
939 for (i = 0; i < ps->performance_level_count; i++) {
940 if (ps->performance_levels[i].mclk > max_limits->mclk)
941 ps->performance_levels[i].mclk = max_limits->mclk;
942 if (ps->performance_levels[i].sclk > max_limits->sclk)
943 ps->performance_levels[i].sclk = max_limits->sclk;
944 }
945 }
946
947
948
949 if (disable_mclk_switching) {
950 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
951 sclk = ps->performance_levels[0].sclk;
952 } else {
953 mclk = ps->performance_levels[0].mclk;
954 sclk = ps->performance_levels[0].sclk;
955 }
956
957 if (rps->vce_active) {
958 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
959 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
960 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
961 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
962 }
963
964 ps->performance_levels[0].sclk = sclk;
965 ps->performance_levels[0].mclk = mclk;
966
967 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
968 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
969
970 if (disable_mclk_switching) {
971 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
972 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
973 } else {
974 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
975 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
976 }
977}
978
979static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
980 int min_temp, int max_temp)
981{
982 int low_temp = 0 * 1000;
983 int high_temp = 255 * 1000;
984 u32 tmp;
985
986 if (low_temp < min_temp)
987 low_temp = min_temp;
988 if (high_temp > max_temp)
989 high_temp = max_temp;
990 if (high_temp < low_temp) {
991 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
992 return -EINVAL;
993 }
994
995 tmp = RREG32_SMC(ixCG_THERMAL_INT);
996 tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
997 tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
998 ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
999 WREG32_SMC(ixCG_THERMAL_INT, tmp);
1000
1001#if 0
1002
1003 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1004 tmp &= DIG_THERM_DPM_MASK;
1005 tmp |= DIG_THERM_DPM(high_temp / 1000);
1006 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1007#endif
1008
1009 adev->pm.dpm.thermal.min_temp = low_temp;
1010 adev->pm.dpm.thermal.max_temp = high_temp;
1011 return 0;
1012}
1013
1014static int ci_thermal_enable_alert(struct amdgpu_device *adev,
1015 bool enable)
1016{
1017 u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
1018 PPSMC_Result result;
1019
1020 if (enable) {
1021 thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1022 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
1023 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1024 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
1025 if (result != PPSMC_Result_OK) {
1026 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1027 return -EINVAL;
1028 }
1029 } else {
1030 thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1031 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
1032 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1033 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
1034 if (result != PPSMC_Result_OK) {
1035 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
1036 return -EINVAL;
1037 }
1038 }
1039
1040 return 0;
1041}
1042
1043static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
1044{
1045 struct ci_power_info *pi = ci_get_pi(adev);
1046 u32 tmp;
1047
1048 if (pi->fan_ctrl_is_in_default_mode) {
1049 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
1050 >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1051 pi->fan_ctrl_default_mode = tmp;
1052 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
1053 >> CG_FDO_CTRL2__TMIN__SHIFT;
1054 pi->t_min = tmp;
1055 pi->fan_ctrl_is_in_default_mode = false;
1056 }
1057
1058 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1059 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
1060 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1061
1062 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1063 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1064 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1065}
1066
1067static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
1068{
1069 struct ci_power_info *pi = ci_get_pi(adev);
1070 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
1071 u32 duty100;
1072 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
1073 u16 fdo_min, slope1, slope2;
1074 u32 reference_clock, tmp;
1075 int ret;
1076 u64 tmp64;
1077
1078 if (!pi->fan_table_start) {
1079 adev->pm.dpm.fan.ucode_fan_control = false;
1080 return 0;
1081 }
1082
1083 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1084 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1085
1086 if (duty100 == 0) {
1087 adev->pm.dpm.fan.ucode_fan_control = false;
1088 return 0;
1089 }
1090
1091 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
1092 do_div(tmp64, 10000);
1093 fdo_min = (u16)tmp64;
1094
1095 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
1096 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
1097
1098 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
1099 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
1100
1101 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
1102 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
1103
1104 fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
1105 fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
1106 fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
1107
1108 fan_table.Slope1 = cpu_to_be16(slope1);
1109 fan_table.Slope2 = cpu_to_be16(slope2);
1110
1111 fan_table.FdoMin = cpu_to_be16(fdo_min);
1112
1113 fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
1114
1115 fan_table.HystUp = cpu_to_be16(1);
1116
1117 fan_table.HystSlope = cpu_to_be16(1);
1118
1119 fan_table.TempRespLim = cpu_to_be16(5);
1120
1121 reference_clock = amdgpu_asic_get_xclk(adev);
1122
1123 fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
1124 reference_clock) / 1600);
1125
1126 fan_table.FdoMax = cpu_to_be16((u16)duty100);
1127
1128 tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
1129 >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
1130 fan_table.TempSrc = (uint8_t)tmp;
1131
1132 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1133 pi->fan_table_start,
1134 (u8 *)(&fan_table),
1135 sizeof(fan_table),
1136 pi->sram_end);
1137
1138 if (ret) {
1139 DRM_ERROR("Failed to load fan table to the SMC.");
1140 adev->pm.dpm.fan.ucode_fan_control = false;
1141 }
1142
1143 return 0;
1144}
1145
1146static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
1147{
1148 struct ci_power_info *pi = ci_get_pi(adev);
1149 PPSMC_Result ret;
1150
1151 if (pi->caps_od_fuzzy_fan_control_support) {
1152 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1153 PPSMC_StartFanControl,
1154 FAN_CONTROL_FUZZY);
1155 if (ret != PPSMC_Result_OK)
1156 return -EINVAL;
1157 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1158 PPSMC_MSG_SetFanPwmMax,
1159 adev->pm.dpm.fan.default_max_fan_pwm);
1160 if (ret != PPSMC_Result_OK)
1161 return -EINVAL;
1162 } else {
1163 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1164 PPSMC_StartFanControl,
1165 FAN_CONTROL_TABLE);
1166 if (ret != PPSMC_Result_OK)
1167 return -EINVAL;
1168 }
1169
1170 pi->fan_is_controlled_by_smc = true;
1171 return 0;
1172}
1173
1174
1175static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
1176{
1177 PPSMC_Result ret;
1178 struct ci_power_info *pi = ci_get_pi(adev);
1179
1180 ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
1181 if (ret == PPSMC_Result_OK) {
1182 pi->fan_is_controlled_by_smc = false;
1183 return 0;
1184 } else {
1185 return -EINVAL;
1186 }
1187}
1188
1189static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
1190 u32 *speed)
1191{
1192 u32 duty, duty100;
1193 u64 tmp64;
1194
1195 if (adev->pm.no_fan)
1196 return -ENOENT;
1197
1198 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1199 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1200 duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
1201 >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
1202
1203 if (duty100 == 0)
1204 return -EINVAL;
1205
1206 tmp64 = (u64)duty * 100;
1207 do_div(tmp64, duty100);
1208 *speed = (u32)tmp64;
1209
1210 if (*speed > 100)
1211 *speed = 100;
1212
1213 return 0;
1214}
1215
1216static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
1217 u32 speed)
1218{
1219 u32 tmp;
1220 u32 duty, duty100;
1221 u64 tmp64;
1222 struct ci_power_info *pi = ci_get_pi(adev);
1223
1224 if (adev->pm.no_fan)
1225 return -ENOENT;
1226
1227 if (pi->fan_is_controlled_by_smc)
1228 return -EINVAL;
1229
1230 if (speed > 100)
1231 return -EINVAL;
1232
1233 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1234 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1235
1236 if (duty100 == 0)
1237 return -EINVAL;
1238
1239 tmp64 = (u64)speed * duty100;
1240 do_div(tmp64, 100);
1241 duty = (u32)tmp64;
1242
1243 tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
1244 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
1245 WREG32_SMC(ixCG_FDO_CTRL0, tmp);
1246
1247 return 0;
1248}
1249
1250static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
1251{
1252 if (mode) {
1253
1254 if (adev->pm.dpm.fan.ucode_fan_control)
1255 ci_fan_ctrl_stop_smc_fan_control(adev);
1256 ci_fan_ctrl_set_static_mode(adev, mode);
1257 } else {
1258
1259 if (adev->pm.dpm.fan.ucode_fan_control)
1260 ci_thermal_start_smc_fan_control(adev);
1261 else
1262 ci_fan_ctrl_set_default_mode(adev);
1263 }
1264}
1265
1266static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
1267{
1268 struct ci_power_info *pi = ci_get_pi(adev);
1269 u32 tmp;
1270
1271 if (pi->fan_is_controlled_by_smc)
1272 return 0;
1273
1274 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1275 return (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
1276}
1277
1278#if 0
1279static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
1280 u32 *speed)
1281{
1282 u32 tach_period;
1283 u32 xclk = amdgpu_asic_get_xclk(adev);
1284
1285 if (adev->pm.no_fan)
1286 return -ENOENT;
1287
1288 if (adev->pm.fan_pulses_per_revolution == 0)
1289 return -ENOENT;
1290
1291 tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
1292 >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
1293 if (tach_period == 0)
1294 return -ENOENT;
1295
1296 *speed = 60 * xclk * 10000 / tach_period;
1297
1298 return 0;
1299}
1300
1301static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
1302 u32 speed)
1303{
1304 u32 tach_period, tmp;
1305 u32 xclk = amdgpu_asic_get_xclk(adev);
1306
1307 if (adev->pm.no_fan)
1308 return -ENOENT;
1309
1310 if (adev->pm.fan_pulses_per_revolution == 0)
1311 return -ENOENT;
1312
1313 if ((speed < adev->pm.fan_min_rpm) ||
1314 (speed > adev->pm.fan_max_rpm))
1315 return -EINVAL;
1316
1317 if (adev->pm.dpm.fan.ucode_fan_control)
1318 ci_fan_ctrl_stop_smc_fan_control(adev);
1319
1320 tach_period = 60 * xclk * 10000 / (8 * speed);
1321 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
1322 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
1323 WREG32_SMC(CG_TACH_CTRL, tmp);
1324
1325 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
1326
1327 return 0;
1328}
1329#endif
1330
1331static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
1332{
1333 struct ci_power_info *pi = ci_get_pi(adev);
1334 u32 tmp;
1335
1336 if (!pi->fan_ctrl_is_in_default_mode) {
1337 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1338 tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1339 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1340
1341 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1342 tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
1343 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1344 pi->fan_ctrl_is_in_default_mode = true;
1345 }
1346}
1347
1348static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
1349{
1350 if (adev->pm.dpm.fan.ucode_fan_control) {
1351 ci_fan_ctrl_start_smc_fan_control(adev);
1352 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
1353 }
1354}
1355
1356static void ci_thermal_initialize(struct amdgpu_device *adev)
1357{
1358 u32 tmp;
1359
1360 if (adev->pm.fan_pulses_per_revolution) {
1361 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
1362 tmp |= (adev->pm.fan_pulses_per_revolution - 1)
1363 << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
1364 WREG32_SMC(ixCG_TACH_CTRL, tmp);
1365 }
1366
1367 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
1368 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
1369 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1370}
1371
1372static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
1373{
1374 int ret;
1375
1376 ci_thermal_initialize(adev);
1377 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
1378 if (ret)
1379 return ret;
1380 ret = ci_thermal_enable_alert(adev, true);
1381 if (ret)
1382 return ret;
1383 if (adev->pm.dpm.fan.ucode_fan_control) {
1384 ret = ci_thermal_setup_fan_table(adev);
1385 if (ret)
1386 return ret;
1387 ci_thermal_start_smc_fan_control(adev);
1388 }
1389
1390 return 0;
1391}
1392
1393static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
1394{
1395 if (!adev->pm.no_fan)
1396 ci_fan_ctrl_set_default_mode(adev);
1397}
1398
1399static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1400 u16 reg_offset, u32 *value)
1401{
1402 struct ci_power_info *pi = ci_get_pi(adev);
1403
1404 return amdgpu_ci_read_smc_sram_dword(adev,
1405 pi->soft_regs_start + reg_offset,
1406 value, pi->sram_end);
1407}
1408
1409static int ci_write_smc_soft_register(struct amdgpu_device *adev,
1410 u16 reg_offset, u32 value)
1411{
1412 struct ci_power_info *pi = ci_get_pi(adev);
1413
1414 return amdgpu_ci_write_smc_sram_dword(adev,
1415 pi->soft_regs_start + reg_offset,
1416 value, pi->sram_end);
1417}
1418
1419static void ci_init_fps_limits(struct amdgpu_device *adev)
1420{
1421 struct ci_power_info *pi = ci_get_pi(adev);
1422 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1423
1424 if (pi->caps_fps) {
1425 u16 tmp;
1426
1427 tmp = 45;
1428 table->FpsHighT = cpu_to_be16(tmp);
1429
1430 tmp = 30;
1431 table->FpsLowT = cpu_to_be16(tmp);
1432 }
1433}
1434
1435static int ci_update_sclk_t(struct amdgpu_device *adev)
1436{
1437 struct ci_power_info *pi = ci_get_pi(adev);
1438 int ret = 0;
1439 u32 low_sclk_interrupt_t = 0;
1440
1441 if (pi->caps_sclk_throttle_low_notification) {
1442 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1443
1444 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1445 pi->dpm_table_start +
1446 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1447 (u8 *)&low_sclk_interrupt_t,
1448 sizeof(u32), pi->sram_end);
1449
1450 }
1451
1452 return ret;
1453}
1454
1455static void ci_get_leakage_voltages(struct amdgpu_device *adev)
1456{
1457 struct ci_power_info *pi = ci_get_pi(adev);
1458 u16 leakage_id, virtual_voltage_id;
1459 u16 vddc, vddci;
1460 int i;
1461
1462 pi->vddc_leakage.count = 0;
1463 pi->vddci_leakage.count = 0;
1464
1465 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1466 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1467 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1468 if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
1469 continue;
1470 if (vddc != 0 && vddc != virtual_voltage_id) {
1471 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1472 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1473 pi->vddc_leakage.count++;
1474 }
1475 }
1476 } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
1477 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1478 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1479 if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
1480 virtual_voltage_id,
1481 leakage_id) == 0) {
1482 if (vddc != 0 && vddc != virtual_voltage_id) {
1483 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1484 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1485 pi->vddc_leakage.count++;
1486 }
1487 if (vddci != 0 && vddci != virtual_voltage_id) {
1488 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1489 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1490 pi->vddci_leakage.count++;
1491 }
1492 }
1493 }
1494 }
1495}
1496
1497static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
1498{
1499 struct ci_power_info *pi = ci_get_pi(adev);
1500 bool want_thermal_protection;
1501 enum amdgpu_dpm_event_src dpm_event_src;
1502 u32 tmp;
1503
1504 switch (sources) {
1505 case 0:
1506 default:
1507 want_thermal_protection = false;
1508 break;
1509 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
1510 want_thermal_protection = true;
1511 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
1512 break;
1513 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1514 want_thermal_protection = true;
1515 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
1516 break;
1517 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1518 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1519 want_thermal_protection = true;
1520 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1521 break;
1522 }
1523
1524 if (want_thermal_protection) {
1525#if 0
1526
1527 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1528 tmp &= DPM_EVENT_SRC_MASK;
1529 tmp |= DPM_EVENT_SRC(dpm_event_src);
1530 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1531#endif
1532
1533 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1534 if (pi->thermal_protection)
1535 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1536 else
1537 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1538 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1539 } else {
1540 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1541 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1542 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1543 }
1544}
1545
1546static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
1547 enum amdgpu_dpm_auto_throttle_src source,
1548 bool enable)
1549{
1550 struct ci_power_info *pi = ci_get_pi(adev);
1551
1552 if (enable) {
1553 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1554 pi->active_auto_throttle_sources |= 1 << source;
1555 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1556 }
1557 } else {
1558 if (pi->active_auto_throttle_sources & (1 << source)) {
1559 pi->active_auto_throttle_sources &= ~(1 << source);
1560 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1561 }
1562 }
1563}
1564
1565static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
1566{
1567 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1568 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1569}
1570
1571static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1572{
1573 struct ci_power_info *pi = ci_get_pi(adev);
1574 PPSMC_Result smc_result;
1575
1576 if (!pi->need_update_smu7_dpm_table)
1577 return 0;
1578
1579 if ((!pi->sclk_dpm_key_disabled) &&
1580 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1581 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1582 if (smc_result != PPSMC_Result_OK)
1583 return -EINVAL;
1584 }
1585
1586 if ((!pi->mclk_dpm_key_disabled) &&
1587 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1588 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1589 if (smc_result != PPSMC_Result_OK)
1590 return -EINVAL;
1591 }
1592
1593 pi->need_update_smu7_dpm_table = 0;
1594 return 0;
1595}
1596
1597static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
1598{
1599 struct ci_power_info *pi = ci_get_pi(adev);
1600 PPSMC_Result smc_result;
1601
1602 if (enable) {
1603 if (!pi->sclk_dpm_key_disabled) {
1604 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
1605 if (smc_result != PPSMC_Result_OK)
1606 return -EINVAL;
1607 }
1608
1609 if (!pi->mclk_dpm_key_disabled) {
1610 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
1611 if (smc_result != PPSMC_Result_OK)
1612 return -EINVAL;
1613
1614 WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
1615 ~MC_SEQ_CNTL_3__CAC_EN_MASK);
1616
1617 WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
1618 WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
1619 WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
1620
1621 udelay(10);
1622
1623 WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
1624 WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
1625 WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
1626 }
1627 } else {
1628 if (!pi->sclk_dpm_key_disabled) {
1629 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
1630 if (smc_result != PPSMC_Result_OK)
1631 return -EINVAL;
1632 }
1633
1634 if (!pi->mclk_dpm_key_disabled) {
1635 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
1636 if (smc_result != PPSMC_Result_OK)
1637 return -EINVAL;
1638 }
1639 }
1640
1641 return 0;
1642}
1643
1644static int ci_start_dpm(struct amdgpu_device *adev)
1645{
1646 struct ci_power_info *pi = ci_get_pi(adev);
1647 PPSMC_Result smc_result;
1648 int ret;
1649 u32 tmp;
1650
1651 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1652 tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1653 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1654
1655 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1656 tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1657 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1658
1659 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1660
1661 WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
1662
1663 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
1664 if (smc_result != PPSMC_Result_OK)
1665 return -EINVAL;
1666
1667 ret = ci_enable_sclk_mclk_dpm(adev, true);
1668 if (ret)
1669 return ret;
1670
1671 if (!pi->pcie_dpm_key_disabled) {
1672 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
1673 if (smc_result != PPSMC_Result_OK)
1674 return -EINVAL;
1675 }
1676
1677 return 0;
1678}
1679
1680static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1681{
1682 struct ci_power_info *pi = ci_get_pi(adev);
1683 PPSMC_Result smc_result;
1684
1685 if (!pi->need_update_smu7_dpm_table)
1686 return 0;
1687
1688 if ((!pi->sclk_dpm_key_disabled) &&
1689 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1690 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1691 if (smc_result != PPSMC_Result_OK)
1692 return -EINVAL;
1693 }
1694
1695 if ((!pi->mclk_dpm_key_disabled) &&
1696 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1697 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1698 if (smc_result != PPSMC_Result_OK)
1699 return -EINVAL;
1700 }
1701
1702 return 0;
1703}
1704
1705static int ci_stop_dpm(struct amdgpu_device *adev)
1706{
1707 struct ci_power_info *pi = ci_get_pi(adev);
1708 PPSMC_Result smc_result;
1709 int ret;
1710 u32 tmp;
1711
1712 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1713 tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1714 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1715
1716 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1717 tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1718 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1719
1720 if (!pi->pcie_dpm_key_disabled) {
1721 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
1722 if (smc_result != PPSMC_Result_OK)
1723 return -EINVAL;
1724 }
1725
1726 ret = ci_enable_sclk_mclk_dpm(adev, false);
1727 if (ret)
1728 return ret;
1729
1730 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
1731 if (smc_result != PPSMC_Result_OK)
1732 return -EINVAL;
1733
1734 return 0;
1735}
1736
1737static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
1738{
1739 u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1740
1741 if (enable)
1742 tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1743 else
1744 tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1745 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1746}
1747
1748#if 0
1749static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
1750 bool ac_power)
1751{
1752 struct ci_power_info *pi = ci_get_pi(adev);
1753 struct amdgpu_cac_tdp_table *cac_tdp_table =
1754 adev->pm.dpm.dyn_state.cac_tdp_table;
1755 u32 power_limit;
1756
1757 if (ac_power)
1758 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1759 else
1760 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1761
1762 ci_set_power_limit(adev, power_limit);
1763
1764 if (pi->caps_automatic_dc_transition) {
1765 if (ac_power)
1766 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
1767 else
1768 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
1769 }
1770
1771 return 0;
1772}
1773#endif
1774
1775static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
1776 PPSMC_Msg msg, u32 parameter)
1777{
1778 WREG32(mmSMC_MSG_ARG_0, parameter);
1779 return amdgpu_ci_send_msg_to_smc(adev, msg);
1780}
1781
1782static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
1783 PPSMC_Msg msg, u32 *parameter)
1784{
1785 PPSMC_Result smc_result;
1786
1787 smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
1788
1789 if ((smc_result == PPSMC_Result_OK) && parameter)
1790 *parameter = RREG32(mmSMC_MSG_ARG_0);
1791
1792 return smc_result;
1793}
1794
1795static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
1796{
1797 struct ci_power_info *pi = ci_get_pi(adev);
1798
1799 if (!pi->sclk_dpm_key_disabled) {
1800 PPSMC_Result smc_result =
1801 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1802 if (smc_result != PPSMC_Result_OK)
1803 return -EINVAL;
1804 }
1805
1806 return 0;
1807}
1808
1809static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
1810{
1811 struct ci_power_info *pi = ci_get_pi(adev);
1812
1813 if (!pi->mclk_dpm_key_disabled) {
1814 PPSMC_Result smc_result =
1815 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1816 if (smc_result != PPSMC_Result_OK)
1817 return -EINVAL;
1818 }
1819
1820 return 0;
1821}
1822
1823static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
1824{
1825 struct ci_power_info *pi = ci_get_pi(adev);
1826
1827 if (!pi->pcie_dpm_key_disabled) {
1828 PPSMC_Result smc_result =
1829 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1830 if (smc_result != PPSMC_Result_OK)
1831 return -EINVAL;
1832 }
1833
1834 return 0;
1835}
1836
1837static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
1838{
1839 struct ci_power_info *pi = ci_get_pi(adev);
1840
1841 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1842 PPSMC_Result smc_result =
1843 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
1844 if (smc_result != PPSMC_Result_OK)
1845 return -EINVAL;
1846 }
1847
1848 return 0;
1849}
1850
1851static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
1852 u32 target_tdp)
1853{
1854 PPSMC_Result smc_result =
1855 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1856 if (smc_result != PPSMC_Result_OK)
1857 return -EINVAL;
1858 return 0;
1859}
1860
1861#if 0
1862static int ci_set_boot_state(struct amdgpu_device *adev)
1863{
1864 return ci_enable_sclk_mclk_dpm(adev, false);
1865}
1866#endif
1867
1868static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
1869{
1870 u32 sclk_freq;
1871 PPSMC_Result smc_result =
1872 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1873 PPSMC_MSG_API_GetSclkFrequency,
1874 &sclk_freq);
1875 if (smc_result != PPSMC_Result_OK)
1876 sclk_freq = 0;
1877
1878 return sclk_freq;
1879}
1880
1881static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
1882{
1883 u32 mclk_freq;
1884 PPSMC_Result smc_result =
1885 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1886 PPSMC_MSG_API_GetMclkFrequency,
1887 &mclk_freq);
1888 if (smc_result != PPSMC_Result_OK)
1889 mclk_freq = 0;
1890
1891 return mclk_freq;
1892}
1893
1894static void ci_dpm_start_smc(struct amdgpu_device *adev)
1895{
1896 int i;
1897
1898 amdgpu_ci_program_jump_on_start(adev);
1899 amdgpu_ci_start_smc_clock(adev);
1900 amdgpu_ci_start_smc(adev);
1901 for (i = 0; i < adev->usec_timeout; i++) {
1902 if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
1903 break;
1904 }
1905}
1906
1907static void ci_dpm_stop_smc(struct amdgpu_device *adev)
1908{
1909 amdgpu_ci_reset_smc(adev);
1910 amdgpu_ci_stop_smc_clock(adev);
1911}
1912
1913static int ci_process_firmware_header(struct amdgpu_device *adev)
1914{
1915 struct ci_power_info *pi = ci_get_pi(adev);
1916 u32 tmp;
1917 int ret;
1918
1919 ret = amdgpu_ci_read_smc_sram_dword(adev,
1920 SMU7_FIRMWARE_HEADER_LOCATION +
1921 offsetof(SMU7_Firmware_Header, DpmTable),
1922 &tmp, pi->sram_end);
1923 if (ret)
1924 return ret;
1925
1926 pi->dpm_table_start = tmp;
1927
1928 ret = amdgpu_ci_read_smc_sram_dword(adev,
1929 SMU7_FIRMWARE_HEADER_LOCATION +
1930 offsetof(SMU7_Firmware_Header, SoftRegisters),
1931 &tmp, pi->sram_end);
1932 if (ret)
1933 return ret;
1934
1935 pi->soft_regs_start = tmp;
1936
1937 ret = amdgpu_ci_read_smc_sram_dword(adev,
1938 SMU7_FIRMWARE_HEADER_LOCATION +
1939 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1940 &tmp, pi->sram_end);
1941 if (ret)
1942 return ret;
1943
1944 pi->mc_reg_table_start = tmp;
1945
1946 ret = amdgpu_ci_read_smc_sram_dword(adev,
1947 SMU7_FIRMWARE_HEADER_LOCATION +
1948 offsetof(SMU7_Firmware_Header, FanTable),
1949 &tmp, pi->sram_end);
1950 if (ret)
1951 return ret;
1952
1953 pi->fan_table_start = tmp;
1954
1955 ret = amdgpu_ci_read_smc_sram_dword(adev,
1956 SMU7_FIRMWARE_HEADER_LOCATION +
1957 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1958 &tmp, pi->sram_end);
1959 if (ret)
1960 return ret;
1961
1962 pi->arb_table_start = tmp;
1963
1964 return 0;
1965}
1966
1967static void ci_read_clock_registers(struct amdgpu_device *adev)
1968{
1969 struct ci_power_info *pi = ci_get_pi(adev);
1970
1971 pi->clock_registers.cg_spll_func_cntl =
1972 RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
1973 pi->clock_registers.cg_spll_func_cntl_2 =
1974 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
1975 pi->clock_registers.cg_spll_func_cntl_3 =
1976 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
1977 pi->clock_registers.cg_spll_func_cntl_4 =
1978 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
1979 pi->clock_registers.cg_spll_spread_spectrum =
1980 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
1981 pi->clock_registers.cg_spll_spread_spectrum_2 =
1982 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
1983 pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
1984 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
1985 pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
1986 pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
1987 pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
1988 pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
1989 pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
1990 pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
1991 pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
1992}
1993
1994static void ci_init_sclk_t(struct amdgpu_device *adev)
1995{
1996 struct ci_power_info *pi = ci_get_pi(adev);
1997
1998 pi->low_sclk_interrupt_t = 0;
1999}
2000
2001static void ci_enable_thermal_protection(struct amdgpu_device *adev,
2002 bool enable)
2003{
2004 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2005
2006 if (enable)
2007 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2008 else
2009 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2010 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2011}
2012
2013static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
2014{
2015 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2016
2017 tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
2018
2019 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2020}
2021
2022#if 0
2023static int ci_enter_ulp_state(struct amdgpu_device *adev)
2024{
2025
2026 WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
2027
2028 udelay(25000);
2029
2030 return 0;
2031}
2032
2033static int ci_exit_ulp_state(struct amdgpu_device *adev)
2034{
2035 int i;
2036
2037 WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
2038
2039 udelay(7000);
2040
2041 for (i = 0; i < adev->usec_timeout; i++) {
2042 if (RREG32(mmSMC_RESP_0) == 1)
2043 break;
2044 udelay(1000);
2045 }
2046
2047 return 0;
2048}
2049#endif
2050
2051static int ci_notify_smc_display_change(struct amdgpu_device *adev,
2052 bool has_display)
2053{
2054 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
2055
2056 return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
2057}
2058
2059static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
2060 bool enable)
2061{
2062 struct ci_power_info *pi = ci_get_pi(adev);
2063
2064 if (enable) {
2065 if (pi->caps_sclk_ds) {
2066 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
2067 return -EINVAL;
2068 } else {
2069 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2070 return -EINVAL;
2071 }
2072 } else {
2073 if (pi->caps_sclk_ds) {
2074 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2075 return -EINVAL;
2076 }
2077 }
2078
2079 return 0;
2080}
2081
2082static void ci_program_display_gap(struct amdgpu_device *adev)
2083{
2084 u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2085 u32 pre_vbi_time_in_us;
2086 u32 frame_time_in_us;
2087 u32 ref_clock = adev->clock.spll.reference_freq;
2088 u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
2089 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
2090
2091 tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
2092 if (adev->pm.dpm.new_active_crtc_count > 0)
2093 tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2094 else
2095 tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2096 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2097
2098 if (refresh_rate == 0)
2099 refresh_rate = 60;
2100 if (vblank_time == 0xffffffff)
2101 vblank_time = 500;
2102 frame_time_in_us = 1000000 / refresh_rate;
2103 pre_vbi_time_in_us =
2104 frame_time_in_us - 200 - vblank_time;
2105 tmp = pre_vbi_time_in_us * (ref_clock / 100);
2106
2107 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
2108 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
2109 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2110
2111
2112 ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
2113
2114}
2115
2116static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
2117{
2118 struct ci_power_info *pi = ci_get_pi(adev);
2119 u32 tmp;
2120
2121 if (enable) {
2122 if (pi->caps_sclk_ss_support) {
2123 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2124 tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2125 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2126 }
2127 } else {
2128 tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2129 tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
2130 WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
2131
2132 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2133 tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2134 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2135 }
2136}
2137
2138static void ci_program_sstp(struct amdgpu_device *adev)
2139{
2140 WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
2141 ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
2142 (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
2143}
2144
2145static void ci_enable_display_gap(struct amdgpu_device *adev)
2146{
2147 u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2148
2149 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
2150 CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
2151 tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
2152 (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
2153
2154 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2155}
2156
2157static void ci_program_vc(struct amdgpu_device *adev)
2158{
2159 u32 tmp;
2160
2161 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2162 tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2163 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2164
2165 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
2166 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
2167 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
2168 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
2169 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
2170 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
2171 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
2172 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
2173}
2174
2175static void ci_clear_vc(struct amdgpu_device *adev)
2176{
2177 u32 tmp;
2178
2179 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2180 tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2181 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2182
2183 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
2184 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
2185 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
2186 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
2187 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
2188 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
2189 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
2190 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
2191}
2192
2193static int ci_upload_firmware(struct amdgpu_device *adev)
2194{
2195 struct ci_power_info *pi = ci_get_pi(adev);
2196 int i, ret;
2197
2198 for (i = 0; i < adev->usec_timeout; i++) {
2199 if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
2200 break;
2201 }
2202 WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
2203
2204 amdgpu_ci_stop_smc_clock(adev);
2205 amdgpu_ci_reset_smc(adev);
2206
2207 ret = amdgpu_ci_load_smc_ucode(adev, pi->sram_end);
2208
2209 return ret;
2210
2211}
2212
2213static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
2214 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
2215 struct atom_voltage_table *voltage_table)
2216{
2217 u32 i;
2218
2219 if (voltage_dependency_table == NULL)
2220 return -EINVAL;
2221
2222 voltage_table->mask_low = 0;
2223 voltage_table->phase_delay = 0;
2224
2225 voltage_table->count = voltage_dependency_table->count;
2226 for (i = 0; i < voltage_table->count; i++) {
2227 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2228 voltage_table->entries[i].smio_low = 0;
2229 }
2230
2231 return 0;
2232}
2233
2234static int ci_construct_voltage_tables(struct amdgpu_device *adev)
2235{
2236 struct ci_power_info *pi = ci_get_pi(adev);
2237 int ret;
2238
2239 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2240 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
2241 VOLTAGE_OBJ_GPIO_LUT,
2242 &pi->vddc_voltage_table);
2243 if (ret)
2244 return ret;
2245 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2246 ret = ci_get_svi2_voltage_table(adev,
2247 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2248 &pi->vddc_voltage_table);
2249 if (ret)
2250 return ret;
2251 }
2252
2253 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2254 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
2255 &pi->vddc_voltage_table);
2256
2257 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2258 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
2259 VOLTAGE_OBJ_GPIO_LUT,
2260 &pi->vddci_voltage_table);
2261 if (ret)
2262 return ret;
2263 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2264 ret = ci_get_svi2_voltage_table(adev,
2265 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2266 &pi->vddci_voltage_table);
2267 if (ret)
2268 return ret;
2269 }
2270
2271 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2272 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
2273 &pi->vddci_voltage_table);
2274
2275 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2276 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
2277 VOLTAGE_OBJ_GPIO_LUT,
2278 &pi->mvdd_voltage_table);
2279 if (ret)
2280 return ret;
2281 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2282 ret = ci_get_svi2_voltage_table(adev,
2283 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2284 &pi->mvdd_voltage_table);
2285 if (ret)
2286 return ret;
2287 }
2288
2289 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2290 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
2291 &pi->mvdd_voltage_table);
2292
2293 return 0;
2294}
2295
2296static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
2297 struct atom_voltage_table_entry *voltage_table,
2298 SMU7_Discrete_VoltageLevel *smc_voltage_table)
2299{
2300 int ret;
2301
2302 ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
2303 &smc_voltage_table->StdVoltageHiSidd,
2304 &smc_voltage_table->StdVoltageLoSidd);
2305
2306 if (ret) {
2307 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2308 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2309 }
2310
2311 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2312 smc_voltage_table->StdVoltageHiSidd =
2313 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2314 smc_voltage_table->StdVoltageLoSidd =
2315 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2316}
2317
2318static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
2319 SMU7_Discrete_DpmTable *table)
2320{
2321 struct ci_power_info *pi = ci_get_pi(adev);
2322 unsigned int count;
2323
2324 table->VddcLevelCount = pi->vddc_voltage_table.count;
2325 for (count = 0; count < table->VddcLevelCount; count++) {
2326 ci_populate_smc_voltage_table(adev,
2327 &pi->vddc_voltage_table.entries[count],
2328 &table->VddcLevel[count]);
2329
2330 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2331 table->VddcLevel[count].Smio |=
2332 pi->vddc_voltage_table.entries[count].smio_low;
2333 else
2334 table->VddcLevel[count].Smio = 0;
2335 }
2336 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2337
2338 return 0;
2339}
2340
2341static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
2342 SMU7_Discrete_DpmTable *table)
2343{
2344 unsigned int count;
2345 struct ci_power_info *pi = ci_get_pi(adev);
2346
2347 table->VddciLevelCount = pi->vddci_voltage_table.count;
2348 for (count = 0; count < table->VddciLevelCount; count++) {
2349 ci_populate_smc_voltage_table(adev,
2350 &pi->vddci_voltage_table.entries[count],
2351 &table->VddciLevel[count]);
2352
2353 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2354 table->VddciLevel[count].Smio |=
2355 pi->vddci_voltage_table.entries[count].smio_low;
2356 else
2357 table->VddciLevel[count].Smio = 0;
2358 }
2359 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2360
2361 return 0;
2362}
2363
2364static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
2365 SMU7_Discrete_DpmTable *table)
2366{
2367 struct ci_power_info *pi = ci_get_pi(adev);
2368 unsigned int count;
2369
2370 table->MvddLevelCount = pi->mvdd_voltage_table.count;
2371 for (count = 0; count < table->MvddLevelCount; count++) {
2372 ci_populate_smc_voltage_table(adev,
2373 &pi->mvdd_voltage_table.entries[count],
2374 &table->MvddLevel[count]);
2375
2376 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2377 table->MvddLevel[count].Smio |=
2378 pi->mvdd_voltage_table.entries[count].smio_low;
2379 else
2380 table->MvddLevel[count].Smio = 0;
2381 }
2382 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2383
2384 return 0;
2385}
2386
2387static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
2388 SMU7_Discrete_DpmTable *table)
2389{
2390 int ret;
2391
2392 ret = ci_populate_smc_vddc_table(adev, table);
2393 if (ret)
2394 return ret;
2395
2396 ret = ci_populate_smc_vddci_table(adev, table);
2397 if (ret)
2398 return ret;
2399
2400 ret = ci_populate_smc_mvdd_table(adev, table);
2401 if (ret)
2402 return ret;
2403
2404 return 0;
2405}
2406
2407static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
2408 SMU7_Discrete_VoltageLevel *voltage)
2409{
2410 struct ci_power_info *pi = ci_get_pi(adev);
2411 u32 i = 0;
2412
2413 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2414 for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2415 if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2416 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2417 break;
2418 }
2419 }
2420
2421 if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2422 return -EINVAL;
2423 }
2424
2425 return -EINVAL;
2426}
2427
2428static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
2429 struct atom_voltage_table_entry *voltage_table,
2430 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2431{
2432 u16 v_index, idx;
2433 bool voltage_found = false;
2434 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2435 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2436
2437 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2438 return -EINVAL;
2439
2440 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2441 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2442 if (voltage_table->value ==
2443 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2444 voltage_found = true;
2445 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2446 idx = v_index;
2447 else
2448 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2449 *std_voltage_lo_sidd =
2450 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2451 *std_voltage_hi_sidd =
2452 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2453 break;
2454 }
2455 }
2456
2457 if (!voltage_found) {
2458 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2459 if (voltage_table->value <=
2460 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2461 voltage_found = true;
2462 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2463 idx = v_index;
2464 else
2465 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2466 *std_voltage_lo_sidd =
2467 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2468 *std_voltage_hi_sidd =
2469 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2470 break;
2471 }
2472 }
2473 }
2474 }
2475
2476 return 0;
2477}
2478
2479static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
2480 const struct amdgpu_phase_shedding_limits_table *limits,
2481 u32 sclk,
2482 u32 *phase_shedding)
2483{
2484 unsigned int i;
2485
2486 *phase_shedding = 1;
2487
2488 for (i = 0; i < limits->count; i++) {
2489 if (sclk < limits->entries[i].sclk) {
2490 *phase_shedding = i;
2491 break;
2492 }
2493 }
2494}
2495
2496static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
2497 const struct amdgpu_phase_shedding_limits_table *limits,
2498 u32 mclk,
2499 u32 *phase_shedding)
2500{
2501 unsigned int i;
2502
2503 *phase_shedding = 1;
2504
2505 for (i = 0; i < limits->count; i++) {
2506 if (mclk < limits->entries[i].mclk) {
2507 *phase_shedding = i;
2508 break;
2509 }
2510 }
2511}
2512
2513static int ci_init_arb_table_index(struct amdgpu_device *adev)
2514{
2515 struct ci_power_info *pi = ci_get_pi(adev);
2516 u32 tmp;
2517 int ret;
2518
2519 ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
2520 &tmp, pi->sram_end);
2521 if (ret)
2522 return ret;
2523
2524 tmp &= 0x00FFFFFF;
2525 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2526
2527 return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
2528 tmp, pi->sram_end);
2529}
2530
2531static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
2532 struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
2533 u32 clock, u32 *voltage)
2534{
2535 u32 i = 0;
2536
2537 if (allowed_clock_voltage_table->count == 0)
2538 return -EINVAL;
2539
2540 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2541 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2542 *voltage = allowed_clock_voltage_table->entries[i].v;
2543 return 0;
2544 }
2545 }
2546
2547 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2548
2549 return 0;
2550}
2551
2552static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr)
2553{
2554 u32 i;
2555 u32 tmp;
2556 u32 min = max(min_sclk_in_sr, (u32)CISLAND_MINIMUM_ENGINE_CLOCK);
2557
2558 if (sclk < min)
2559 return 0;
2560
2561 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2562 tmp = sclk >> i;
2563 if (tmp >= min || i == 0)
2564 break;
2565 }
2566
2567 return (u8)i;
2568}
2569
2570static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
2571{
2572 return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2573}
2574
2575static int ci_reset_to_default(struct amdgpu_device *adev)
2576{
2577 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2578 0 : -EINVAL;
2579}
2580
2581static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
2582{
2583 u32 tmp;
2584
2585 tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
2586
2587 if (tmp == MC_CG_ARB_FREQ_F0)
2588 return 0;
2589
2590 return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
2591}
2592
2593static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
2594 const u32 engine_clock,
2595 const u32 memory_clock,
2596 u32 *dram_timimg2)
2597{
2598 bool patch;
2599 u32 tmp, tmp2;
2600
2601 tmp = RREG32(mmMC_SEQ_MISC0);
2602 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2603
2604 if (patch &&
2605 ((adev->pdev->device == 0x67B0) ||
2606 (adev->pdev->device == 0x67B1))) {
2607 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2608 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2609 *dram_timimg2 &= ~0x00ff0000;
2610 *dram_timimg2 |= tmp2 << 16;
2611 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2612 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2613 *dram_timimg2 &= ~0x00ff0000;
2614 *dram_timimg2 |= tmp2 << 16;
2615 }
2616 }
2617}
2618
2619static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
2620 u32 sclk,
2621 u32 mclk,
2622 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2623{
2624 u32 dram_timing;
2625 u32 dram_timing2;
2626 u32 burst_time;
2627
2628 amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
2629
2630 dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
2631 dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
2632 burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
2633
2634 ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
2635
2636 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2637 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2638 arb_regs->McArbBurstTime = (u8)burst_time;
2639
2640 return 0;
2641}
2642
2643static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
2644{
2645 struct ci_power_info *pi = ci_get_pi(adev);
2646 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2647 u32 i, j;
2648 int ret = 0;
2649
2650 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2651
2652 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2653 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2654 ret = ci_populate_memory_timing_parameters(adev,
2655 pi->dpm_table.sclk_table.dpm_levels[i].value,
2656 pi->dpm_table.mclk_table.dpm_levels[j].value,
2657 &arb_regs.entries[i][j]);
2658 if (ret)
2659 break;
2660 }
2661 }
2662
2663 if (ret == 0)
2664 ret = amdgpu_ci_copy_bytes_to_smc(adev,
2665 pi->arb_table_start,
2666 (u8 *)&arb_regs,
2667 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2668 pi->sram_end);
2669
2670 return ret;
2671}
2672
2673static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
2674{
2675 struct ci_power_info *pi = ci_get_pi(adev);
2676
2677 if (pi->need_update_smu7_dpm_table == 0)
2678 return 0;
2679
2680 return ci_do_program_memory_timing_parameters(adev);
2681}
2682
2683static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
2684 struct amdgpu_ps *amdgpu_boot_state)
2685{
2686 struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
2687 struct ci_power_info *pi = ci_get_pi(adev);
2688 u32 level = 0;
2689
2690 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2691 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2692 boot_state->performance_levels[0].sclk) {
2693 pi->smc_state_table.GraphicsBootLevel = level;
2694 break;
2695 }
2696 }
2697
2698 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2699 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2700 boot_state->performance_levels[0].mclk) {
2701 pi->smc_state_table.MemoryBootLevel = level;
2702 break;
2703 }
2704 }
2705}
2706
2707static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2708{
2709 u32 i;
2710 u32 mask_value = 0;
2711
2712 for (i = dpm_table->count; i > 0; i--) {
2713 mask_value = mask_value << 1;
2714 if (dpm_table->dpm_levels[i-1].enabled)
2715 mask_value |= 0x1;
2716 else
2717 mask_value &= 0xFFFFFFFE;
2718 }
2719
2720 return mask_value;
2721}
2722
2723static void ci_populate_smc_link_level(struct amdgpu_device *adev,
2724 SMU7_Discrete_DpmTable *table)
2725{
2726 struct ci_power_info *pi = ci_get_pi(adev);
2727 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2728 u32 i;
2729
2730 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2731 table->LinkLevel[i].PcieGenSpeed =
2732 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2733 table->LinkLevel[i].PcieLaneCount =
2734 amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2735 table->LinkLevel[i].EnabledForActivity = 1;
2736 table->LinkLevel[i].DownT = cpu_to_be32(5);
2737 table->LinkLevel[i].UpT = cpu_to_be32(30);
2738 }
2739
2740 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2741 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2742 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2743}
2744
2745static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
2746 SMU7_Discrete_DpmTable *table)
2747{
2748 u32 count;
2749 struct atom_clock_dividers dividers;
2750 int ret = -EINVAL;
2751
2752 table->UvdLevelCount =
2753 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2754
2755 for (count = 0; count < table->UvdLevelCount; count++) {
2756 table->UvdLevel[count].VclkFrequency =
2757 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2758 table->UvdLevel[count].DclkFrequency =
2759 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2760 table->UvdLevel[count].MinVddc =
2761 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2762 table->UvdLevel[count].MinVddcPhases = 1;
2763
2764 ret = amdgpu_atombios_get_clock_dividers(adev,
2765 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2766 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2767 if (ret)
2768 return ret;
2769
2770 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2771
2772 ret = amdgpu_atombios_get_clock_dividers(adev,
2773 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2774 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2775 if (ret)
2776 return ret;
2777
2778 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2779
2780 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2781 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2782 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2783 }
2784
2785 return ret;
2786}
2787
2788static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
2789 SMU7_Discrete_DpmTable *table)
2790{
2791 u32 count;
2792 struct atom_clock_dividers dividers;
2793 int ret = -EINVAL;
2794
2795 table->VceLevelCount =
2796 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2797
2798 for (count = 0; count < table->VceLevelCount; count++) {
2799 table->VceLevel[count].Frequency =
2800 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2801 table->VceLevel[count].MinVoltage =
2802 (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2803 table->VceLevel[count].MinPhases = 1;
2804
2805 ret = amdgpu_atombios_get_clock_dividers(adev,
2806 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2807 table->VceLevel[count].Frequency, false, ÷rs);
2808 if (ret)
2809 return ret;
2810
2811 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2812
2813 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2814 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2815 }
2816
2817 return ret;
2818
2819}
2820
2821static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
2822 SMU7_Discrete_DpmTable *table)
2823{
2824 u32 count;
2825 struct atom_clock_dividers dividers;
2826 int ret = -EINVAL;
2827
2828 table->AcpLevelCount = (u8)
2829 (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2830
2831 for (count = 0; count < table->AcpLevelCount; count++) {
2832 table->AcpLevel[count].Frequency =
2833 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2834 table->AcpLevel[count].MinVoltage =
2835 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2836 table->AcpLevel[count].MinPhases = 1;
2837
2838 ret = amdgpu_atombios_get_clock_dividers(adev,
2839 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2840 table->AcpLevel[count].Frequency, false, ÷rs);
2841 if (ret)
2842 return ret;
2843
2844 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2845
2846 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2847 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2848 }
2849
2850 return ret;
2851}
2852
2853static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
2854 SMU7_Discrete_DpmTable *table)
2855{
2856 u32 count;
2857 struct atom_clock_dividers dividers;
2858 int ret = -EINVAL;
2859
2860 table->SamuLevelCount =
2861 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2862
2863 for (count = 0; count < table->SamuLevelCount; count++) {
2864 table->SamuLevel[count].Frequency =
2865 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2866 table->SamuLevel[count].MinVoltage =
2867 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2868 table->SamuLevel[count].MinPhases = 1;
2869
2870 ret = amdgpu_atombios_get_clock_dividers(adev,
2871 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2872 table->SamuLevel[count].Frequency, false, ÷rs);
2873 if (ret)
2874 return ret;
2875
2876 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2877
2878 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2879 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2880 }
2881
2882 return ret;
2883}
2884
2885static int ci_calculate_mclk_params(struct amdgpu_device *adev,
2886 u32 memory_clock,
2887 SMU7_Discrete_MemoryLevel *mclk,
2888 bool strobe_mode,
2889 bool dll_state_on)
2890{
2891 struct ci_power_info *pi = ci_get_pi(adev);
2892 u32 dll_cntl = pi->clock_registers.dll_cntl;
2893 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2894 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2895 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2896 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2897 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2898 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2899 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2900 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2901 struct atom_mpll_param mpll_param;
2902 int ret;
2903
2904 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
2905 if (ret)
2906 return ret;
2907
2908 mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
2909 mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
2910
2911 mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
2912 MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
2913 mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
2914 (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
2915 (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
2916
2917 mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
2918 mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2919
2920 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
2921 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
2922 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
2923 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
2924 (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2925 }
2926
2927 if (pi->caps_mclk_ss_support) {
2928 struct amdgpu_atom_ss ss;
2929 u32 freq_nom;
2930 u32 tmp;
2931 u32 reference_clock = adev->clock.mpll.reference_freq;
2932
2933 if (mpll_param.qdr == 1)
2934 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2935 else
2936 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2937
2938 tmp = (freq_nom / reference_clock);
2939 tmp = tmp * tmp;
2940 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
2941 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2942 u32 clks = reference_clock * 5 / ss.rate;
2943 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2944
2945 mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
2946 mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
2947
2948 mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
2949 mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
2950 }
2951 }
2952
2953 mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
2954 mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
2955
2956 if (dll_state_on)
2957 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2958 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
2959 else
2960 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2961 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
2962
2963 mclk->MclkFrequency = memory_clock;
2964 mclk->MpllFuncCntl = mpll_func_cntl;
2965 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2966 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2967 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2968 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2969 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2970 mclk->DllCntl = dll_cntl;
2971 mclk->MpllSs1 = mpll_ss1;
2972 mclk->MpllSs2 = mpll_ss2;
2973
2974 return 0;
2975}
2976
2977static int ci_populate_single_memory_level(struct amdgpu_device *adev,
2978 u32 memory_clock,
2979 SMU7_Discrete_MemoryLevel *memory_level)
2980{
2981 struct ci_power_info *pi = ci_get_pi(adev);
2982 int ret;
2983 bool dll_state_on;
2984
2985 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2986 ret = ci_get_dependency_volt_by_clk(adev,
2987 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2988 memory_clock, &memory_level->MinVddc);
2989 if (ret)
2990 return ret;
2991 }
2992
2993 if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2994 ret = ci_get_dependency_volt_by_clk(adev,
2995 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2996 memory_clock, &memory_level->MinVddci);
2997 if (ret)
2998 return ret;
2999 }
3000
3001 if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
3002 ret = ci_get_dependency_volt_by_clk(adev,
3003 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
3004 memory_clock, &memory_level->MinMvdd);
3005 if (ret)
3006 return ret;
3007 }
3008
3009 memory_level->MinVddcPhases = 1;
3010
3011 if (pi->vddc_phase_shed_control)
3012 ci_populate_phase_value_based_on_mclk(adev,
3013 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3014 memory_clock,
3015 &memory_level->MinVddcPhases);
3016
3017 memory_level->EnabledForThrottle = 1;
3018 memory_level->UpH = 0;
3019 memory_level->DownH = 100;
3020 memory_level->VoltageDownH = 0;
3021 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
3022
3023 memory_level->StutterEnable = false;
3024 memory_level->StrobeEnable = false;
3025 memory_level->EdcReadEnable = false;
3026 memory_level->EdcWriteEnable = false;
3027 memory_level->RttEnable = false;
3028
3029 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3030
3031 if (pi->mclk_stutter_mode_threshold &&
3032 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
3033 (pi->uvd_enabled == false) &&
3034 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
3035 (adev->pm.dpm.new_active_crtc_count <= 2))
3036 memory_level->StutterEnable = true;
3037
3038 if (pi->mclk_strobe_mode_threshold &&
3039 (memory_clock <= pi->mclk_strobe_mode_threshold))
3040 memory_level->StrobeEnable = 1;
3041
3042 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
3043 memory_level->StrobeRatio =
3044 ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
3045 if (pi->mclk_edc_enable_threshold &&
3046 (memory_clock > pi->mclk_edc_enable_threshold))
3047 memory_level->EdcReadEnable = true;
3048
3049 if (pi->mclk_edc_wr_enable_threshold &&
3050 (memory_clock > pi->mclk_edc_wr_enable_threshold))
3051 memory_level->EdcWriteEnable = true;
3052
3053 if (memory_level->StrobeEnable) {
3054 if (ci_get_mclk_frequency_ratio(memory_clock, true) >=
3055 ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
3056 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3057 else
3058 dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
3059 } else {
3060 dll_state_on = pi->dll_default_on;
3061 }
3062 } else {
3063 memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);
3064 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3065 }
3066
3067 ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
3068 if (ret)
3069 return ret;
3070
3071 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
3072 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
3073 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
3074 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
3075
3076 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
3077 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
3078 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
3079 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
3080 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
3081 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
3082 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
3083 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
3084 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
3085 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
3086 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
3087
3088 return 0;
3089}
3090
3091static int ci_populate_smc_acpi_level(struct amdgpu_device *adev,
3092 SMU7_Discrete_DpmTable *table)
3093{
3094 struct ci_power_info *pi = ci_get_pi(adev);
3095 struct atom_clock_dividers dividers;
3096 SMU7_Discrete_VoltageLevel voltage_level;
3097 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
3098 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
3099 u32 dll_cntl = pi->clock_registers.dll_cntl;
3100 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
3101 int ret;
3102
3103 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
3104
3105 if (pi->acpi_vddc)
3106 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
3107 else
3108 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
3109
3110 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
3111
3112 table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;
3113
3114 ret = amdgpu_atombios_get_clock_dividers(adev,
3115 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3116 table->ACPILevel.SclkFrequency, false, ÷rs);
3117 if (ret)
3118 return ret;
3119
3120 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3121 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3122 table->ACPILevel.DeepSleepDivId = 0;
3123
3124 spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK;
3125 spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
3126
3127 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
3128 spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT);
3129
3130 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3131 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3132 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3133 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3134 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3135 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3136 table->ACPILevel.CcPwrDynRm = 0;
3137 table->ACPILevel.CcPwrDynRm1 = 0;
3138
3139 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3140 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3141 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3142 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3143 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3144 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3145 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3146 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3147 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3148 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3149 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3150
3151 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3152 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3153
3154 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3155 if (pi->acpi_vddci)
3156 table->MemoryACPILevel.MinVddci =
3157 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3158 else
3159 table->MemoryACPILevel.MinVddci =
3160 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3161 }
3162
3163 if (ci_populate_mvdd_value(adev, 0, &voltage_level))
3164 table->MemoryACPILevel.MinMvdd = 0;
3165 else
3166 table->MemoryACPILevel.MinMvdd =
3167 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3168
3169 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK |
3170 MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK;
3171 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
3172 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
3173
3174 dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK);
3175
3176 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3177 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3178 table->MemoryACPILevel.MpllAdFuncCntl =
3179 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3180 table->MemoryACPILevel.MpllDqFuncCntl =
3181 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3182 table->MemoryACPILevel.MpllFuncCntl =
3183 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3184 table->MemoryACPILevel.MpllFuncCntl_1 =
3185 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3186 table->MemoryACPILevel.MpllFuncCntl_2 =
3187 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3188 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3189 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3190
3191 table->MemoryACPILevel.EnabledForThrottle = 0;
3192 table->MemoryACPILevel.EnabledForActivity = 0;
3193 table->MemoryACPILevel.UpH = 0;
3194 table->MemoryACPILevel.DownH = 100;
3195 table->MemoryACPILevel.VoltageDownH = 0;
3196 table->MemoryACPILevel.ActivityLevel =
3197 cpu_to_be16((u16)pi->mclk_activity_target);
3198
3199 table->MemoryACPILevel.StutterEnable = false;
3200 table->MemoryACPILevel.StrobeEnable = false;
3201 table->MemoryACPILevel.EdcReadEnable = false;
3202 table->MemoryACPILevel.EdcWriteEnable = false;
3203 table->MemoryACPILevel.RttEnable = false;
3204
3205 return 0;
3206}
3207
3208
3209static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
3210{
3211 struct ci_power_info *pi = ci_get_pi(adev);
3212 struct ci_ulv_parm *ulv = &pi->ulv;
3213
3214 if (ulv->supported) {
3215 if (enable)
3216 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3217 0 : -EINVAL;
3218 else
3219 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3220 0 : -EINVAL;
3221 }
3222
3223 return 0;
3224}
3225
3226static int ci_populate_ulv_level(struct amdgpu_device *adev,
3227 SMU7_Discrete_Ulv *state)
3228{
3229 struct ci_power_info *pi = ci_get_pi(adev);
3230 u16 ulv_voltage = adev->pm.dpm.backbias_response_time;
3231
3232 state->CcPwrDynRm = 0;
3233 state->CcPwrDynRm1 = 0;
3234
3235 if (ulv_voltage == 0) {
3236 pi->ulv.supported = false;
3237 return 0;
3238 }
3239
3240 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3241 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3242 state->VddcOffset = 0;
3243 else
3244 state->VddcOffset =
3245 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3246 } else {
3247 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3248 state->VddcOffsetVid = 0;
3249 else
3250 state->VddcOffsetVid = (u8)
3251 ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3252 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3253 }
3254 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3255
3256 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3257 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3258 state->VddcOffset = cpu_to_be16(state->VddcOffset);
3259
3260 return 0;
3261}
3262
3263static int ci_calculate_sclk_params(struct amdgpu_device *adev,
3264 u32 engine_clock,
3265 SMU7_Discrete_GraphicsLevel *sclk)
3266{
3267 struct ci_power_info *pi = ci_get_pi(adev);
3268 struct atom_clock_dividers dividers;
3269 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3270 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3271 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3272 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3273 u32 reference_clock = adev->clock.spll.reference_freq;
3274 u32 reference_divider;
3275 u32 fbdiv;
3276 int ret;
3277
3278 ret = amdgpu_atombios_get_clock_dividers(adev,
3279 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3280 engine_clock, false, ÷rs);
3281 if (ret)
3282 return ret;
3283
3284 reference_divider = 1 + dividers.ref_div;
3285 fbdiv = dividers.fb_div & 0x3FFFFFF;
3286
3287 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
3288 spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT);
3289 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
3290
3291 if (pi->caps_sclk_ss_support) {
3292 struct amdgpu_atom_ss ss;
3293 u32 vco_freq = engine_clock * dividers.post_div;
3294
3295 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
3296 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3297 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3298 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3299
3300 cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
3301 cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT);
3302 cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT);
3303
3304 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK;
3305 cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT);
3306 }
3307 }
3308
3309 sclk->SclkFrequency = engine_clock;
3310 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3311 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3312 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3313 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
3314 sclk->SclkDid = (u8)dividers.post_divider;
3315
3316 return 0;
3317}
3318
3319static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
3320 u32 engine_clock,
3321 u16 sclk_activity_level_t,
3322 SMU7_Discrete_GraphicsLevel *graphic_level)
3323{
3324 struct ci_power_info *pi = ci_get_pi(adev);
3325 int ret;
3326
3327 ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);
3328 if (ret)
3329 return ret;
3330
3331 ret = ci_get_dependency_volt_by_clk(adev,
3332 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3333 engine_clock, &graphic_level->MinVddc);
3334 if (ret)
3335 return ret;
3336
3337 graphic_level->SclkFrequency = engine_clock;
3338
3339 graphic_level->Flags = 0;
3340 graphic_level->MinVddcPhases = 1;
3341
3342 if (pi->vddc_phase_shed_control)
3343 ci_populate_phase_value_based_on_sclk(adev,
3344 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3345 engine_clock,
3346 &graphic_level->MinVddcPhases);
3347
3348 graphic_level->ActivityLevel = sclk_activity_level_t;
3349
3350 graphic_level->CcPwrDynRm = 0;
3351 graphic_level->CcPwrDynRm1 = 0;
3352 graphic_level->EnabledForThrottle = 1;
3353 graphic_level->UpH = 0;
3354 graphic_level->DownH = 0;
3355 graphic_level->VoltageDownH = 0;
3356 graphic_level->PowerThrottle = 0;
3357
3358 if (pi->caps_sclk_ds)
3359 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(engine_clock,
3360 CISLAND_MINIMUM_ENGINE_CLOCK);
3361
3362 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3363
3364 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3365 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3366 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3367 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3368 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3369 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3370 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3371 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3372 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3373 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3374 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3375
3376 return 0;
3377}
3378
3379static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
3380{
3381 struct ci_power_info *pi = ci_get_pi(adev);
3382 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3383 u32 level_array_address = pi->dpm_table_start +
3384 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3385 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3386 SMU7_MAX_LEVELS_GRAPHICS;
3387 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3388 u32 i, ret;
3389
3390 memset(levels, 0, level_array_size);
3391
3392 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3393 ret = ci_populate_single_graphic_level(adev,
3394 dpm_table->sclk_table.dpm_levels[i].value,
3395 (u16)pi->activity_target[i],
3396 &pi->smc_state_table.GraphicsLevel[i]);
3397 if (ret)
3398 return ret;
3399 if (i > 1)
3400 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3401 if (i == (dpm_table->sclk_table.count - 1))
3402 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3403 PPSMC_DISPLAY_WATERMARK_HIGH;
3404 }
3405 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3406
3407 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3408 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3409 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3410
3411 ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3412 (u8 *)levels, level_array_size,
3413 pi->sram_end);
3414 if (ret)
3415 return ret;
3416
3417 return 0;
3418}
3419
3420static int ci_populate_ulv_state(struct amdgpu_device *adev,
3421 SMU7_Discrete_Ulv *ulv_level)
3422{
3423 return ci_populate_ulv_level(adev, ulv_level);
3424}
3425
3426static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
3427{
3428 struct ci_power_info *pi = ci_get_pi(adev);
3429 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3430 u32 level_array_address = pi->dpm_table_start +
3431 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3432 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3433 SMU7_MAX_LEVELS_MEMORY;
3434 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3435 u32 i, ret;
3436
3437 memset(levels, 0, level_array_size);
3438
3439 for (i = 0; i < dpm_table->mclk_table.count; i++) {
3440 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3441 return -EINVAL;
3442 ret = ci_populate_single_memory_level(adev,
3443 dpm_table->mclk_table.dpm_levels[i].value,
3444 &pi->smc_state_table.MemoryLevel[i]);
3445 if (ret)
3446 return ret;
3447 }
3448
3449 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3450
3451 if ((dpm_table->mclk_table.count >= 2) &&
3452 ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
3453 pi->smc_state_table.MemoryLevel[1].MinVddc =
3454 pi->smc_state_table.MemoryLevel[0].MinVddc;
3455 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3456 pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3457 }
3458
3459 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3460
3461 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3462 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3463 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3464
3465 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3466 PPSMC_DISPLAY_WATERMARK_HIGH;
3467
3468 ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3469 (u8 *)levels, level_array_size,
3470 pi->sram_end);
3471 if (ret)
3472 return ret;
3473
3474 return 0;
3475}
3476
3477static void ci_reset_single_dpm_table(struct amdgpu_device *adev,
3478 struct ci_single_dpm_table* dpm_table,
3479 u32 count)
3480{
3481 u32 i;
3482
3483 dpm_table->count = count;
3484 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3485 dpm_table->dpm_levels[i].enabled = false;
3486}
3487
3488static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3489 u32 index, u32 pcie_gen, u32 pcie_lanes)
3490{
3491 dpm_table->dpm_levels[index].value = pcie_gen;
3492 dpm_table->dpm_levels[index].param1 = pcie_lanes;
3493 dpm_table->dpm_levels[index].enabled = true;
3494}
3495
3496static int ci_setup_default_pcie_tables(struct amdgpu_device *adev)
3497{
3498 struct ci_power_info *pi = ci_get_pi(adev);
3499
3500 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3501 return -EINVAL;
3502
3503 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3504 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3505 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3506 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3507 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3508 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3509 }
3510
3511 ci_reset_single_dpm_table(adev,
3512 &pi->dpm_table.pcie_speed_table,
3513 SMU7_MAX_LEVELS_LINK);
3514
3515 if (adev->asic_type == CHIP_BONAIRE)
3516 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3517 pi->pcie_gen_powersaving.min,
3518 pi->pcie_lane_powersaving.max);
3519 else
3520 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3521 pi->pcie_gen_powersaving.min,
3522 pi->pcie_lane_powersaving.min);
3523 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3524 pi->pcie_gen_performance.min,
3525 pi->pcie_lane_performance.min);
3526 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3527 pi->pcie_gen_powersaving.min,
3528 pi->pcie_lane_powersaving.max);
3529 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3530 pi->pcie_gen_performance.min,
3531 pi->pcie_lane_performance.max);
3532 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3533 pi->pcie_gen_powersaving.max,
3534 pi->pcie_lane_powersaving.max);
3535 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3536 pi->pcie_gen_performance.max,
3537 pi->pcie_lane_performance.max);
3538
3539 pi->dpm_table.pcie_speed_table.count = 6;
3540
3541 return 0;
3542}
3543
3544static int ci_setup_default_dpm_tables(struct amdgpu_device *adev)
3545{
3546 struct ci_power_info *pi = ci_get_pi(adev);
3547 struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3548 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3549 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table =
3550 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3551 struct amdgpu_cac_leakage_table *std_voltage_table =
3552 &adev->pm.dpm.dyn_state.cac_leakage_table;
3553 u32 i;
3554
3555 if (allowed_sclk_vddc_table == NULL)
3556 return -EINVAL;
3557 if (allowed_sclk_vddc_table->count < 1)
3558 return -EINVAL;
3559 if (allowed_mclk_table == NULL)
3560 return -EINVAL;
3561 if (allowed_mclk_table->count < 1)
3562 return -EINVAL;
3563
3564 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3565
3566 ci_reset_single_dpm_table(adev,
3567 &pi->dpm_table.sclk_table,
3568 SMU7_MAX_LEVELS_GRAPHICS);
3569 ci_reset_single_dpm_table(adev,
3570 &pi->dpm_table.mclk_table,
3571 SMU7_MAX_LEVELS_MEMORY);
3572 ci_reset_single_dpm_table(adev,
3573 &pi->dpm_table.vddc_table,
3574 SMU7_MAX_LEVELS_VDDC);
3575 ci_reset_single_dpm_table(adev,
3576 &pi->dpm_table.vddci_table,
3577 SMU7_MAX_LEVELS_VDDCI);
3578 ci_reset_single_dpm_table(adev,
3579 &pi->dpm_table.mvdd_table,
3580 SMU7_MAX_LEVELS_MVDD);
3581
3582 pi->dpm_table.sclk_table.count = 0;
3583 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3584 if ((i == 0) ||
3585 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3586 allowed_sclk_vddc_table->entries[i].clk)) {
3587 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3588 allowed_sclk_vddc_table->entries[i].clk;
3589 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3590 (i == 0) ? true : false;
3591 pi->dpm_table.sclk_table.count++;
3592 }
3593 }
3594
3595 pi->dpm_table.mclk_table.count = 0;
3596 for (i = 0; i < allowed_mclk_table->count; i++) {
3597 if ((i == 0) ||
3598 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3599 allowed_mclk_table->entries[i].clk)) {
3600 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3601 allowed_mclk_table->entries[i].clk;
3602 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3603 (i == 0) ? true : false;
3604 pi->dpm_table.mclk_table.count++;
3605 }
3606 }
3607
3608 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3609 pi->dpm_table.vddc_table.dpm_levels[i].value =
3610 allowed_sclk_vddc_table->entries[i].v;
3611 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3612 std_voltage_table->entries[i].leakage;
3613 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3614 }
3615 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3616
3617 allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3618 if (allowed_mclk_table) {
3619 for (i = 0; i < allowed_mclk_table->count; i++) {
3620 pi->dpm_table.vddci_table.dpm_levels[i].value =
3621 allowed_mclk_table->entries[i].v;
3622 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3623 }
3624 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3625 }
3626
3627 allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3628 if (allowed_mclk_table) {
3629 for (i = 0; i < allowed_mclk_table->count; i++) {
3630 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3631 allowed_mclk_table->entries[i].v;
3632 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3633 }
3634 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3635 }
3636
3637 ci_setup_default_pcie_tables(adev);
3638
3639 return 0;
3640}
3641
3642static int ci_find_boot_level(struct ci_single_dpm_table *table,
3643 u32 value, u32 *boot_level)
3644{
3645 u32 i;
3646 int ret = -EINVAL;
3647
3648 for(i = 0; i < table->count; i++) {
3649 if (value == table->dpm_levels[i].value) {
3650 *boot_level = i;
3651 ret = 0;
3652 }
3653 }
3654
3655 return ret;
3656}
3657
3658static int ci_init_smc_table(struct amdgpu_device *adev)
3659{
3660 struct ci_power_info *pi = ci_get_pi(adev);
3661 struct ci_ulv_parm *ulv = &pi->ulv;
3662 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
3663 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3664 int ret;
3665
3666 ret = ci_setup_default_dpm_tables(adev);
3667 if (ret)
3668 return ret;
3669
3670 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3671 ci_populate_smc_voltage_tables(adev, table);
3672
3673 ci_init_fps_limits(adev);
3674
3675 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3676 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3677
3678 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3679 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3680
3681 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
3682 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3683
3684 if (ulv->supported) {
3685 ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);
3686 if (ret)
3687 return ret;
3688 WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3689 }
3690
3691 ret = ci_populate_all_graphic_levels(adev);
3692 if (ret)
3693 return ret;
3694
3695 ret = ci_populate_all_memory_levels(adev);
3696 if (ret)
3697 return ret;
3698
3699 ci_populate_smc_link_level(adev, table);
3700
3701 ret = ci_populate_smc_acpi_level(adev, table);
3702 if (ret)
3703 return ret;
3704
3705 ret = ci_populate_smc_vce_level(adev, table);
3706 if (ret)
3707 return ret;
3708
3709 ret = ci_populate_smc_acp_level(adev, table);
3710 if (ret)
3711 return ret;
3712
3713 ret = ci_populate_smc_samu_level(adev, table);
3714 if (ret)
3715 return ret;
3716
3717 ret = ci_do_program_memory_timing_parameters(adev);
3718 if (ret)
3719 return ret;
3720
3721 ret = ci_populate_smc_uvd_level(adev, table);
3722 if (ret)
3723 return ret;
3724
3725 table->UvdBootLevel = 0;
3726 table->VceBootLevel = 0;
3727 table->AcpBootLevel = 0;
3728 table->SamuBootLevel = 0;
3729 table->GraphicsBootLevel = 0;
3730 table->MemoryBootLevel = 0;
3731
3732 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3733 pi->vbios_boot_state.sclk_bootup_value,
3734 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3735
3736 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3737 pi->vbios_boot_state.mclk_bootup_value,
3738 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3739
3740 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3741 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3742 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3743
3744 ci_populate_smc_initial_state(adev, amdgpu_boot_state);
3745
3746 ret = ci_populate_bapm_parameters_in_dpm_table(adev);
3747 if (ret)
3748 return ret;
3749
3750 table->UVDInterval = 1;
3751 table->VCEInterval = 1;
3752 table->ACPInterval = 1;
3753 table->SAMUInterval = 1;
3754 table->GraphicsVoltageChangeEnable = 1;
3755 table->GraphicsThermThrottleEnable = 1;
3756 table->GraphicsInterval = 1;
3757 table->VoltageInterval = 1;
3758 table->ThermalInterval = 1;
3759 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3760 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3761 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3762 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3763 table->MemoryVoltageChangeEnable = 1;
3764 table->MemoryInterval = 1;
3765 table->VoltageResponseTime = 0;
3766 table->VddcVddciDelta = 4000;
3767 table->PhaseResponseTime = 0;
3768 table->MemoryThermThrottleEnable = 1;
3769 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3770 table->PCIeGenInterval = 1;
3771 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3772 table->SVI2Enable = 1;
3773 else
3774 table->SVI2Enable = 0;
3775
3776 table->ThermGpio = 17;
3777 table->SclkStepSize = 0x4000;
3778
3779 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3780 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3781 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3782 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3783 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3784 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3785 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3786 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3787 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3788 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3789 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3790 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3791 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3792 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3793
3794 ret = amdgpu_ci_copy_bytes_to_smc(adev,
3795 pi->dpm_table_start +
3796 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3797 (u8 *)&table->SystemFlags,
3798 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3799 pi->sram_end);
3800 if (ret)
3801 return ret;
3802
3803 return 0;
3804}
3805
3806static void ci_trim_single_dpm_states(struct amdgpu_device *adev,
3807 struct ci_single_dpm_table *dpm_table,
3808 u32 low_limit, u32 high_limit)
3809{
3810 u32 i;
3811
3812 for (i = 0; i < dpm_table->count; i++) {
3813 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3814 (dpm_table->dpm_levels[i].value > high_limit))
3815 dpm_table->dpm_levels[i].enabled = false;
3816 else
3817 dpm_table->dpm_levels[i].enabled = true;
3818 }
3819}
3820
3821static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev,
3822 u32 speed_low, u32 lanes_low,
3823 u32 speed_high, u32 lanes_high)
3824{
3825 struct ci_power_info *pi = ci_get_pi(adev);
3826 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3827 u32 i, j;
3828
3829 for (i = 0; i < pcie_table->count; i++) {
3830 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3831 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3832 (pcie_table->dpm_levels[i].value > speed_high) ||
3833 (pcie_table->dpm_levels[i].param1 > lanes_high))
3834 pcie_table->dpm_levels[i].enabled = false;
3835 else
3836 pcie_table->dpm_levels[i].enabled = true;
3837 }
3838
3839 for (i = 0; i < pcie_table->count; i++) {
3840 if (pcie_table->dpm_levels[i].enabled) {
3841 for (j = i + 1; j < pcie_table->count; j++) {
3842 if (pcie_table->dpm_levels[j].enabled) {
3843 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3844 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3845 pcie_table->dpm_levels[j].enabled = false;
3846 }
3847 }
3848 }
3849 }
3850}
3851
3852static int ci_trim_dpm_states(struct amdgpu_device *adev,
3853 struct amdgpu_ps *amdgpu_state)
3854{
3855 struct ci_ps *state = ci_get_ps(amdgpu_state);
3856 struct ci_power_info *pi = ci_get_pi(adev);
3857 u32 high_limit_count;
3858
3859 if (state->performance_level_count < 1)
3860 return -EINVAL;
3861
3862 if (state->performance_level_count == 1)
3863 high_limit_count = 0;
3864 else
3865 high_limit_count = 1;
3866
3867 ci_trim_single_dpm_states(adev,
3868 &pi->dpm_table.sclk_table,
3869 state->performance_levels[0].sclk,
3870 state->performance_levels[high_limit_count].sclk);
3871
3872 ci_trim_single_dpm_states(adev,
3873 &pi->dpm_table.mclk_table,
3874 state->performance_levels[0].mclk,
3875 state->performance_levels[high_limit_count].mclk);
3876
3877 ci_trim_pcie_dpm_states(adev,
3878 state->performance_levels[0].pcie_gen,
3879 state->performance_levels[0].pcie_lane,
3880 state->performance_levels[high_limit_count].pcie_gen,
3881 state->performance_levels[high_limit_count].pcie_lane);
3882
3883 return 0;
3884}
3885
3886static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev)
3887{
3888 struct amdgpu_clock_voltage_dependency_table *disp_voltage_table =
3889 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3890 struct amdgpu_clock_voltage_dependency_table *vddc_table =
3891 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3892 u32 requested_voltage = 0;
3893 u32 i;
3894
3895 if (disp_voltage_table == NULL)
3896 return -EINVAL;
3897 if (!disp_voltage_table->count)
3898 return -EINVAL;
3899
3900 for (i = 0; i < disp_voltage_table->count; i++) {
3901 if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3902 requested_voltage = disp_voltage_table->entries[i].v;
3903 }
3904
3905 for (i = 0; i < vddc_table->count; i++) {
3906 if (requested_voltage <= vddc_table->entries[i].v) {
3907 requested_voltage = vddc_table->entries[i].v;
3908 return (amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3909 PPSMC_MSG_VddC_Request,
3910 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3911 0 : -EINVAL;
3912 }
3913 }
3914
3915 return -EINVAL;
3916}
3917
3918static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev)
3919{
3920 struct ci_power_info *pi = ci_get_pi(adev);
3921 PPSMC_Result result;
3922
3923 ci_apply_disp_minimum_voltage_request(adev);
3924
3925 if (!pi->sclk_dpm_key_disabled) {
3926 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3927 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3928 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3929 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3930 if (result != PPSMC_Result_OK)
3931 return -EINVAL;
3932 }
3933 }
3934
3935 if (!pi->mclk_dpm_key_disabled) {
3936 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3937 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3938 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3939 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3940 if (result != PPSMC_Result_OK)
3941 return -EINVAL;
3942 }
3943 }
3944
3945#if 0
3946 if (!pi->pcie_dpm_key_disabled) {
3947 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3948 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3949 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3950 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3951 if (result != PPSMC_Result_OK)
3952 return -EINVAL;
3953 }
3954 }
3955#endif
3956
3957 return 0;
3958}
3959
3960static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev,
3961 struct amdgpu_ps *amdgpu_state)
3962{
3963 struct ci_power_info *pi = ci_get_pi(adev);
3964 struct ci_ps *state = ci_get_ps(amdgpu_state);
3965 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3966 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3967 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3968 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3969 u32 i;
3970
3971 pi->need_update_smu7_dpm_table = 0;
3972
3973 for (i = 0; i < sclk_table->count; i++) {
3974 if (sclk == sclk_table->dpm_levels[i].value)
3975 break;
3976 }
3977
3978 if (i >= sclk_table->count) {
3979 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3980 } else {
3981
3982 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3983 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3984 }
3985
3986 for (i = 0; i < mclk_table->count; i++) {
3987 if (mclk == mclk_table->dpm_levels[i].value)
3988 break;
3989 }
3990
3991 if (i >= mclk_table->count)
3992 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3993
3994 if (adev->pm.dpm.current_active_crtc_count !=
3995 adev->pm.dpm.new_active_crtc_count)
3996 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3997}
3998
3999static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev,
4000 struct amdgpu_ps *amdgpu_state)
4001{
4002 struct ci_power_info *pi = ci_get_pi(adev);
4003 struct ci_ps *state = ci_get_ps(amdgpu_state);
4004 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
4005 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4006 struct ci_dpm_table *dpm_table = &pi->dpm_table;
4007 int ret;
4008
4009 if (!pi->need_update_smu7_dpm_table)
4010 return 0;
4011
4012 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
4013 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
4014
4015 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
4016 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
4017
4018 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
4019 ret = ci_populate_all_graphic_levels(adev);
4020 if (ret)
4021 return ret;
4022 }
4023
4024 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
4025 ret = ci_populate_all_memory_levels(adev);
4026 if (ret)
4027 return ret;
4028 }
4029
4030 return 0;
4031}
4032
4033static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
4034{
4035 struct ci_power_info *pi = ci_get_pi(adev);
4036 const struct amdgpu_clock_and_voltage_limits *max_limits;
4037 int i;
4038
4039 if (adev->pm.dpm.ac_power)
4040 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4041 else
4042 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4043
4044 if (enable) {
4045 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
4046
4047 for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4048 if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4049 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
4050
4051 if (!pi->caps_uvd_dpm)
4052 break;
4053 }
4054 }
4055
4056 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4057 PPSMC_MSG_UVDDPM_SetEnabledMask,
4058 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
4059
4060 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4061 pi->uvd_enabled = true;
4062 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4063 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4064 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4065 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4066 }
4067 } else {
4068 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4069 pi->uvd_enabled = false;
4070 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
4071 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4072 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4073 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4074 }
4075 }
4076
4077 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4078 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
4079 0 : -EINVAL;
4080}
4081
4082static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
4083{
4084 struct ci_power_info *pi = ci_get_pi(adev);
4085 const struct amdgpu_clock_and_voltage_limits *max_limits;
4086 int i;
4087
4088 if (adev->pm.dpm.ac_power)
4089 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4090 else
4091 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4092
4093 if (enable) {
4094 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
4095 for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4096 if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4097 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
4098
4099 if (!pi->caps_vce_dpm)
4100 break;
4101 }
4102 }
4103
4104 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4105 PPSMC_MSG_VCEDPM_SetEnabledMask,
4106 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
4107 }
4108
4109 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4110 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
4111 0 : -EINVAL;
4112}
4113
4114#if 0
4115static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
4116{
4117 struct ci_power_info *pi = ci_get_pi(adev);
4118 const struct amdgpu_clock_and_voltage_limits *max_limits;
4119 int i;
4120
4121 if (adev->pm.dpm.ac_power)
4122 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4123 else
4124 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4125
4126 if (enable) {
4127 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4128 for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4129 if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4130 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4131
4132 if (!pi->caps_samu_dpm)
4133 break;
4134 }
4135 }
4136
4137 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4138 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4139 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4140 }
4141 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4142 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4143 0 : -EINVAL;
4144}
4145
4146static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
4147{
4148 struct ci_power_info *pi = ci_get_pi(adev);
4149 const struct amdgpu_clock_and_voltage_limits *max_limits;
4150 int i;
4151
4152 if (adev->pm.dpm.ac_power)
4153 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4154 else
4155 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4156
4157 if (enable) {
4158 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4159 for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4160 if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4161 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4162
4163 if (!pi->caps_acp_dpm)
4164 break;
4165 }
4166 }
4167
4168 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4169 PPSMC_MSG_ACPDPM_SetEnabledMask,
4170 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4171 }
4172
4173 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4174 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4175 0 : -EINVAL;
4176}
4177#endif
4178
4179static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4180{
4181 struct ci_power_info *pi = ci_get_pi(adev);
4182 u32 tmp;
4183
4184 if (!gate) {
4185 if (pi->caps_uvd_dpm ||
4186 (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4187 pi->smc_state_table.UvdBootLevel = 0;
4188 else
4189 pi->smc_state_table.UvdBootLevel =
4190 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4191
4192 tmp = RREG32_SMC(ixDPM_TABLE_475);
4193 tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
4194 tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
4195 WREG32_SMC(ixDPM_TABLE_475, tmp);
4196 }
4197
4198 return ci_enable_uvd_dpm(adev, !gate);
4199}
4200
4201static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
4202{
4203 u8 i;
4204 u32 min_evclk = 30000;
4205 struct amdgpu_vce_clock_voltage_dependency_table *table =
4206 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4207
4208 for (i = 0; i < table->count; i++) {
4209 if (table->entries[i].evclk >= min_evclk)
4210 return i;
4211 }
4212
4213 return table->count - 1;
4214}
4215
4216static int ci_update_vce_dpm(struct amdgpu_device *adev,
4217 struct amdgpu_ps *amdgpu_new_state,
4218 struct amdgpu_ps *amdgpu_current_state)
4219{
4220 struct ci_power_info *pi = ci_get_pi(adev);
4221 int ret = 0;
4222 u32 tmp;
4223
4224 if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
4225 if (amdgpu_new_state->evclk) {
4226
4227 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4228 AMD_CG_STATE_UNGATE);
4229 if (ret)
4230 return ret;
4231
4232 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
4233 tmp = RREG32_SMC(ixDPM_TABLE_475);
4234 tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
4235 tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
4236 WREG32_SMC(ixDPM_TABLE_475, tmp);
4237
4238 ret = ci_enable_vce_dpm(adev, true);
4239 } else {
4240
4241 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4242 AMD_CG_STATE_GATE);
4243 if (ret)
4244 return ret;
4245
4246 ret = ci_enable_vce_dpm(adev, false);
4247 }
4248 }
4249 return ret;
4250}
4251
4252#if 0
4253static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
4254{
4255 return ci_enable_samu_dpm(adev, gate);
4256}
4257
4258static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
4259{
4260 struct ci_power_info *pi = ci_get_pi(adev);
4261 u32 tmp;
4262
4263 if (!gate) {
4264 pi->smc_state_table.AcpBootLevel = 0;
4265
4266 tmp = RREG32_SMC(ixDPM_TABLE_475);
4267 tmp &= ~AcpBootLevel_MASK;
4268 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4269 WREG32_SMC(ixDPM_TABLE_475, tmp);
4270 }
4271
4272 return ci_enable_acp_dpm(adev, !gate);
4273}
4274#endif
4275
4276static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev,
4277 struct amdgpu_ps *amdgpu_state)
4278{
4279 struct ci_power_info *pi = ci_get_pi(adev);
4280 int ret;
4281
4282 ret = ci_trim_dpm_states(adev, amdgpu_state);
4283 if (ret)
4284 return ret;
4285
4286 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4287 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4288 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4289 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4290 pi->last_mclk_dpm_enable_mask =
4291 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4292 if (pi->uvd_enabled) {
4293 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4294 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4295 }
4296 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4297 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4298
4299 return 0;
4300}
4301
4302static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
4303 u32 level_mask)
4304{
4305 u32 level = 0;
4306
4307 while ((level_mask & (1 << level)) == 0)
4308 level++;
4309
4310 return level;
4311}
4312
4313
4314static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
4315 enum amdgpu_dpm_forced_level level)
4316{
4317 struct ci_power_info *pi = ci_get_pi(adev);
4318 u32 tmp, levels, i;
4319 int ret;
4320
4321 if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
4322 if ((!pi->pcie_dpm_key_disabled) &&
4323 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4324 levels = 0;
4325 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4326 while (tmp >>= 1)
4327 levels++;
4328 if (levels) {
4329 ret = ci_dpm_force_state_pcie(adev, level);
4330 if (ret)
4331 return ret;
4332 for (i = 0; i < adev->usec_timeout; i++) {
4333 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4334 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4335 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4336 if (tmp == levels)
4337 break;
4338 udelay(1);
4339 }
4340 }
4341 }
4342 if ((!pi->sclk_dpm_key_disabled) &&
4343 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4344 levels = 0;
4345 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4346 while (tmp >>= 1)
4347 levels++;
4348 if (levels) {
4349 ret = ci_dpm_force_state_sclk(adev, levels);
4350 if (ret)
4351 return ret;
4352 for (i = 0; i < adev->usec_timeout; i++) {
4353 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4354 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4355 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4356 if (tmp == levels)
4357 break;
4358 udelay(1);
4359 }
4360 }
4361 }
4362 if ((!pi->mclk_dpm_key_disabled) &&
4363 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4364 levels = 0;
4365 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4366 while (tmp >>= 1)
4367 levels++;
4368 if (levels) {
4369 ret = ci_dpm_force_state_mclk(adev, levels);
4370 if (ret)
4371 return ret;
4372 for (i = 0; i < adev->usec_timeout; i++) {
4373 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4374 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4375 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4376 if (tmp == levels)
4377 break;
4378 udelay(1);
4379 }
4380 }
4381 }
4382 } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
4383 if ((!pi->sclk_dpm_key_disabled) &&
4384 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4385 levels = ci_get_lowest_enabled_level(adev,
4386 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4387 ret = ci_dpm_force_state_sclk(adev, levels);
4388 if (ret)
4389 return ret;
4390 for (i = 0; i < adev->usec_timeout; i++) {
4391 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4392 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4393 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4394 if (tmp == levels)
4395 break;
4396 udelay(1);
4397 }
4398 }
4399 if ((!pi->mclk_dpm_key_disabled) &&
4400 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4401 levels = ci_get_lowest_enabled_level(adev,
4402 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4403 ret = ci_dpm_force_state_mclk(adev, levels);
4404 if (ret)
4405 return ret;
4406 for (i = 0; i < adev->usec_timeout; i++) {
4407 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4408 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4409 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4410 if (tmp == levels)
4411 break;
4412 udelay(1);
4413 }
4414 }
4415 if ((!pi->pcie_dpm_key_disabled) &&
4416 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4417 levels = ci_get_lowest_enabled_level(adev,
4418 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4419 ret = ci_dpm_force_state_pcie(adev, levels);
4420 if (ret)
4421 return ret;
4422 for (i = 0; i < adev->usec_timeout; i++) {
4423 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4424 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4425 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4426 if (tmp == levels)
4427 break;
4428 udelay(1);
4429 }
4430 }
4431 } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
4432 if (!pi->pcie_dpm_key_disabled) {
4433 PPSMC_Result smc_result;
4434
4435 smc_result = amdgpu_ci_send_msg_to_smc(adev,
4436 PPSMC_MSG_PCIeDPM_UnForceLevel);
4437 if (smc_result != PPSMC_Result_OK)
4438 return -EINVAL;
4439 }
4440 ret = ci_upload_dpm_level_enable_mask(adev);
4441 if (ret)
4442 return ret;
4443 }
4444
4445 adev->pm.dpm.forced_level = level;
4446
4447 return 0;
4448}
4449
4450static int ci_set_mc_special_registers(struct amdgpu_device *adev,
4451 struct ci_mc_reg_table *table)
4452{
4453 u8 i, j, k;
4454 u32 temp_reg;
4455
4456 for (i = 0, j = table->last; i < table->last; i++) {
4457 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4458 return -EINVAL;
4459 switch(table->mc_reg_address[i].s1) {
4460 case mmMC_SEQ_MISC1:
4461 temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
4462 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
4463 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
4464 for (k = 0; k < table->num_entries; k++) {
4465 table->mc_reg_table_entry[k].mc_data[j] =
4466 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4467 }
4468 j++;
4469 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4470 return -EINVAL;
4471
4472 temp_reg = RREG32(mmMC_PMG_CMD_MRS);
4473 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
4474 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
4475 for (k = 0; k < table->num_entries; k++) {
4476 table->mc_reg_table_entry[k].mc_data[j] =
4477 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4478 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
4479 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4480 }
4481 j++;
4482 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4483 return -EINVAL;
4484
4485 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
4486 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
4487 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
4488 for (k = 0; k < table->num_entries; k++) {
4489 table->mc_reg_table_entry[k].mc_data[j] =
4490 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4491 }
4492 j++;
4493 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4494 return -EINVAL;
4495 }
4496 break;
4497 case mmMC_SEQ_RESERVE_M:
4498 temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
4499 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
4500 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
4501 for (k = 0; k < table->num_entries; k++) {
4502 table->mc_reg_table_entry[k].mc_data[j] =
4503 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4504 }
4505 j++;
4506 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4507 return -EINVAL;
4508 break;
4509 default:
4510 break;
4511 }
4512
4513 }
4514
4515 table->last = j;
4516
4517 return 0;
4518}
4519
4520static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4521{
4522 bool result = true;
4523
4524 switch(in_reg) {
4525 case mmMC_SEQ_RAS_TIMING:
4526 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
4527 break;
4528 case mmMC_SEQ_DLL_STBY:
4529 *out_reg = mmMC_SEQ_DLL_STBY_LP;
4530 break;
4531 case mmMC_SEQ_G5PDX_CMD0:
4532 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
4533 break;
4534 case mmMC_SEQ_G5PDX_CMD1:
4535 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
4536 break;
4537 case mmMC_SEQ_G5PDX_CTRL:
4538 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
4539 break;
4540 case mmMC_SEQ_CAS_TIMING:
4541 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
4542 break;
4543 case mmMC_SEQ_MISC_TIMING:
4544 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
4545 break;
4546 case mmMC_SEQ_MISC_TIMING2:
4547 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
4548 break;
4549 case mmMC_SEQ_PMG_DVS_CMD:
4550 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
4551 break;
4552 case mmMC_SEQ_PMG_DVS_CTL:
4553 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
4554 break;
4555 case mmMC_SEQ_RD_CTL_D0:
4556 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
4557 break;
4558 case mmMC_SEQ_RD_CTL_D1:
4559 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
4560 break;
4561 case mmMC_SEQ_WR_CTL_D0:
4562 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
4563 break;
4564 case mmMC_SEQ_WR_CTL_D1:
4565 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
4566 break;
4567 case mmMC_PMG_CMD_EMRS:
4568 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
4569 break;
4570 case mmMC_PMG_CMD_MRS:
4571 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
4572 break;
4573 case mmMC_PMG_CMD_MRS1:
4574 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
4575 break;
4576 case mmMC_SEQ_PMG_TIMING:
4577 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
4578 break;
4579 case mmMC_PMG_CMD_MRS2:
4580 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
4581 break;
4582 case mmMC_SEQ_WR_CTL_2:
4583 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
4584 break;
4585 default:
4586 result = false;
4587 break;
4588 }
4589
4590 return result;
4591}
4592
4593static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4594{
4595 u8 i, j;
4596
4597 for (i = 0; i < table->last; i++) {
4598 for (j = 1; j < table->num_entries; j++) {
4599 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4600 table->mc_reg_table_entry[j].mc_data[i]) {
4601 table->valid_flag |= 1 << i;
4602 break;
4603 }
4604 }
4605 }
4606}
4607
4608static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4609{
4610 u32 i;
4611 u16 address;
4612
4613 for (i = 0; i < table->last; i++) {
4614 table->mc_reg_address[i].s0 =
4615 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4616 address : table->mc_reg_address[i].s1;
4617 }
4618}
4619
4620static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4621 struct ci_mc_reg_table *ci_table)
4622{
4623 u8 i, j;
4624
4625 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4626 return -EINVAL;
4627 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4628 return -EINVAL;
4629
4630 for (i = 0; i < table->last; i++)
4631 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4632
4633 ci_table->last = table->last;
4634
4635 for (i = 0; i < table->num_entries; i++) {
4636 ci_table->mc_reg_table_entry[i].mclk_max =
4637 table->mc_reg_table_entry[i].mclk_max;
4638 for (j = 0; j < table->last; j++)
4639 ci_table->mc_reg_table_entry[i].mc_data[j] =
4640 table->mc_reg_table_entry[i].mc_data[j];
4641 }
4642 ci_table->num_entries = table->num_entries;
4643
4644 return 0;
4645}
4646
4647static int ci_register_patching_mc_seq(struct amdgpu_device *adev,
4648 struct ci_mc_reg_table *table)
4649{
4650 u8 i, k;
4651 u32 tmp;
4652 bool patch;
4653
4654 tmp = RREG32(mmMC_SEQ_MISC0);
4655 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4656
4657 if (patch &&
4658 ((adev->pdev->device == 0x67B0) ||
4659 (adev->pdev->device == 0x67B1))) {
4660 for (i = 0; i < table->last; i++) {
4661 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4662 return -EINVAL;
4663 switch (table->mc_reg_address[i].s1) {
4664 case mmMC_SEQ_MISC1:
4665 for (k = 0; k < table->num_entries; k++) {
4666 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4667 (table->mc_reg_table_entry[k].mclk_max == 137500))
4668 table->mc_reg_table_entry[k].mc_data[i] =
4669 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4670 0x00000007;
4671 }
4672 break;
4673 case mmMC_SEQ_WR_CTL_D0:
4674 for (k = 0; k < table->num_entries; k++) {
4675 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4676 (table->mc_reg_table_entry[k].mclk_max == 137500))
4677 table->mc_reg_table_entry[k].mc_data[i] =
4678 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4679 0x0000D0DD;
4680 }
4681 break;
4682 case mmMC_SEQ_WR_CTL_D1:
4683 for (k = 0; k < table->num_entries; k++) {
4684 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4685 (table->mc_reg_table_entry[k].mclk_max == 137500))
4686 table->mc_reg_table_entry[k].mc_data[i] =
4687 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4688 0x0000D0DD;
4689 }
4690 break;
4691 case mmMC_SEQ_WR_CTL_2:
4692 for (k = 0; k < table->num_entries; k++) {
4693 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4694 (table->mc_reg_table_entry[k].mclk_max == 137500))
4695 table->mc_reg_table_entry[k].mc_data[i] = 0;
4696 }
4697 break;
4698 case mmMC_SEQ_CAS_TIMING:
4699 for (k = 0; k < table->num_entries; k++) {
4700 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4701 table->mc_reg_table_entry[k].mc_data[i] =
4702 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4703 0x000C0140;
4704 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4705 table->mc_reg_table_entry[k].mc_data[i] =
4706 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4707 0x000C0150;
4708 }
4709 break;
4710 case mmMC_SEQ_MISC_TIMING:
4711 for (k = 0; k < table->num_entries; k++) {
4712 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4713 table->mc_reg_table_entry[k].mc_data[i] =
4714 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4715 0x00000030;
4716 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4717 table->mc_reg_table_entry[k].mc_data[i] =
4718 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4719 0x00000035;
4720 }
4721 break;
4722 default:
4723 break;
4724 }
4725 }
4726
4727 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4728 tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
4729 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4730 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4731 WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
4732 }
4733
4734 return 0;
4735}
4736
4737static int ci_initialize_mc_reg_table(struct amdgpu_device *adev)
4738{
4739 struct ci_power_info *pi = ci_get_pi(adev);
4740 struct atom_mc_reg_table *table;
4741 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4742 u8 module_index = ci_get_memory_module_index(adev);
4743 int ret;
4744
4745 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4746 if (!table)
4747 return -ENOMEM;
4748
4749 WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
4750 WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
4751 WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
4752 WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
4753 WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
4754 WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
4755 WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
4756 WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
4757 WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
4758 WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
4759 WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
4760 WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
4761 WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
4762 WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
4763 WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
4764 WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
4765 WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
4766 WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
4767 WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
4768 WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
4769
4770 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
4771 if (ret)
4772 goto init_mc_done;
4773
4774 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4775 if (ret)
4776 goto init_mc_done;
4777
4778 ci_set_s0_mc_reg_index(ci_table);
4779
4780 ret = ci_register_patching_mc_seq(adev, ci_table);
4781 if (ret)
4782 goto init_mc_done;
4783
4784 ret = ci_set_mc_special_registers(adev, ci_table);
4785 if (ret)
4786 goto init_mc_done;
4787
4788 ci_set_valid_flag(ci_table);
4789
4790init_mc_done:
4791 kfree(table);
4792
4793 return ret;
4794}
4795
4796static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev,
4797 SMU7_Discrete_MCRegisters *mc_reg_table)
4798{
4799 struct ci_power_info *pi = ci_get_pi(adev);
4800 u32 i, j;
4801
4802 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4803 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4804 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4805 return -EINVAL;
4806 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4807 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4808 i++;
4809 }
4810 }
4811
4812 mc_reg_table->last = (u8)i;
4813
4814 return 0;
4815}
4816
4817static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4818 SMU7_Discrete_MCRegisterSet *data,
4819 u32 num_entries, u32 valid_flag)
4820{
4821 u32 i, j;
4822
4823 for (i = 0, j = 0; j < num_entries; j++) {
4824 if (valid_flag & (1 << j)) {
4825 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4826 i++;
4827 }
4828 }
4829}
4830
4831static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
4832 const u32 memory_clock,
4833 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4834{
4835 struct ci_power_info *pi = ci_get_pi(adev);
4836 u32 i = 0;
4837
4838 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4839 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4840 break;
4841 }
4842
4843 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4844 --i;
4845
4846 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4847 mc_reg_table_data, pi->mc_reg_table.last,
4848 pi->mc_reg_table.valid_flag);
4849}
4850
4851static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
4852 SMU7_Discrete_MCRegisters *mc_reg_table)
4853{
4854 struct ci_power_info *pi = ci_get_pi(adev);
4855 u32 i;
4856
4857 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4858 ci_convert_mc_reg_table_entry_to_smc(adev,
4859 pi->dpm_table.mclk_table.dpm_levels[i].value,
4860 &mc_reg_table->data[i]);
4861}
4862
4863static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev)
4864{
4865 struct ci_power_info *pi = ci_get_pi(adev);
4866 int ret;
4867
4868 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4869
4870 ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);
4871 if (ret)
4872 return ret;
4873 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4874
4875 return amdgpu_ci_copy_bytes_to_smc(adev,
4876 pi->mc_reg_table_start,
4877 (u8 *)&pi->smc_mc_reg_table,
4878 sizeof(SMU7_Discrete_MCRegisters),
4879 pi->sram_end);
4880}
4881
4882static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev)
4883{
4884 struct ci_power_info *pi = ci_get_pi(adev);
4885
4886 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4887 return 0;
4888
4889 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4890
4891 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4892
4893 return amdgpu_ci_copy_bytes_to_smc(adev,
4894 pi->mc_reg_table_start +
4895 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4896 (u8 *)&pi->smc_mc_reg_table.data[0],
4897 sizeof(SMU7_Discrete_MCRegisterSet) *
4898 pi->dpm_table.mclk_table.count,
4899 pi->sram_end);
4900}
4901
4902static void ci_enable_voltage_control(struct amdgpu_device *adev)
4903{
4904 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
4905
4906 tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
4907 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
4908}
4909
4910static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev,
4911 struct amdgpu_ps *amdgpu_state)
4912{
4913 struct ci_ps *state = ci_get_ps(amdgpu_state);
4914 int i;
4915 u16 pcie_speed, max_speed = 0;
4916
4917 for (i = 0; i < state->performance_level_count; i++) {
4918 pcie_speed = state->performance_levels[i].pcie_gen;
4919 if (max_speed < pcie_speed)
4920 max_speed = pcie_speed;
4921 }
4922
4923 return max_speed;
4924}
4925
4926static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev)
4927{
4928 u32 speed_cntl = 0;
4929
4930 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) &
4931 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
4932 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4933
4934 return (u16)speed_cntl;
4935}
4936
4937static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev)
4938{
4939 u32 link_width = 0;
4940
4941 link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) &
4942 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK;
4943 link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
4944
4945 switch (link_width) {
4946 case 1:
4947 return 1;
4948 case 2:
4949 return 2;
4950 case 3:
4951 return 4;
4952 case 4:
4953 return 8;
4954 case 0:
4955 case 6:
4956 default:
4957 return 16;
4958 }
4959}
4960
4961static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
4962 struct amdgpu_ps *amdgpu_new_state,
4963 struct amdgpu_ps *amdgpu_current_state)
4964{
4965 struct ci_power_info *pi = ci_get_pi(adev);
4966 enum amdgpu_pcie_gen target_link_speed =
4967 ci_get_maximum_link_speed(adev, amdgpu_new_state);
4968 enum amdgpu_pcie_gen current_link_speed;
4969
4970 if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
4971 current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state);
4972 else
4973 current_link_speed = pi->force_pcie_gen;
4974
4975 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
4976 pi->pspp_notify_required = false;
4977 if (target_link_speed > current_link_speed) {
4978 switch (target_link_speed) {
4979#ifdef CONFIG_ACPI
4980 case AMDGPU_PCIE_GEN3:
4981 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4982 break;
4983 pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
4984 if (current_link_speed == AMDGPU_PCIE_GEN2)
4985 break;
4986 case AMDGPU_PCIE_GEN2:
4987 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4988 break;
4989#endif
4990 default:
4991 pi->force_pcie_gen = ci_get_current_pcie_speed(adev);
4992 break;
4993 }
4994 } else {
4995 if (target_link_speed < current_link_speed)
4996 pi->pspp_notify_required = true;
4997 }
4998}
4999
5000static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
5001 struct amdgpu_ps *amdgpu_new_state,
5002 struct amdgpu_ps *amdgpu_current_state)
5003{
5004 struct ci_power_info *pi = ci_get_pi(adev);
5005 enum amdgpu_pcie_gen target_link_speed =
5006 ci_get_maximum_link_speed(adev, amdgpu_new_state);
5007 u8 request;
5008
5009 if (pi->pspp_notify_required) {
5010 if (target_link_speed == AMDGPU_PCIE_GEN3)
5011 request = PCIE_PERF_REQ_PECI_GEN3;
5012 else if (target_link_speed == AMDGPU_PCIE_GEN2)
5013 request = PCIE_PERF_REQ_PECI_GEN2;
5014 else
5015 request = PCIE_PERF_REQ_PECI_GEN1;
5016
5017 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5018 (ci_get_current_pcie_speed(adev) > 0))
5019 return;
5020
5021#ifdef CONFIG_ACPI
5022 amdgpu_acpi_pcie_performance_request(adev, request, false);
5023#endif
5024 }
5025}
5026
5027static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev)
5028{
5029 struct ci_power_info *pi = ci_get_pi(adev);
5030 struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
5031 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
5032 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table =
5033 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
5034 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table =
5035 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
5036
5037 if (allowed_sclk_vddc_table == NULL)
5038 return -EINVAL;
5039 if (allowed_sclk_vddc_table->count < 1)
5040 return -EINVAL;
5041 if (allowed_mclk_vddc_table == NULL)
5042 return -EINVAL;
5043 if (allowed_mclk_vddc_table->count < 1)
5044 return -EINVAL;
5045 if (allowed_mclk_vddci_table == NULL)
5046 return -EINVAL;
5047 if (allowed_mclk_vddci_table->count < 1)
5048 return -EINVAL;
5049
5050 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
5051 pi->max_vddc_in_pp_table =
5052 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5053
5054 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
5055 pi->max_vddci_in_pp_table =
5056 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5057
5058 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
5059 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5060 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
5061 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5062 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
5063 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5064 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
5065 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5066
5067 return 0;
5068}
5069
5070static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc)
5071{
5072 struct ci_power_info *pi = ci_get_pi(adev);
5073 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
5074 u32 leakage_index;
5075
5076 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5077 if (leakage_table->leakage_id[leakage_index] == *vddc) {
5078 *vddc = leakage_table->actual_voltage[leakage_index];
5079 break;
5080 }
5081 }
5082}
5083
5084static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci)
5085{
5086 struct ci_power_info *pi = ci_get_pi(adev);
5087 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
5088 u32 leakage_index;
5089
5090 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5091 if (leakage_table->leakage_id[leakage_index] == *vddci) {
5092 *vddci = leakage_table->actual_voltage[leakage_index];
5093 break;
5094 }
5095 }
5096}
5097
5098static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5099 struct amdgpu_clock_voltage_dependency_table *table)
5100{
5101 u32 i;
5102
5103 if (table) {
5104 for (i = 0; i < table->count; i++)
5105 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5106 }
5107}
5108
5109static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev,
5110 struct amdgpu_clock_voltage_dependency_table *table)
5111{
5112 u32 i;
5113
5114 if (table) {
5115 for (i = 0; i < table->count; i++)
5116 ci_patch_with_vddci_leakage(adev, &table->entries[i].v);
5117 }
5118}
5119
5120static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5121 struct amdgpu_vce_clock_voltage_dependency_table *table)
5122{
5123 u32 i;
5124
5125 if (table) {
5126 for (i = 0; i < table->count; i++)
5127 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5128 }
5129}
5130
5131static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5132 struct amdgpu_uvd_clock_voltage_dependency_table *table)
5133{
5134 u32 i;
5135
5136 if (table) {
5137 for (i = 0; i < table->count; i++)
5138 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5139 }
5140}
5141
5142static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev,
5143 struct amdgpu_phase_shedding_limits_table *table)
5144{
5145 u32 i;
5146
5147 if (table) {
5148 for (i = 0; i < table->count; i++)
5149 ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);
5150 }
5151}
5152
5153static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev,
5154 struct amdgpu_clock_and_voltage_limits *table)
5155{
5156 if (table) {
5157 ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);
5158 ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);
5159 }
5160}
5161
5162static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev,
5163 struct amdgpu_cac_leakage_table *table)
5164{
5165 u32 i;
5166
5167 if (table) {
5168 for (i = 0; i < table->count; i++)
5169 ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);
5170 }
5171}
5172
5173static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev)
5174{
5175
5176 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5177 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5178 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5179 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5180 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5181 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5182 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev,
5183 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5184 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev,
5185 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5186 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev,
5187 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5188 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5189 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5190 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5191 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5192 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev,
5193 &adev->pm.dpm.dyn_state.phase_shedding_limits_table);
5194 ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5195 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5196 ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5197 &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5198 ci_patch_cac_leakage_table_with_vddc_leakage(adev,
5199 &adev->pm.dpm.dyn_state.cac_leakage_table);
5200
5201}
5202
5203static void ci_update_current_ps(struct amdgpu_device *adev,
5204 struct amdgpu_ps *rps)
5205{
5206 struct ci_ps *new_ps = ci_get_ps(rps);
5207 struct ci_power_info *pi = ci_get_pi(adev);
5208
5209 pi->current_rps = *rps;
5210 pi->current_ps = *new_ps;
5211 pi->current_rps.ps_priv = &pi->current_ps;
5212}
5213
5214static void ci_update_requested_ps(struct amdgpu_device *adev,
5215 struct amdgpu_ps *rps)
5216{
5217 struct ci_ps *new_ps = ci_get_ps(rps);
5218 struct ci_power_info *pi = ci_get_pi(adev);
5219
5220 pi->requested_rps = *rps;
5221 pi->requested_ps = *new_ps;
5222 pi->requested_rps.ps_priv = &pi->requested_ps;
5223}
5224
5225static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
5226{
5227 struct ci_power_info *pi = ci_get_pi(adev);
5228 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
5229 struct amdgpu_ps *new_ps = &requested_ps;
5230
5231 ci_update_requested_ps(adev, new_ps);
5232
5233 ci_apply_state_adjust_rules(adev, &pi->requested_rps);
5234
5235 return 0;
5236}
5237
5238static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)
5239{
5240 struct ci_power_info *pi = ci_get_pi(adev);
5241 struct amdgpu_ps *new_ps = &pi->requested_rps;
5242
5243 ci_update_current_ps(adev, new_ps);
5244}
5245
5246
5247static void ci_dpm_setup_asic(struct amdgpu_device *adev)
5248{
5249 ci_read_clock_registers(adev);
5250 ci_enable_acpi_power_management(adev);
5251 ci_init_sclk_t(adev);
5252}
5253
5254static int ci_dpm_enable(struct amdgpu_device *adev)
5255{
5256 struct ci_power_info *pi = ci_get_pi(adev);
5257 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5258 int ret;
5259
5260 if (amdgpu_ci_is_smc_running(adev))
5261 return -EINVAL;
5262 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5263 ci_enable_voltage_control(adev);
5264 ret = ci_construct_voltage_tables(adev);
5265 if (ret) {
5266 DRM_ERROR("ci_construct_voltage_tables failed\n");
5267 return ret;
5268 }
5269 }
5270 if (pi->caps_dynamic_ac_timing) {
5271 ret = ci_initialize_mc_reg_table(adev);
5272 if (ret)
5273 pi->caps_dynamic_ac_timing = false;
5274 }
5275 if (pi->dynamic_ss)
5276 ci_enable_spread_spectrum(adev, true);
5277 if (pi->thermal_protection)
5278 ci_enable_thermal_protection(adev, true);
5279 ci_program_sstp(adev);
5280 ci_enable_display_gap(adev);
5281 ci_program_vc(adev);
5282 ret = ci_upload_firmware(adev);
5283 if (ret) {
5284 DRM_ERROR("ci_upload_firmware failed\n");
5285 return ret;
5286 }
5287 ret = ci_process_firmware_header(adev);
5288 if (ret) {
5289 DRM_ERROR("ci_process_firmware_header failed\n");
5290 return ret;
5291 }
5292 ret = ci_initial_switch_from_arb_f0_to_f1(adev);
5293 if (ret) {
5294 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5295 return ret;
5296 }
5297 ret = ci_init_smc_table(adev);
5298 if (ret) {
5299 DRM_ERROR("ci_init_smc_table failed\n");
5300 return ret;
5301 }
5302 ret = ci_init_arb_table_index(adev);
5303 if (ret) {
5304 DRM_ERROR("ci_init_arb_table_index failed\n");
5305 return ret;
5306 }
5307 if (pi->caps_dynamic_ac_timing) {
5308 ret = ci_populate_initial_mc_reg_table(adev);
5309 if (ret) {
5310 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5311 return ret;
5312 }
5313 }
5314 ret = ci_populate_pm_base(adev);
5315 if (ret) {
5316 DRM_ERROR("ci_populate_pm_base failed\n");
5317 return ret;
5318 }
5319 ci_dpm_start_smc(adev);
5320 ci_enable_vr_hot_gpio_interrupt(adev);
5321 ret = ci_notify_smc_display_change(adev, false);
5322 if (ret) {
5323 DRM_ERROR("ci_notify_smc_display_change failed\n");
5324 return ret;
5325 }
5326 ci_enable_sclk_control(adev, true);
5327 ret = ci_enable_ulv(adev, true);
5328 if (ret) {
5329 DRM_ERROR("ci_enable_ulv failed\n");
5330 return ret;
5331 }
5332 ret = ci_enable_ds_master_switch(adev, true);
5333 if (ret) {
5334 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5335 return ret;
5336 }
5337 ret = ci_start_dpm(adev);
5338 if (ret) {
5339 DRM_ERROR("ci_start_dpm failed\n");
5340 return ret;
5341 }
5342 ret = ci_enable_didt(adev, true);
5343 if (ret) {
5344 DRM_ERROR("ci_enable_didt failed\n");
5345 return ret;
5346 }
5347 ret = ci_enable_smc_cac(adev, true);
5348 if (ret) {
5349 DRM_ERROR("ci_enable_smc_cac failed\n");
5350 return ret;
5351 }
5352 ret = ci_enable_power_containment(adev, true);
5353 if (ret) {
5354 DRM_ERROR("ci_enable_power_containment failed\n");
5355 return ret;
5356 }
5357
5358 ret = ci_power_control_set_level(adev);
5359 if (ret) {
5360 DRM_ERROR("ci_power_control_set_level failed\n");
5361 return ret;
5362 }
5363
5364 ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5365
5366 ret = ci_enable_thermal_based_sclk_dpm(adev, true);
5367 if (ret) {
5368 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5369 return ret;
5370 }
5371
5372 ci_thermal_start_thermal_controller(adev);
5373
5374 ci_update_current_ps(adev, boot_ps);
5375
5376 return 0;
5377}
5378
5379static void ci_dpm_disable(struct amdgpu_device *adev)
5380{
5381 struct ci_power_info *pi = ci_get_pi(adev);
5382 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5383
5384 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5385 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
5386 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5387 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
5388
5389 ci_dpm_powergate_uvd(adev, false);
5390
5391 if (!amdgpu_ci_is_smc_running(adev))
5392 return;
5393
5394 ci_thermal_stop_thermal_controller(adev);
5395
5396 if (pi->thermal_protection)
5397 ci_enable_thermal_protection(adev, false);
5398 ci_enable_power_containment(adev, false);
5399 ci_enable_smc_cac(adev, false);
5400 ci_enable_didt(adev, false);
5401 ci_enable_spread_spectrum(adev, false);
5402 ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5403 ci_stop_dpm(adev);
5404 ci_enable_ds_master_switch(adev, false);
5405 ci_enable_ulv(adev, false);
5406 ci_clear_vc(adev);
5407 ci_reset_to_default(adev);
5408 ci_dpm_stop_smc(adev);
5409 ci_force_switch_to_arb_f0(adev);
5410 ci_enable_thermal_based_sclk_dpm(adev, false);
5411
5412 ci_update_current_ps(adev, boot_ps);
5413}
5414
5415static int ci_dpm_set_power_state(struct amdgpu_device *adev)
5416{
5417 struct ci_power_info *pi = ci_get_pi(adev);
5418 struct amdgpu_ps *new_ps = &pi->requested_rps;
5419 struct amdgpu_ps *old_ps = &pi->current_rps;
5420 int ret;
5421
5422 ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps);
5423 if (pi->pcie_performance_request)
5424 ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
5425 ret = ci_freeze_sclk_mclk_dpm(adev);
5426 if (ret) {
5427 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5428 return ret;
5429 }
5430 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps);
5431 if (ret) {
5432 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5433 return ret;
5434 }
5435 ret = ci_generate_dpm_level_enable_mask(adev, new_ps);
5436 if (ret) {
5437 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5438 return ret;
5439 }
5440
5441 ret = ci_update_vce_dpm(adev, new_ps, old_ps);
5442 if (ret) {
5443 DRM_ERROR("ci_update_vce_dpm failed\n");
5444 return ret;
5445 }
5446
5447 ret = ci_update_sclk_t(adev);
5448 if (ret) {
5449 DRM_ERROR("ci_update_sclk_t failed\n");
5450 return ret;
5451 }
5452 if (pi->caps_dynamic_ac_timing) {
5453 ret = ci_update_and_upload_mc_reg_table(adev);
5454 if (ret) {
5455 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5456 return ret;
5457 }
5458 }
5459 ret = ci_program_memory_timing_parameters(adev);
5460 if (ret) {
5461 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5462 return ret;
5463 }
5464 ret = ci_unfreeze_sclk_mclk_dpm(adev);
5465 if (ret) {
5466 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5467 return ret;
5468 }
5469 ret = ci_upload_dpm_level_enable_mask(adev);
5470 if (ret) {
5471 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5472 return ret;
5473 }
5474 if (pi->pcie_performance_request)
5475 ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
5476
5477 return 0;
5478}
5479
5480#if 0
5481static void ci_dpm_reset_asic(struct amdgpu_device *adev)
5482{
5483 ci_set_boot_state(adev);
5484}
5485#endif
5486
5487static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)
5488{
5489 ci_program_display_gap(adev);
5490}
5491
5492union power_info {
5493 struct _ATOM_POWERPLAY_INFO info;
5494 struct _ATOM_POWERPLAY_INFO_V2 info_2;
5495 struct _ATOM_POWERPLAY_INFO_V3 info_3;
5496 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5497 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5498 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5499};
5500
5501union pplib_clock_info {
5502 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5503 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5504 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5505 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5506 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5507 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5508};
5509
5510union pplib_power_state {
5511 struct _ATOM_PPLIB_STATE v1;
5512 struct _ATOM_PPLIB_STATE_V2 v2;
5513};
5514
5515static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev,
5516 struct amdgpu_ps *rps,
5517 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5518 u8 table_rev)
5519{
5520 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5521 rps->class = le16_to_cpu(non_clock_info->usClassification);
5522 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5523
5524 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5525 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5526 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5527 } else {
5528 rps->vclk = 0;
5529 rps->dclk = 0;
5530 }
5531
5532 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5533 adev->pm.dpm.boot_ps = rps;
5534 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5535 adev->pm.dpm.uvd_ps = rps;
5536}
5537
5538static void ci_parse_pplib_clock_info(struct amdgpu_device *adev,
5539 struct amdgpu_ps *rps, int index,
5540 union pplib_clock_info *clock_info)
5541{
5542 struct ci_power_info *pi = ci_get_pi(adev);
5543 struct ci_ps *ps = ci_get_ps(rps);
5544 struct ci_pl *pl = &ps->performance_levels[index];
5545
5546 ps->performance_level_count = index + 1;
5547
5548 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5549 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5550 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5551 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5552
5553 pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
5554 pi->sys_pcie_mask,
5555 pi->vbios_boot_state.pcie_gen_bootup_value,
5556 clock_info->ci.ucPCIEGen);
5557 pl->pcie_lane = amdgpu_get_pcie_lane_support(adev,
5558 pi->vbios_boot_state.pcie_lane_bootup_value,
5559 le16_to_cpu(clock_info->ci.usPCIELane));
5560
5561 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5562 pi->acpi_pcie_gen = pl->pcie_gen;
5563 }
5564
5565 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5566 pi->ulv.supported = true;
5567 pi->ulv.pl = *pl;
5568 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5569 }
5570
5571
5572 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5573 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5574 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5575 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5576 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5577 }
5578
5579 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5580 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5581 pi->use_pcie_powersaving_levels = true;
5582 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5583 pi->pcie_gen_powersaving.max = pl->pcie_gen;
5584 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5585 pi->pcie_gen_powersaving.min = pl->pcie_gen;
5586 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5587 pi->pcie_lane_powersaving.max = pl->pcie_lane;
5588 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5589 pi->pcie_lane_powersaving.min = pl->pcie_lane;
5590 break;
5591 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5592 pi->use_pcie_performance_levels = true;
5593 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5594 pi->pcie_gen_performance.max = pl->pcie_gen;
5595 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5596 pi->pcie_gen_performance.min = pl->pcie_gen;
5597 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5598 pi->pcie_lane_performance.max = pl->pcie_lane;
5599 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5600 pi->pcie_lane_performance.min = pl->pcie_lane;
5601 break;
5602 default:
5603 break;
5604 }
5605}
5606
5607static int ci_parse_power_table(struct amdgpu_device *adev)
5608{
5609 struct amdgpu_mode_info *mode_info = &adev->mode_info;
5610 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5611 union pplib_power_state *power_state;
5612 int i, j, k, non_clock_array_index, clock_array_index;
5613 union pplib_clock_info *clock_info;
5614 struct _StateArray *state_array;
5615 struct _ClockInfoArray *clock_info_array;
5616 struct _NonClockInfoArray *non_clock_info_array;
5617 union power_info *power_info;
5618 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5619 u16 data_offset;
5620 u8 frev, crev;
5621 u8 *power_state_offset;
5622 struct ci_ps *ps;
5623
5624 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5625 &frev, &crev, &data_offset))
5626 return -EINVAL;
5627 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5628
5629 amdgpu_add_thermal_controller(adev);
5630
5631 state_array = (struct _StateArray *)
5632 (mode_info->atom_context->bios + data_offset +
5633 le16_to_cpu(power_info->pplib.usStateArrayOffset));
5634 clock_info_array = (struct _ClockInfoArray *)
5635 (mode_info->atom_context->bios + data_offset +
5636 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5637 non_clock_info_array = (struct _NonClockInfoArray *)
5638 (mode_info->atom_context->bios + data_offset +
5639 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5640
5641 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
5642 state_array->ucNumEntries, GFP_KERNEL);
5643 if (!adev->pm.dpm.ps)
5644 return -ENOMEM;
5645 power_state_offset = (u8 *)state_array->states;
5646 for (i = 0; i < state_array->ucNumEntries; i++) {
5647 u8 *idx;
5648 power_state = (union pplib_power_state *)power_state_offset;
5649 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5650 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5651 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5652 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5653 if (ps == NULL) {
5654 kfree(adev->pm.dpm.ps);
5655 return -ENOMEM;
5656 }
5657 adev->pm.dpm.ps[i].ps_priv = ps;
5658 ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
5659 non_clock_info,
5660 non_clock_info_array->ucEntrySize);
5661 k = 0;
5662 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5663 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5664 clock_array_index = idx[j];
5665 if (clock_array_index >= clock_info_array->ucNumEntries)
5666 continue;
5667 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5668 break;
5669 clock_info = (union pplib_clock_info *)
5670 ((u8 *)&clock_info_array->clockInfo[0] +
5671 (clock_array_index * clock_info_array->ucEntrySize));
5672 ci_parse_pplib_clock_info(adev,
5673 &adev->pm.dpm.ps[i], k,
5674 clock_info);
5675 k++;
5676 }
5677 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5678 }
5679 adev->pm.dpm.num_ps = state_array->ucNumEntries;
5680
5681
5682 for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
5683 u32 sclk, mclk;
5684 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
5685 clock_info = (union pplib_clock_info *)
5686 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5687 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5688 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5689 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5690 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5691 adev->pm.dpm.vce_states[i].sclk = sclk;
5692 adev->pm.dpm.vce_states[i].mclk = mclk;
5693 }
5694
5695 return 0;
5696}
5697
5698static int ci_get_vbios_boot_values(struct amdgpu_device *adev,
5699 struct ci_vbios_boot_state *boot_state)
5700{
5701 struct amdgpu_mode_info *mode_info = &adev->mode_info;
5702 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5703 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5704 u8 frev, crev;
5705 u16 data_offset;
5706
5707 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5708 &frev, &crev, &data_offset)) {
5709 firmware_info =
5710 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5711 data_offset);
5712 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5713 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5714 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5715 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev);
5716 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev);
5717 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5718 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5719
5720 return 0;
5721 }
5722 return -EINVAL;
5723}
5724
5725static void ci_dpm_fini(struct amdgpu_device *adev)
5726{
5727 int i;
5728
5729 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
5730 kfree(adev->pm.dpm.ps[i].ps_priv);
5731 }
5732 kfree(adev->pm.dpm.ps);
5733 kfree(adev->pm.dpm.priv);
5734 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5735 amdgpu_free_extended_power_table(adev);
5736}
5737
5738
5739
5740
5741
5742
5743
5744
5745
5746
5747static int ci_dpm_init_microcode(struct amdgpu_device *adev)
5748{
5749 const char *chip_name;
5750 char fw_name[30];
5751 int err;
5752
5753 DRM_DEBUG("\n");
5754
5755 switch (adev->asic_type) {
5756 case CHIP_BONAIRE:
5757 chip_name = "bonaire";
5758 break;
5759 case CHIP_HAWAII:
5760 chip_name = "hawaii";
5761 break;
5762 case CHIP_KAVERI:
5763 case CHIP_KABINI:
5764 default: BUG();
5765 }
5766
5767 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
5768 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
5769 if (err)
5770 goto out;
5771 err = amdgpu_ucode_validate(adev->pm.fw);
5772
5773out:
5774 if (err) {
5775 printk(KERN_ERR
5776 "cik_smc: Failed to load firmware \"%s\"\n",
5777 fw_name);
5778 release_firmware(adev->pm.fw);
5779 adev->pm.fw = NULL;
5780 }
5781 return err;
5782}
5783
5784static int ci_dpm_init(struct amdgpu_device *adev)
5785{
5786 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5787 SMU7_Discrete_DpmTable *dpm_table;
5788 struct amdgpu_gpio_rec gpio;
5789 u16 data_offset, size;
5790 u8 frev, crev;
5791 struct ci_power_info *pi;
5792 int ret;
5793
5794 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5795 if (pi == NULL)
5796 return -ENOMEM;
5797 adev->pm.dpm.priv = pi;
5798
5799 pi->sys_pcie_mask =
5800 (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
5801 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
5802
5803 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5804
5805 pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
5806 pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;
5807 pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;
5808 pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;
5809
5810 pi->pcie_lane_performance.max = 0;
5811 pi->pcie_lane_performance.min = 16;
5812 pi->pcie_lane_powersaving.max = 0;
5813 pi->pcie_lane_powersaving.min = 16;
5814
5815 ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);
5816 if (ret) {
5817 ci_dpm_fini(adev);
5818 return ret;
5819 }
5820
5821 ret = amdgpu_get_platform_caps(adev);
5822 if (ret) {
5823 ci_dpm_fini(adev);
5824 return ret;
5825 }
5826
5827 ret = amdgpu_parse_extended_power_table(adev);
5828 if (ret) {
5829 ci_dpm_fini(adev);
5830 return ret;
5831 }
5832
5833 ret = ci_parse_power_table(adev);
5834 if (ret) {
5835 ci_dpm_fini(adev);
5836 return ret;
5837 }
5838
5839 pi->dll_default_on = false;
5840 pi->sram_end = SMC_RAM_END;
5841
5842 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5843 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5844 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5845 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5846 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5847 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5848 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5849 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5850
5851 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5852
5853 pi->sclk_dpm_key_disabled = 0;
5854 pi->mclk_dpm_key_disabled = 0;
5855 pi->pcie_dpm_key_disabled = 0;
5856 pi->thermal_sclk_dpm_enabled = 0;
5857
5858 pi->caps_sclk_ds = true;
5859
5860 pi->mclk_strobe_mode_threshold = 40000;
5861 pi->mclk_stutter_mode_threshold = 40000;
5862 pi->mclk_edc_enable_threshold = 40000;
5863 pi->mclk_edc_wr_enable_threshold = 40000;
5864
5865 ci_initialize_powertune_defaults(adev);
5866
5867 pi->caps_fps = false;
5868
5869 pi->caps_sclk_throttle_low_notification = false;
5870
5871 pi->caps_uvd_dpm = true;
5872 pi->caps_vce_dpm = true;
5873
5874 ci_get_leakage_voltages(adev);
5875 ci_patch_dependency_tables_with_leakage(adev);
5876 ci_set_private_data_variables_based_on_pptable(adev);
5877
5878 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5879 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
5880 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5881 ci_dpm_fini(adev);
5882 return -ENOMEM;
5883 }
5884 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5885 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5886 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5887 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5888 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5889 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5890 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5891 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5892 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5893
5894 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5895 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5896 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5897
5898 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5899 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5900 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5901 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5902
5903 if (adev->asic_type == CHIP_HAWAII) {
5904 pi->thermal_temp_setting.temperature_low = 94500;
5905 pi->thermal_temp_setting.temperature_high = 95000;
5906 pi->thermal_temp_setting.temperature_shutdown = 104000;
5907 } else {
5908 pi->thermal_temp_setting.temperature_low = 99500;
5909 pi->thermal_temp_setting.temperature_high = 100000;
5910 pi->thermal_temp_setting.temperature_shutdown = 104000;
5911 }
5912
5913 pi->uvd_enabled = false;
5914
5915 dpm_table = &pi->smc_state_table;
5916
5917 gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID);
5918 if (gpio.valid) {
5919 dpm_table->VRHotGpio = gpio.shift;
5920 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5921 } else {
5922 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5923 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5924 }
5925
5926 gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID);
5927 if (gpio.valid) {
5928 dpm_table->AcDcGpio = gpio.shift;
5929 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5930 } else {
5931 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5932 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5933 }
5934
5935 gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID);
5936 if (gpio.valid) {
5937 u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
5938
5939 switch (gpio.shift) {
5940 case 0:
5941 tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5942 tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5943 break;
5944 case 1:
5945 tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5946 tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5947 break;
5948 case 2:
5949 tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
5950 break;
5951 case 3:
5952 tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
5953 break;
5954 case 4:
5955 tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
5956 break;
5957 default:
5958 DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift);
5959 break;
5960 }
5961 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
5962 }
5963
5964 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5965 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5966 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5967 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5968 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5969 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5970 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5971
5972 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5973 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5974 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5975 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5976 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5977 else
5978 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5979 }
5980
5981 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5982 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5983 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5984 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5985 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5986 else
5987 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5988 }
5989
5990 pi->vddc_phase_shed_control = true;
5991
5992#if defined(CONFIG_ACPI)
5993 pi->pcie_performance_request =
5994 amdgpu_acpi_is_pcie_performance_request_supported(adev);
5995#else
5996 pi->pcie_performance_request = false;
5997#endif
5998
5999 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
6000 &frev, &crev, &data_offset)) {
6001 pi->caps_sclk_ss_support = true;
6002 pi->caps_mclk_ss_support = true;
6003 pi->dynamic_ss = true;
6004 } else {
6005 pi->caps_sclk_ss_support = false;
6006 pi->caps_mclk_ss_support = false;
6007 pi->dynamic_ss = true;
6008 }
6009
6010 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6011 pi->thermal_protection = true;
6012 else
6013 pi->thermal_protection = false;
6014
6015 pi->caps_dynamic_ac_timing = true;
6016
6017 pi->uvd_power_gated = false;
6018
6019
6020 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6021 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6022 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6023 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6024
6025 pi->fan_ctrl_is_in_default_mode = true;
6026
6027 return 0;
6028}
6029
6030static void
6031ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
6032 struct seq_file *m)
6033{
6034 struct ci_power_info *pi = ci_get_pi(adev);
6035 struct amdgpu_ps *rps = &pi->current_rps;
6036 u32 sclk = ci_get_average_sclk_freq(adev);
6037 u32 mclk = ci_get_average_mclk_freq(adev);
6038 u32 activity_percent = 50;
6039 int ret;
6040
6041 ret = ci_read_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, AverageGraphicsA),
6042 &activity_percent);
6043
6044 if (ret == 0) {
6045 activity_percent += 0x80;
6046 activity_percent >>= 8;
6047 activity_percent = activity_percent > 100 ? 100 : activity_percent;
6048 }
6049
6050 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
6051 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
6052 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
6053 sclk, mclk);
6054 seq_printf(m, "GPU load: %u %%\n", activity_percent);
6055}
6056
6057static void ci_dpm_print_power_state(struct amdgpu_device *adev,
6058 struct amdgpu_ps *rps)
6059{
6060 struct ci_ps *ps = ci_get_ps(rps);
6061 struct ci_pl *pl;
6062 int i;
6063
6064 amdgpu_dpm_print_class_info(rps->class, rps->class2);
6065 amdgpu_dpm_print_cap_info(rps->caps);
6066 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6067 for (i = 0; i < ps->performance_level_count; i++) {
6068 pl = &ps->performance_levels[i];
6069 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
6070 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
6071 }
6072 amdgpu_dpm_print_ps_status(adev, rps);
6073}
6074
6075static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
6076{
6077 struct ci_power_info *pi = ci_get_pi(adev);
6078 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6079
6080 if (low)
6081 return requested_state->performance_levels[0].sclk;
6082 else
6083 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
6084}
6085
6086static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
6087{
6088 struct ci_power_info *pi = ci_get_pi(adev);
6089 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6090
6091 if (low)
6092 return requested_state->performance_levels[0].mclk;
6093 else
6094 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
6095}
6096
6097
6098static int ci_dpm_get_temp(struct amdgpu_device *adev)
6099{
6100 u32 temp;
6101 int actual_temp = 0;
6102
6103 temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
6104 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
6105
6106 if (temp & 0x200)
6107 actual_temp = 255;
6108 else
6109 actual_temp = temp & 0x1ff;
6110
6111 actual_temp = actual_temp * 1000;
6112
6113 return actual_temp;
6114}
6115
6116static int ci_set_temperature_range(struct amdgpu_device *adev)
6117{
6118 int ret;
6119
6120 ret = ci_thermal_enable_alert(adev, false);
6121 if (ret)
6122 return ret;
6123 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
6124 CISLANDS_TEMP_RANGE_MAX);
6125 if (ret)
6126 return ret;
6127 ret = ci_thermal_enable_alert(adev, true);
6128 if (ret)
6129 return ret;
6130 return ret;
6131}
6132
6133static int ci_dpm_early_init(void *handle)
6134{
6135 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6136
6137 ci_dpm_set_dpm_funcs(adev);
6138 ci_dpm_set_irq_funcs(adev);
6139
6140 return 0;
6141}
6142
6143static int ci_dpm_late_init(void *handle)
6144{
6145 int ret;
6146 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6147
6148 if (!amdgpu_dpm)
6149 return 0;
6150
6151
6152 ret = amdgpu_pm_sysfs_init(adev);
6153 if (ret)
6154 return ret;
6155
6156 ret = ci_set_temperature_range(adev);
6157 if (ret)
6158 return ret;
6159
6160 ci_dpm_powergate_uvd(adev, true);
6161
6162 return 0;
6163}
6164
6165static int ci_dpm_sw_init(void *handle)
6166{
6167 int ret;
6168 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6169
6170 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
6171 if (ret)
6172 return ret;
6173
6174 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
6175 if (ret)
6176 return ret;
6177
6178
6179 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
6180 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
6181 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
6182 adev->pm.default_sclk = adev->clock.default_sclk;
6183 adev->pm.default_mclk = adev->clock.default_mclk;
6184 adev->pm.current_sclk = adev->clock.default_sclk;
6185 adev->pm.current_mclk = adev->clock.default_mclk;
6186 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
6187
6188 if (amdgpu_dpm == 0)
6189 return 0;
6190
6191 ret = ci_dpm_init_microcode(adev);
6192 if (ret)
6193 return ret;
6194
6195 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
6196 mutex_lock(&adev->pm.mutex);
6197 ret = ci_dpm_init(adev);
6198 if (ret)
6199 goto dpm_failed;
6200 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6201 if (amdgpu_dpm == 1)
6202 amdgpu_pm_print_power_states(adev);
6203 mutex_unlock(&adev->pm.mutex);
6204 DRM_INFO("amdgpu: dpm initialized\n");
6205
6206 return 0;
6207
6208dpm_failed:
6209 ci_dpm_fini(adev);
6210 mutex_unlock(&adev->pm.mutex);
6211 DRM_ERROR("amdgpu: dpm initialization failed\n");
6212 return ret;
6213}
6214
6215static int ci_dpm_sw_fini(void *handle)
6216{
6217 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6218
6219 mutex_lock(&adev->pm.mutex);
6220 amdgpu_pm_sysfs_fini(adev);
6221 ci_dpm_fini(adev);
6222 mutex_unlock(&adev->pm.mutex);
6223
6224 release_firmware(adev->pm.fw);
6225 adev->pm.fw = NULL;
6226
6227 return 0;
6228}
6229
6230static int ci_dpm_hw_init(void *handle)
6231{
6232 int ret;
6233
6234 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6235
6236 if (!amdgpu_dpm)
6237 return 0;
6238
6239 mutex_lock(&adev->pm.mutex);
6240 ci_dpm_setup_asic(adev);
6241 ret = ci_dpm_enable(adev);
6242 if (ret)
6243 adev->pm.dpm_enabled = false;
6244 else
6245 adev->pm.dpm_enabled = true;
6246 mutex_unlock(&adev->pm.mutex);
6247
6248 return ret;
6249}
6250
6251static int ci_dpm_hw_fini(void *handle)
6252{
6253 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6254
6255 if (adev->pm.dpm_enabled) {
6256 mutex_lock(&adev->pm.mutex);
6257 ci_dpm_disable(adev);
6258 mutex_unlock(&adev->pm.mutex);
6259 }
6260
6261 return 0;
6262}
6263
6264static int ci_dpm_suspend(void *handle)
6265{
6266 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6267
6268 if (adev->pm.dpm_enabled) {
6269 mutex_lock(&adev->pm.mutex);
6270
6271 ci_dpm_disable(adev);
6272
6273 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6274 mutex_unlock(&adev->pm.mutex);
6275 }
6276 return 0;
6277}
6278
6279static int ci_dpm_resume(void *handle)
6280{
6281 int ret;
6282 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6283
6284 if (adev->pm.dpm_enabled) {
6285
6286 mutex_lock(&adev->pm.mutex);
6287 ci_dpm_setup_asic(adev);
6288 ret = ci_dpm_enable(adev);
6289 if (ret)
6290 adev->pm.dpm_enabled = false;
6291 else
6292 adev->pm.dpm_enabled = true;
6293 mutex_unlock(&adev->pm.mutex);
6294 if (adev->pm.dpm_enabled)
6295 amdgpu_pm_compute_clocks(adev);
6296 }
6297 return 0;
6298}
6299
6300static bool ci_dpm_is_idle(void *handle)
6301{
6302
6303 return true;
6304}
6305
6306static int ci_dpm_wait_for_idle(void *handle)
6307{
6308
6309 return 0;
6310}
6311
6312static int ci_dpm_soft_reset(void *handle)
6313{
6314 return 0;
6315}
6316
6317static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
6318 struct amdgpu_irq_src *source,
6319 unsigned type,
6320 enum amdgpu_interrupt_state state)
6321{
6322 u32 cg_thermal_int;
6323
6324 switch (type) {
6325 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
6326 switch (state) {
6327 case AMDGPU_IRQ_STATE_DISABLE:
6328 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6329 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6330 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6331 break;
6332 case AMDGPU_IRQ_STATE_ENABLE:
6333 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6334 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6335 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6336 break;
6337 default:
6338 break;
6339 }
6340 break;
6341
6342 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
6343 switch (state) {
6344 case AMDGPU_IRQ_STATE_DISABLE:
6345 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6346 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6347 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6348 break;
6349 case AMDGPU_IRQ_STATE_ENABLE:
6350 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6351 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6352 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6353 break;
6354 default:
6355 break;
6356 }
6357 break;
6358
6359 default:
6360 break;
6361 }
6362 return 0;
6363}
6364
6365static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
6366 struct amdgpu_irq_src *source,
6367 struct amdgpu_iv_entry *entry)
6368{
6369 bool queue_thermal = false;
6370
6371 if (entry == NULL)
6372 return -EINVAL;
6373
6374 switch (entry->src_id) {
6375 case 230:
6376 DRM_DEBUG("IH: thermal low to high\n");
6377 adev->pm.dpm.thermal.high_to_low = false;
6378 queue_thermal = true;
6379 break;
6380 case 231:
6381 DRM_DEBUG("IH: thermal high to low\n");
6382 adev->pm.dpm.thermal.high_to_low = true;
6383 queue_thermal = true;
6384 break;
6385 default:
6386 break;
6387 }
6388
6389 if (queue_thermal)
6390 schedule_work(&adev->pm.dpm.thermal.work);
6391
6392 return 0;
6393}
6394
6395static int ci_dpm_set_clockgating_state(void *handle,
6396 enum amd_clockgating_state state)
6397{
6398 return 0;
6399}
6400
6401static int ci_dpm_set_powergating_state(void *handle,
6402 enum amd_powergating_state state)
6403{
6404 return 0;
6405}
6406
6407const struct amd_ip_funcs ci_dpm_ip_funcs = {
6408 .name = "ci_dpm",
6409 .early_init = ci_dpm_early_init,
6410 .late_init = ci_dpm_late_init,
6411 .sw_init = ci_dpm_sw_init,
6412 .sw_fini = ci_dpm_sw_fini,
6413 .hw_init = ci_dpm_hw_init,
6414 .hw_fini = ci_dpm_hw_fini,
6415 .suspend = ci_dpm_suspend,
6416 .resume = ci_dpm_resume,
6417 .is_idle = ci_dpm_is_idle,
6418 .wait_for_idle = ci_dpm_wait_for_idle,
6419 .soft_reset = ci_dpm_soft_reset,
6420 .set_clockgating_state = ci_dpm_set_clockgating_state,
6421 .set_powergating_state = ci_dpm_set_powergating_state,
6422};
6423
6424static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
6425 .get_temperature = &ci_dpm_get_temp,
6426 .pre_set_power_state = &ci_dpm_pre_set_power_state,
6427 .set_power_state = &ci_dpm_set_power_state,
6428 .post_set_power_state = &ci_dpm_post_set_power_state,
6429 .display_configuration_changed = &ci_dpm_display_configuration_changed,
6430 .get_sclk = &ci_dpm_get_sclk,
6431 .get_mclk = &ci_dpm_get_mclk,
6432 .print_power_state = &ci_dpm_print_power_state,
6433 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
6434 .force_performance_level = &ci_dpm_force_performance_level,
6435 .vblank_too_short = &ci_dpm_vblank_too_short,
6436 .powergate_uvd = &ci_dpm_powergate_uvd,
6437 .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
6438 .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
6439 .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
6440 .get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
6441};
6442
6443static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
6444{
6445 if (adev->pm.funcs == NULL)
6446 adev->pm.funcs = &ci_dpm_funcs;
6447}
6448
6449static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
6450 .set = ci_dpm_set_interrupt_state,
6451 .process = ci_dpm_process_interrupt,
6452};
6453
6454static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
6455{
6456 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
6457 adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;
6458}
6459
