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33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <rdma/ib_umem.h>
36#include <linux/atomic.h>
37#include <rdma/ib_user_verbs.h>
38
39#include "iw_cxgb4.h"
40
41int use_dsgl = 0;
42module_param(use_dsgl, int, 0644);
43MODULE_PARM_DESC(use_dsgl, "Use DSGL for PBL/FastReg (default=0)");
44
45#define T4_ULPTX_MIN_IO 32
46#define C4IW_MAX_INLINE_SIZE 96
47#define T4_ULPTX_MAX_DMA 1024
48#define C4IW_INLINE_THRESHOLD 128
49
50static int inline_threshold = C4IW_INLINE_THRESHOLD;
51module_param(inline_threshold, int, 0644);
52MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)");
53
54static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length)
55{
56 return (is_t4(dev->rdev.lldi.adapter_type) ||
57 is_t5(dev->rdev.lldi.adapter_type)) &&
58 length >= 8*1024*1024*1024ULL;
59}
60
61static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
62 u32 len, dma_addr_t data, int wait)
63{
64 struct sk_buff *skb;
65 struct ulp_mem_io *req;
66 struct ulptx_sgl *sgl;
67 u8 wr_len;
68 int ret = 0;
69 struct c4iw_wr_wait wr_wait;
70
71 addr &= 0x7FFFFFF;
72
73 if (wait)
74 c4iw_init_wr_wait(&wr_wait);
75 wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16);
76
77 skb = alloc_skb(wr_len, GFP_KERNEL);
78 if (!skb)
79 return -ENOMEM;
80 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
81
82 req = (struct ulp_mem_io *)__skb_put(skb, wr_len);
83 memset(req, 0, wr_len);
84 INIT_ULPTX_WR(req, wr_len, 0, 0);
85 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
86 (wait ? FW_WR_COMPL_F : 0));
87 req->wr.wr_lo = wait ? (__force __be64)(unsigned long) &wr_wait : 0L;
88 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
89 req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE) |
90 T5_ULP_MEMIO_ORDER_V(1) |
91 T5_ULP_MEMIO_FID_V(rdev->lldi.rxq_ids[0]));
92 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(len>>5));
93 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 16));
94 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr));
95
96 sgl = (struct ulptx_sgl *)(req + 1);
97 sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
98 ULPTX_NSGE_V(1));
99 sgl->len0 = cpu_to_be32(len);
100 sgl->addr0 = cpu_to_be64(data);
101
102 ret = c4iw_ofld_send(rdev, skb);
103 if (ret)
104 return ret;
105 if (wait)
106 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
107 return ret;
108}
109
110static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
111 void *data)
112{
113 struct sk_buff *skb;
114 struct ulp_mem_io *req;
115 struct ulptx_idata *sc;
116 u8 wr_len, *to_dp, *from_dp;
117 int copy_len, num_wqe, i, ret = 0;
118 struct c4iw_wr_wait wr_wait;
119 __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE));
120
121 if (is_t4(rdev->lldi.adapter_type))
122 cmd |= cpu_to_be32(ULP_MEMIO_ORDER_F);
123 else
124 cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F);
125
126 addr &= 0x7FFFFFF;
127 PDBG("%s addr 0x%x len %u\n", __func__, addr, len);
128 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE);
129 c4iw_init_wr_wait(&wr_wait);
130 for (i = 0; i < num_wqe; i++) {
131
132 copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE :
133 len;
134 wr_len = roundup(sizeof *req + sizeof *sc +
135 roundup(copy_len, T4_ULPTX_MIN_IO), 16);
136
137 skb = alloc_skb(wr_len, GFP_KERNEL);
138 if (!skb)
139 return -ENOMEM;
140 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
141
142 req = (struct ulp_mem_io *)__skb_put(skb, wr_len);
143 memset(req, 0, wr_len);
144 INIT_ULPTX_WR(req, wr_len, 0, 0);
145
146 if (i == (num_wqe-1)) {
147 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
148 FW_WR_COMPL_F);
149 req->wr.wr_lo = (__force __be64)(unsigned long)&wr_wait;
150 } else
151 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR));
152 req->wr.wr_mid = cpu_to_be32(
153 FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
154
155 req->cmd = cmd;
156 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(
157 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO)));
158 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr),
159 16));
160 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr + i * 3));
161
162 sc = (struct ulptx_idata *)(req + 1);
163 sc->cmd_more = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_IMM));
164 sc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO));
165
166 to_dp = (u8 *)(sc + 1);
167 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE;
168 if (data)
169 memcpy(to_dp, from_dp, copy_len);
170 else
171 memset(to_dp, 0, copy_len);
172 if (copy_len % T4_ULPTX_MIN_IO)
173 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO -
174 (copy_len % T4_ULPTX_MIN_IO));
175 ret = c4iw_ofld_send(rdev, skb);
176 if (ret)
177 return ret;
178 len -= C4IW_MAX_INLINE_SIZE;
179 }
180
181 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
182 return ret;
183}
184
185static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len, void *data)
186{
187 u32 remain = len;
188 u32 dmalen;
189 int ret = 0;
190 dma_addr_t daddr;
191 dma_addr_t save;
192
193 daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE);
194 if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr))
195 return -1;
196 save = daddr;
197
198 while (remain > inline_threshold) {
199 if (remain < T4_ULPTX_MAX_DMA) {
200 if (remain & ~T4_ULPTX_MIN_IO)
201 dmalen = remain & ~(T4_ULPTX_MIN_IO-1);
202 else
203 dmalen = remain;
204 } else
205 dmalen = T4_ULPTX_MAX_DMA;
206 remain -= dmalen;
207 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr,
208 !remain);
209 if (ret)
210 goto out;
211 addr += dmalen >> 5;
212 data += dmalen;
213 daddr += dmalen;
214 }
215 if (remain)
216 ret = _c4iw_write_mem_inline(rdev, addr, remain, data);
217out:
218 dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE);
219 return ret;
220}
221
222
223
224
225
226static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len,
227 void *data)
228{
229 if (is_t5(rdev->lldi.adapter_type) && use_dsgl) {
230 if (len > inline_threshold) {
231 if (_c4iw_write_mem_dma(rdev, addr, len, data)) {
232 printk_ratelimited(KERN_WARNING
233 "%s: dma map"
234 " failure (non fatal)\n",
235 pci_name(rdev->lldi.pdev));
236 return _c4iw_write_mem_inline(rdev, addr, len,
237 data);
238 } else
239 return 0;
240 } else
241 return _c4iw_write_mem_inline(rdev, addr, len, data);
242 } else
243 return _c4iw_write_mem_inline(rdev, addr, len, data);
244}
245
246
247
248
249
250
251
252static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
253 u32 *stag, u8 stag_state, u32 pdid,
254 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm,
255 int bind_enabled, u32 zbva, u64 to,
256 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr)
257{
258 int err;
259 struct fw_ri_tpte tpt;
260 u32 stag_idx;
261 static atomic_t key;
262
263 if (c4iw_fatal_error(rdev))
264 return -EIO;
265
266 stag_state = stag_state > 0;
267 stag_idx = (*stag) >> 8;
268
269 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) {
270 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table);
271 if (!stag_idx) {
272 mutex_lock(&rdev->stats.lock);
273 rdev->stats.stag.fail++;
274 mutex_unlock(&rdev->stats.lock);
275 return -ENOMEM;
276 }
277 mutex_lock(&rdev->stats.lock);
278 rdev->stats.stag.cur += 32;
279 if (rdev->stats.stag.cur > rdev->stats.stag.max)
280 rdev->stats.stag.max = rdev->stats.stag.cur;
281 mutex_unlock(&rdev->stats.lock);
282 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff);
283 }
284 PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
285 __func__, stag_state, type, pdid, stag_idx);
286
287
288 if (reset_tpt_entry)
289 memset(&tpt, 0, sizeof(tpt));
290 else {
291 tpt.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
292 FW_RI_TPTE_STAGKEY_V((*stag & FW_RI_TPTE_STAGKEY_M)) |
293 FW_RI_TPTE_STAGSTATE_V(stag_state) |
294 FW_RI_TPTE_STAGTYPE_V(type) | FW_RI_TPTE_PDID_V(pdid));
295 tpt.locread_to_qpid = cpu_to_be32(FW_RI_TPTE_PERM_V(perm) |
296 (bind_enabled ? FW_RI_TPTE_MWBINDEN_F : 0) |
297 FW_RI_TPTE_ADDRTYPE_V((zbva ? FW_RI_ZERO_BASED_TO :
298 FW_RI_VA_BASED_TO))|
299 FW_RI_TPTE_PS_V(page_size));
300 tpt.nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32(
301 FW_RI_TPTE_PBLADDR_V(PBL_OFF(rdev, pbl_addr)>>3));
302 tpt.len_lo = cpu_to_be32((u32)(len & 0xffffffffUL));
303 tpt.va_hi = cpu_to_be32((u32)(to >> 32));
304 tpt.va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL));
305 tpt.dca_mwbcnt_pstag = cpu_to_be32(0);
306 tpt.len_hi = cpu_to_be32((u32)(len >> 32));
307 }
308 err = write_adapter_mem(rdev, stag_idx +
309 (rdev->lldi.vr->stag.start >> 5),
310 sizeof(tpt), &tpt);
311
312 if (reset_tpt_entry) {
313 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx);
314 mutex_lock(&rdev->stats.lock);
315 rdev->stats.stag.cur -= 32;
316 mutex_unlock(&rdev->stats.lock);
317 }
318 return err;
319}
320
321static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl,
322 u32 pbl_addr, u32 pbl_size)
323{
324 int err;
325
326 PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
327 __func__, pbl_addr, rdev->lldi.vr->pbl.start,
328 pbl_size);
329
330 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl);
331 return err;
332}
333
334static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size,
335 u32 pbl_addr)
336{
337 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0,
338 pbl_size, pbl_addr);
339}
340
341static int allocate_window(struct c4iw_rdev *rdev, u32 * stag, u32 pdid)
342{
343 *stag = T4_STAG_UNSET;
344 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0,
345 0UL, 0, 0, 0, 0);
346}
347
348static int deallocate_window(struct c4iw_rdev *rdev, u32 stag)
349{
350 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0,
351 0);
352}
353
354static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
355 u32 pbl_size, u32 pbl_addr)
356{
357 *stag = T4_STAG_UNSET;
358 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0,
359 0UL, 0, 0, pbl_size, pbl_addr);
360}
361
362static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag)
363{
364 u32 mmid;
365
366 mhp->attr.state = 1;
367 mhp->attr.stag = stag;
368 mmid = stag >> 8;
369 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
370 PDBG("%s mmid 0x%x mhp %p\n", __func__, mmid, mhp);
371 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid);
372}
373
374static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
375 struct c4iw_mr *mhp, int shift)
376{
377 u32 stag = T4_STAG_UNSET;
378 int ret;
379
380 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid,
381 FW_RI_STAG_NSMR, mhp->attr.len ?
382 mhp->attr.perms : 0,
383 mhp->attr.mw_bind_enable, mhp->attr.zbva,
384 mhp->attr.va_fbo, mhp->attr.len ?
385 mhp->attr.len : -1, shift - 12,
386 mhp->attr.pbl_size, mhp->attr.pbl_addr);
387 if (ret)
388 return ret;
389
390 ret = finish_mem_reg(mhp, stag);
391 if (ret)
392 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
393 mhp->attr.pbl_addr);
394 return ret;
395}
396
397static int alloc_pbl(struct c4iw_mr *mhp, int npages)
398{
399 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev,
400 npages << 3);
401
402 if (!mhp->attr.pbl_addr)
403 return -ENOMEM;
404
405 mhp->attr.pbl_size = npages;
406
407 return 0;
408}
409
410struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc)
411{
412 struct c4iw_dev *rhp;
413 struct c4iw_pd *php;
414 struct c4iw_mr *mhp;
415 int ret;
416 u32 stag = T4_STAG_UNSET;
417
418 PDBG("%s ib_pd %p\n", __func__, pd);
419 php = to_c4iw_pd(pd);
420 rhp = php->rhp;
421
422 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
423 if (!mhp)
424 return ERR_PTR(-ENOMEM);
425
426 mhp->rhp = rhp;
427 mhp->attr.pdid = php->pdid;
428 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
429 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND;
430 mhp->attr.zbva = 0;
431 mhp->attr.va_fbo = 0;
432 mhp->attr.page_size = 0;
433 mhp->attr.len = ~0ULL;
434 mhp->attr.pbl_size = 0;
435
436 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid,
437 FW_RI_STAG_NSMR, mhp->attr.perms,
438 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0);
439 if (ret)
440 goto err1;
441
442 ret = finish_mem_reg(mhp, stag);
443 if (ret)
444 goto err2;
445 return &mhp->ibmr;
446err2:
447 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
448 mhp->attr.pbl_addr);
449err1:
450 kfree(mhp);
451 return ERR_PTR(ret);
452}
453
454struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
455 u64 virt, int acc, struct ib_udata *udata)
456{
457 __be64 *pages;
458 int shift, n, len;
459 int i, k, entry;
460 int err = 0;
461 struct scatterlist *sg;
462 struct c4iw_dev *rhp;
463 struct c4iw_pd *php;
464 struct c4iw_mr *mhp;
465
466 PDBG("%s ib_pd %p\n", __func__, pd);
467
468 if (length == ~0ULL)
469 return ERR_PTR(-EINVAL);
470
471 if ((length + start) < start)
472 return ERR_PTR(-EINVAL);
473
474 php = to_c4iw_pd(pd);
475 rhp = php->rhp;
476
477 if (mr_exceeds_hw_limits(rhp, length))
478 return ERR_PTR(-EINVAL);
479
480 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
481 if (!mhp)
482 return ERR_PTR(-ENOMEM);
483
484 mhp->rhp = rhp;
485
486 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0);
487 if (IS_ERR(mhp->umem)) {
488 err = PTR_ERR(mhp->umem);
489 kfree(mhp);
490 return ERR_PTR(err);
491 }
492
493 shift = ffs(mhp->umem->page_size) - 1;
494
495 n = mhp->umem->nmap;
496 err = alloc_pbl(mhp, n);
497 if (err)
498 goto err;
499
500 pages = (__be64 *) __get_free_page(GFP_KERNEL);
501 if (!pages) {
502 err = -ENOMEM;
503 goto err_pbl;
504 }
505
506 i = n = 0;
507
508 for_each_sg(mhp->umem->sg_head.sgl, sg, mhp->umem->nmap, entry) {
509 len = sg_dma_len(sg) >> shift;
510 for (k = 0; k < len; ++k) {
511 pages[i++] = cpu_to_be64(sg_dma_address(sg) +
512 mhp->umem->page_size * k);
513 if (i == PAGE_SIZE / sizeof *pages) {
514 err = write_pbl(&mhp->rhp->rdev,
515 pages,
516 mhp->attr.pbl_addr + (n << 3), i);
517 if (err)
518 goto pbl_done;
519 n += i;
520 i = 0;
521 }
522 }
523 }
524
525 if (i)
526 err = write_pbl(&mhp->rhp->rdev, pages,
527 mhp->attr.pbl_addr + (n << 3), i);
528
529pbl_done:
530 free_page((unsigned long) pages);
531 if (err)
532 goto err_pbl;
533
534 mhp->attr.pdid = php->pdid;
535 mhp->attr.zbva = 0;
536 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
537 mhp->attr.va_fbo = virt;
538 mhp->attr.page_size = shift - 12;
539 mhp->attr.len = length;
540
541 err = register_mem(rhp, php, mhp, shift);
542 if (err)
543 goto err_pbl;
544
545 return &mhp->ibmr;
546
547err_pbl:
548 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
549 mhp->attr.pbl_size << 3);
550
551err:
552 ib_umem_release(mhp->umem);
553 kfree(mhp);
554 return ERR_PTR(err);
555}
556
557struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
558 struct ib_udata *udata)
559{
560 struct c4iw_dev *rhp;
561 struct c4iw_pd *php;
562 struct c4iw_mw *mhp;
563 u32 mmid;
564 u32 stag = 0;
565 int ret;
566
567 if (type != IB_MW_TYPE_1)
568 return ERR_PTR(-EINVAL);
569
570 php = to_c4iw_pd(pd);
571 rhp = php->rhp;
572 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
573 if (!mhp)
574 return ERR_PTR(-ENOMEM);
575 ret = allocate_window(&rhp->rdev, &stag, php->pdid);
576 if (ret) {
577 kfree(mhp);
578 return ERR_PTR(ret);
579 }
580 mhp->rhp = rhp;
581 mhp->attr.pdid = php->pdid;
582 mhp->attr.type = FW_RI_STAG_MW;
583 mhp->attr.stag = stag;
584 mmid = (stag) >> 8;
585 mhp->ibmw.rkey = stag;
586 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
587 deallocate_window(&rhp->rdev, mhp->attr.stag);
588 kfree(mhp);
589 return ERR_PTR(-ENOMEM);
590 }
591 PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag);
592 return &(mhp->ibmw);
593}
594
595int c4iw_dealloc_mw(struct ib_mw *mw)
596{
597 struct c4iw_dev *rhp;
598 struct c4iw_mw *mhp;
599 u32 mmid;
600
601 mhp = to_c4iw_mw(mw);
602 rhp = mhp->rhp;
603 mmid = (mw->rkey) >> 8;
604 remove_handle(rhp, &rhp->mmidr, mmid);
605 deallocate_window(&rhp->rdev, mhp->attr.stag);
606 kfree(mhp);
607 PDBG("%s ib_mw %p mmid 0x%x ptr %p\n", __func__, mw, mmid, mhp);
608 return 0;
609}
610
611struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
612 enum ib_mr_type mr_type,
613 u32 max_num_sg)
614{
615 struct c4iw_dev *rhp;
616 struct c4iw_pd *php;
617 struct c4iw_mr *mhp;
618 u32 mmid;
619 u32 stag = 0;
620 int ret = 0;
621 int length = roundup(max_num_sg * sizeof(u64), 32);
622
623 php = to_c4iw_pd(pd);
624 rhp = php->rhp;
625
626 if (mr_type != IB_MR_TYPE_MEM_REG ||
627 max_num_sg > t4_max_fr_depth(&rhp->rdev.lldi.ulptx_memwrite_dsgl &&
628 use_dsgl))
629 return ERR_PTR(-EINVAL);
630
631 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
632 if (!mhp) {
633 ret = -ENOMEM;
634 goto err;
635 }
636
637 mhp->mpl = dma_alloc_coherent(&rhp->rdev.lldi.pdev->dev,
638 length, &mhp->mpl_addr, GFP_KERNEL);
639 if (!mhp->mpl) {
640 ret = -ENOMEM;
641 goto err_mpl;
642 }
643 mhp->max_mpl_len = length;
644
645 mhp->rhp = rhp;
646 ret = alloc_pbl(mhp, max_num_sg);
647 if (ret)
648 goto err1;
649 mhp->attr.pbl_size = max_num_sg;
650 ret = allocate_stag(&rhp->rdev, &stag, php->pdid,
651 mhp->attr.pbl_size, mhp->attr.pbl_addr);
652 if (ret)
653 goto err2;
654 mhp->attr.pdid = php->pdid;
655 mhp->attr.type = FW_RI_STAG_NSMR;
656 mhp->attr.stag = stag;
657 mhp->attr.state = 1;
658 mmid = (stag) >> 8;
659 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
660 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
661 ret = -ENOMEM;
662 goto err3;
663 }
664
665 PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag);
666 return &(mhp->ibmr);
667err3:
668 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size,
669 mhp->attr.pbl_addr);
670err2:
671 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
672 mhp->attr.pbl_size << 3);
673err1:
674 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
675 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
676err_mpl:
677 kfree(mhp);
678err:
679 return ERR_PTR(ret);
680}
681
682static int c4iw_set_page(struct ib_mr *ibmr, u64 addr)
683{
684 struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
685
686 if (unlikely(mhp->mpl_len == mhp->max_mpl_len))
687 return -ENOMEM;
688
689 mhp->mpl[mhp->mpl_len++] = addr;
690
691 return 0;
692}
693
694int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
695 unsigned int *sg_offset)
696{
697 struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
698
699 mhp->mpl_len = 0;
700
701 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, c4iw_set_page);
702}
703
704int c4iw_dereg_mr(struct ib_mr *ib_mr)
705{
706 struct c4iw_dev *rhp;
707 struct c4iw_mr *mhp;
708 u32 mmid;
709
710 PDBG("%s ib_mr %p\n", __func__, ib_mr);
711
712 mhp = to_c4iw_mr(ib_mr);
713 rhp = mhp->rhp;
714 mmid = mhp->attr.stag >> 8;
715 remove_handle(rhp, &rhp->mmidr, mmid);
716 if (mhp->mpl)
717 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
718 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
719 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
720 mhp->attr.pbl_addr);
721 if (mhp->attr.pbl_size)
722 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
723 mhp->attr.pbl_size << 3);
724 if (mhp->kva)
725 kfree((void *) (unsigned long) mhp->kva);
726 if (mhp->umem)
727 ib_umem_release(mhp->umem);
728 PDBG("%s mmid 0x%x ptr %p\n", __func__, mmid, mhp);
729 kfree(mhp);
730 return 0;
731}
732
