linux/drivers/media/pci/solo6x10/solo6x10-enc.c
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   1/*
   2 * Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
   3 *
   4 * Original author:
   5 * Ben Collins <bcollins@ubuntu.com>
   6 *
   7 * Additional work by:
   8 * John Brooks <john.brooks@bluecherry.net>
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License as published by
  12 * the Free Software Foundation; either version 2 of the License, or
  13 * (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 */
  20
  21#include <linux/kernel.h>
  22#include <linux/font.h>
  23#include <linux/bitrev.h>
  24#include <linux/slab.h>
  25
  26#include "solo6x10.h"
  27
  28#define VI_PROG_HSIZE                   (1280 - 16)
  29#define VI_PROG_VSIZE                   (1024 - 16)
  30
  31#define IRQ_LEVEL                       2
  32
  33static void solo_capture_config(struct solo_dev *solo_dev)
  34{
  35        unsigned long height;
  36        unsigned long width;
  37        void *buf;
  38        int i;
  39
  40        solo_reg_write(solo_dev, SOLO_CAP_BASE,
  41                       SOLO_CAP_MAX_PAGE((SOLO_CAP_EXT_SIZE(solo_dev)
  42                                          - SOLO_CAP_PAGE_SIZE) >> 16)
  43                       | SOLO_CAP_BASE_ADDR(SOLO_CAP_EXT_ADDR(solo_dev) >> 16));
  44
  45        /* XXX: Undocumented bits at b17 and b24 */
  46        if (solo_dev->type == SOLO_DEV_6110) {
  47                /* NOTE: Ref driver has (62 << 24) here as well, but it causes
  48                 * wacked out frame timing on 4-port 6110. */
  49                solo_reg_write(solo_dev, SOLO_CAP_BTW,
  50                               (1 << 17) | SOLO_CAP_PROG_BANDWIDTH(2) |
  51                               SOLO_CAP_MAX_BANDWIDTH(36));
  52        } else {
  53                solo_reg_write(solo_dev, SOLO_CAP_BTW,
  54                               (1 << 17) | SOLO_CAP_PROG_BANDWIDTH(2) |
  55                               SOLO_CAP_MAX_BANDWIDTH(32));
  56        }
  57
  58        /* Set scale 1, 9 dimension */
  59        width = solo_dev->video_hsize;
  60        height = solo_dev->video_vsize;
  61        solo_reg_write(solo_dev, SOLO_DIM_SCALE1,
  62                       SOLO_DIM_H_MB_NUM(width / 16) |
  63                       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
  64                       SOLO_DIM_V_MB_NUM_FIELD(height / 16));
  65
  66        /* Set scale 2, 10 dimension */
  67        width = solo_dev->video_hsize / 2;
  68        height = solo_dev->video_vsize;
  69        solo_reg_write(solo_dev, SOLO_DIM_SCALE2,
  70                       SOLO_DIM_H_MB_NUM(width / 16) |
  71                       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
  72                       SOLO_DIM_V_MB_NUM_FIELD(height / 16));
  73
  74        /* Set scale 3, 11 dimension */
  75        width = solo_dev->video_hsize / 2;
  76        height = solo_dev->video_vsize / 2;
  77        solo_reg_write(solo_dev, SOLO_DIM_SCALE3,
  78                       SOLO_DIM_H_MB_NUM(width / 16) |
  79                       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
  80                       SOLO_DIM_V_MB_NUM_FIELD(height / 16));
  81
  82        /* Set scale 4, 12 dimension */
  83        width = solo_dev->video_hsize / 3;
  84        height = solo_dev->video_vsize / 3;
  85        solo_reg_write(solo_dev, SOLO_DIM_SCALE4,
  86                       SOLO_DIM_H_MB_NUM(width / 16) |
  87                       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
  88                       SOLO_DIM_V_MB_NUM_FIELD(height / 16));
  89
  90        /* Set scale 5, 13 dimension */
  91        width = solo_dev->video_hsize / 4;
  92        height = solo_dev->video_vsize / 2;
  93        solo_reg_write(solo_dev, SOLO_DIM_SCALE5,
  94                       SOLO_DIM_H_MB_NUM(width / 16) |
  95                       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
  96                       SOLO_DIM_V_MB_NUM_FIELD(height / 16));
  97
  98        /* Progressive */
  99        width = VI_PROG_HSIZE;
 100        height = VI_PROG_VSIZE;
 101        solo_reg_write(solo_dev, SOLO_DIM_PROG,
 102                       SOLO_DIM_H_MB_NUM(width / 16) |
 103                       SOLO_DIM_V_MB_NUM_FRAME(height / 16) |
 104                       SOLO_DIM_V_MB_NUM_FIELD(height / 16));
 105
 106        /* Clear OSD */
 107        solo_reg_write(solo_dev, SOLO_VE_OSD_CH, 0);
 108        solo_reg_write(solo_dev, SOLO_VE_OSD_BASE, SOLO_EOSD_EXT_ADDR >> 16);
 109        solo_reg_write(solo_dev, SOLO_VE_OSD_CLR,
 110                       0xF0 << 16 | 0x80 << 8 | 0x80);
 111
 112        if (solo_dev->type == SOLO_DEV_6010)
 113                solo_reg_write(solo_dev, SOLO_VE_OSD_OPT,
 114                               SOLO_VE_OSD_H_SHADOW | SOLO_VE_OSD_V_SHADOW);
 115        else
 116                solo_reg_write(solo_dev, SOLO_VE_OSD_OPT, SOLO_VE_OSD_V_DOUBLE
 117                               | SOLO_VE_OSD_H_SHADOW | SOLO_VE_OSD_V_SHADOW);
 118
 119        /* Clear OSG buffer */
 120        buf = kzalloc(SOLO_EOSD_EXT_SIZE(solo_dev), GFP_KERNEL);
 121        if (!buf)
 122                return;
 123
 124        for (i = 0; i < solo_dev->nr_chans; i++) {
 125                solo_p2m_dma(solo_dev, 1, buf,
 126                             SOLO_EOSD_EXT_ADDR +
 127                             (SOLO_EOSD_EXT_SIZE(solo_dev) * i),
 128                             SOLO_EOSD_EXT_SIZE(solo_dev), 0, 0);
 129        }
 130        kfree(buf);
 131}
 132
 133#define SOLO_OSD_WRITE_SIZE (16 * OSD_TEXT_MAX)
 134
 135/* Should be called with enable_lock held */
 136int solo_osd_print(struct solo_enc_dev *solo_enc)
 137{
 138        struct solo_dev *solo_dev = solo_enc->solo_dev;
 139        u8 *str = solo_enc->osd_text;
 140        u8 *buf = solo_enc->osd_buf;
 141        u32 reg;
 142        const struct font_desc *vga = find_font("VGA8x16");
 143        const u8 *vga_data;
 144        int i, j;
 145
 146        if (WARN_ON_ONCE(!vga))
 147                return -ENODEV;
 148
 149        reg = solo_reg_read(solo_dev, SOLO_VE_OSD_CH);
 150        if (!*str) {
 151                /* Disable OSD on this channel */
 152                reg &= ~(1 << solo_enc->ch);
 153                goto out;
 154        }
 155
 156        memset(buf, 0, SOLO_OSD_WRITE_SIZE);
 157        vga_data = (const u8 *)vga->data;
 158
 159        for (i = 0; *str; i++, str++) {
 160                for (j = 0; j < 16; j++) {
 161                        buf[(j << 1) | (i & 1) | ((i & ~1) << 4)] =
 162                            bitrev8(vga_data[(*str << 4) | j]);
 163                }
 164        }
 165
 166        solo_p2m_dma(solo_dev, 1, buf,
 167                     SOLO_EOSD_EXT_ADDR_CHAN(solo_dev, solo_enc->ch),
 168                     SOLO_OSD_WRITE_SIZE, 0, 0);
 169
 170        /* Enable OSD on this channel */
 171        reg |= (1 << solo_enc->ch);
 172
 173out:
 174        solo_reg_write(solo_dev, SOLO_VE_OSD_CH, reg);
 175        return 0;
 176}
 177
 178/**
 179 * Set channel Quality Profile (0-3).
 180 */
 181void solo_s_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch,
 182                    unsigned int qp)
 183{
 184        unsigned long flags;
 185        unsigned int idx, reg;
 186
 187        if ((ch > 31) || (qp > 3))
 188                return;
 189
 190        if (solo_dev->type == SOLO_DEV_6010)
 191                return;
 192
 193        if (ch < 16) {
 194                idx = 0;
 195                reg = SOLO_VE_JPEG_QP_CH_L;
 196        } else {
 197                ch -= 16;
 198                idx = 1;
 199                reg = SOLO_VE_JPEG_QP_CH_H;
 200        }
 201        ch *= 2;
 202
 203        spin_lock_irqsave(&solo_dev->jpeg_qp_lock, flags);
 204
 205        solo_dev->jpeg_qp[idx] &= ~(3 << ch);
 206        solo_dev->jpeg_qp[idx] |= (qp & 3) << ch;
 207
 208        solo_reg_write(solo_dev, reg, solo_dev->jpeg_qp[idx]);
 209
 210        spin_unlock_irqrestore(&solo_dev->jpeg_qp_lock, flags);
 211}
 212
 213int solo_g_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch)
 214{
 215        int idx;
 216
 217        if (solo_dev->type == SOLO_DEV_6010)
 218                return 2;
 219
 220        if (WARN_ON_ONCE(ch > 31))
 221                return 2;
 222
 223        if (ch < 16) {
 224                idx = 0;
 225        } else {
 226                ch -= 16;
 227                idx = 1;
 228        }
 229        ch *= 2;
 230
 231        return (solo_dev->jpeg_qp[idx] >> ch) & 3;
 232}
 233
 234#define SOLO_QP_INIT 0xaaaaaaaa
 235
 236static void solo_jpeg_config(struct solo_dev *solo_dev)
 237{
 238        if (solo_dev->type == SOLO_DEV_6010) {
 239                solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_TBL,
 240                               (2 << 24) | (2 << 16) | (2 << 8) | 2);
 241        } else {
 242                solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_TBL,
 243                               (4 << 24) | (3 << 16) | (2 << 8) | 1);
 244        }
 245
 246        spin_lock_init(&solo_dev->jpeg_qp_lock);
 247
 248        /* Initialize Quality Profile for all channels */
 249        solo_dev->jpeg_qp[0] = solo_dev->jpeg_qp[1] = SOLO_QP_INIT;
 250        solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_CH_L, SOLO_QP_INIT);
 251        solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_CH_H, SOLO_QP_INIT);
 252
 253        solo_reg_write(solo_dev, SOLO_VE_JPEG_CFG,
 254                (SOLO_JPEG_EXT_SIZE(solo_dev) & 0xffff0000) |
 255                ((SOLO_JPEG_EXT_ADDR(solo_dev) >> 16) & 0x0000ffff));
 256        solo_reg_write(solo_dev, SOLO_VE_JPEG_CTRL, 0xffffffff);
 257        if (solo_dev->type == SOLO_DEV_6110) {
 258                solo_reg_write(solo_dev, SOLO_VE_JPEG_CFG1,
 259                               (0 << 16) | (30 << 8) | 60);
 260        }
 261}
 262
 263static void solo_mp4e_config(struct solo_dev *solo_dev)
 264{
 265        int i;
 266        u32 cfg;
 267
 268        solo_reg_write(solo_dev, SOLO_VE_CFG0,
 269                       SOLO_VE_INTR_CTRL(IRQ_LEVEL) |
 270                       SOLO_VE_BLOCK_SIZE(SOLO_MP4E_EXT_SIZE(solo_dev) >> 16) |
 271                       SOLO_VE_BLOCK_BASE(SOLO_MP4E_EXT_ADDR(solo_dev) >> 16));
 272
 273
 274        cfg = SOLO_VE_BYTE_ALIGN(2) | SOLO_VE_INSERT_INDEX
 275                | SOLO_VE_MOTION_MODE(0);
 276        if (solo_dev->type != SOLO_DEV_6010) {
 277                cfg |= SOLO_VE_MPEG_SIZE_H(
 278                        (SOLO_MP4E_EXT_SIZE(solo_dev) >> 24) & 0x0f);
 279                cfg |= SOLO_VE_JPEG_SIZE_H(
 280                        (SOLO_JPEG_EXT_SIZE(solo_dev) >> 24) & 0x0f);
 281        }
 282        solo_reg_write(solo_dev, SOLO_VE_CFG1, cfg);
 283
 284        solo_reg_write(solo_dev, SOLO_VE_WMRK_POLY, 0);
 285        solo_reg_write(solo_dev, SOLO_VE_VMRK_INIT_KEY, 0);
 286        solo_reg_write(solo_dev, SOLO_VE_WMRK_STRL, 0);
 287        if (solo_dev->type == SOLO_DEV_6110)
 288                solo_reg_write(solo_dev, SOLO_VE_WMRK_ENABLE, 0);
 289        solo_reg_write(solo_dev, SOLO_VE_ENCRYP_POLY, 0);
 290        solo_reg_write(solo_dev, SOLO_VE_ENCRYP_INIT, 0);
 291
 292        solo_reg_write(solo_dev, SOLO_VE_ATTR,
 293                       SOLO_VE_LITTLE_ENDIAN |
 294                       SOLO_COMP_ATTR_FCODE(1) |
 295                       SOLO_COMP_TIME_INC(0) |
 296                       SOLO_COMP_TIME_WIDTH(15) |
 297                       SOLO_DCT_INTERVAL(solo_dev->type == SOLO_DEV_6010 ? 9 : 10));
 298
 299        for (i = 0; i < solo_dev->nr_chans; i++) {
 300                solo_reg_write(solo_dev, SOLO_VE_CH_REF_BASE(i),
 301                               (SOLO_EREF_EXT_ADDR(solo_dev) +
 302                               (i * SOLO_EREF_EXT_SIZE)) >> 16);
 303                solo_reg_write(solo_dev, SOLO_VE_CH_REF_BASE_E(i),
 304                               (SOLO_EREF_EXT_ADDR(solo_dev) +
 305                               ((i + 16) * SOLO_EREF_EXT_SIZE)) >> 16);
 306        }
 307
 308        if (solo_dev->type == SOLO_DEV_6110) {
 309                solo_reg_write(solo_dev, SOLO_VE_COMPT_MOT, 0x00040008);
 310        } else {
 311                for (i = 0; i < solo_dev->nr_chans; i++)
 312                        solo_reg_write(solo_dev, SOLO_VE_CH_MOT(i), 0x100);
 313        }
 314}
 315
 316int solo_enc_init(struct solo_dev *solo_dev)
 317{
 318        int i;
 319
 320        solo_capture_config(solo_dev);
 321        solo_mp4e_config(solo_dev);
 322        solo_jpeg_config(solo_dev);
 323
 324        for (i = 0; i < solo_dev->nr_chans; i++) {
 325                solo_reg_write(solo_dev, SOLO_CAP_CH_SCALE(i), 0);
 326                solo_reg_write(solo_dev, SOLO_CAP_CH_COMP_ENA_E(i), 0);
 327        }
 328
 329        return 0;
 330}
 331
 332void solo_enc_exit(struct solo_dev *solo_dev)
 333{
 334        int i;
 335
 336        for (i = 0; i < solo_dev->nr_chans; i++) {
 337                solo_reg_write(solo_dev, SOLO_CAP_CH_SCALE(i), 0);
 338                solo_reg_write(solo_dev, SOLO_CAP_CH_COMP_ENA_E(i), 0);
 339        }
 340}
 341