1/* 2 * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10#define MMCIPOWER 0x000 11#define MCI_PWR_OFF 0x00 12#define MCI_PWR_UP 0x02 13#define MCI_PWR_ON 0x03 14#define MCI_OD (1 << 6) 15#define MCI_ROD (1 << 7) 16/* 17 * The ST Micro version does not have ROD and reuse the voltage registers for 18 * direction settings. 19 */ 20#define MCI_ST_DATA2DIREN (1 << 2) 21#define MCI_ST_CMDDIREN (1 << 3) 22#define MCI_ST_DATA0DIREN (1 << 4) 23#define MCI_ST_DATA31DIREN (1 << 5) 24#define MCI_ST_FBCLKEN (1 << 7) 25#define MCI_ST_DATA74DIREN (1 << 8) 26 27#define MMCICLOCK 0x004 28#define MCI_CLK_ENABLE (1 << 8) 29#define MCI_CLK_PWRSAVE (1 << 9) 30#define MCI_CLK_BYPASS (1 << 10) 31#define MCI_4BIT_BUS (1 << 11) 32/* 33 * 8bit wide buses, hardware flow contronl, negative edges and clock inversion 34 * supported in ST Micro U300 and Ux500 versions 35 */ 36#define MCI_ST_8BIT_BUS (1 << 12) 37#define MCI_ST_U300_HWFCEN (1 << 13) 38#define MCI_ST_UX500_NEG_EDGE (1 << 13) 39#define MCI_ST_UX500_HWFCEN (1 << 14) 40#define MCI_ST_UX500_CLK_INV (1 << 15) 41/* Modified PL180 on Versatile Express platform */ 42#define MCI_ARM_HWFCEN (1 << 12) 43 44/* Modified on Qualcomm Integrations */ 45#define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11)) 46#define MCI_QCOM_CLK_FLOWENA BIT(12) 47#define MCI_QCOM_CLK_INVERTOUT BIT(13) 48 49/* select in latch data and command in */ 50#define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15) 51#define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15)) 52 53#define MMCIARGUMENT 0x008 54#define MMCICOMMAND 0x00c 55#define MCI_CPSM_RESPONSE (1 << 6) 56#define MCI_CPSM_LONGRSP (1 << 7) 57#define MCI_CPSM_INTERRUPT (1 << 8) 58#define MCI_CPSM_PENDING (1 << 9) 59#define MCI_CPSM_ENABLE (1 << 10) 60/* Argument flag extenstions in the ST Micro versions */ 61#define MCI_ST_SDIO_SUSP (1 << 11) 62#define MCI_ST_ENCMD_COMPL (1 << 12) 63#define MCI_ST_NIEN (1 << 13) 64#define MCI_ST_CE_ATACMD (1 << 14) 65 66/* Modified on Qualcomm Integrations */ 67#define MCI_QCOM_CSPM_DATCMD BIT(12) 68#define MCI_QCOM_CSPM_MCIABORT BIT(13) 69#define MCI_QCOM_CSPM_CCSENABLE BIT(14) 70#define MCI_QCOM_CSPM_CCSDISABLE BIT(15) 71#define MCI_QCOM_CSPM_AUTO_CMD19 BIT(16) 72#define MCI_QCOM_CSPM_AUTO_CMD21 BIT(21) 73 74#define MMCIRESPCMD 0x010 75#define MMCIRESPONSE0 0x014 76#define MMCIRESPONSE1 0x018 77#define MMCIRESPONSE2 0x01c 78#define MMCIRESPONSE3 0x020 79#define MMCIDATATIMER 0x024 80#define MMCIDATALENGTH 0x028 81#define MMCIDATACTRL 0x02c 82#define MCI_DPSM_ENABLE (1 << 0) 83#define MCI_DPSM_DIRECTION (1 << 1) 84#define MCI_DPSM_MODE (1 << 2) 85#define MCI_DPSM_DMAENABLE (1 << 3) 86#define MCI_DPSM_BLOCKSIZE (1 << 4) 87/* Control register extensions in the ST Micro U300 and Ux500 versions */ 88#define MCI_ST_DPSM_RWSTART (1 << 8) 89#define MCI_ST_DPSM_RWSTOP (1 << 9) 90#define MCI_ST_DPSM_RWMOD (1 << 10) 91#define MCI_ST_DPSM_SDIOEN (1 << 11) 92/* Control register extensions in the ST Micro Ux500 versions */ 93#define MCI_ST_DPSM_DMAREQCTL (1 << 12) 94#define MCI_ST_DPSM_DBOOTMODEEN (1 << 13) 95#define MCI_ST_DPSM_BUSYMODE (1 << 14) 96#define MCI_ST_DPSM_DDRMODE (1 << 15) 97 98#define MMCIDATACNT 0x030 99#define MMCISTATUS 0x034 100#define MCI_CMDCRCFAIL (1 << 0) 101#define MCI_DATACRCFAIL (1 << 1) 102#define MCI_CMDTIMEOUT (1 << 2) 103#define MCI_DATATIMEOUT (1 << 3) 104#define MCI_TXUNDERRUN (1 << 4) 105#define MCI_RXOVERRUN (1 << 5) 106#define MCI_CMDRESPEND (1 << 6) 107#define MCI_CMDSENT (1 << 7) 108#define MCI_DATAEND (1 << 8) 109#define MCI_STARTBITERR (1 << 9) 110#define MCI_DATABLOCKEND (1 << 10) 111#define MCI_CMDACTIVE (1 << 11) 112#define MCI_TXACTIVE (1 << 12) 113#define MCI_RXACTIVE (1 << 13) 114#define MCI_TXFIFOHALFEMPTY (1 << 14) 115#define MCI_RXFIFOHALFFULL (1 << 15) 116#define MCI_TXFIFOFULL (1 << 16) 117#define MCI_RXFIFOFULL (1 << 17) 118#define MCI_TXFIFOEMPTY (1 << 18) 119#define MCI_RXFIFOEMPTY (1 << 19) 120#define MCI_TXDATAAVLBL (1 << 20) 121#define MCI_RXDATAAVLBL (1 << 21) 122/* Extended status bits for the ST Micro variants */ 123#define MCI_ST_SDIOIT (1 << 22) 124#define MCI_ST_CEATAEND (1 << 23) 125#define MCI_ST_CARDBUSY (1 << 24) 126 127#define MMCICLEAR 0x038 128#define MCI_CMDCRCFAILCLR (1 << 0) 129#define MCI_DATACRCFAILCLR (1 << 1) 130#define MCI_CMDTIMEOUTCLR (1 << 2) 131#define MCI_DATATIMEOUTCLR (1 << 3) 132#define MCI_TXUNDERRUNCLR (1 << 4) 133#define MCI_RXOVERRUNCLR (1 << 5) 134#define MCI_CMDRESPENDCLR (1 << 6) 135#define MCI_CMDSENTCLR (1 << 7) 136#define MCI_DATAENDCLR (1 << 8) 137#define MCI_STARTBITERRCLR (1 << 9) 138#define MCI_DATABLOCKENDCLR (1 << 10) 139/* Extended status bits for the ST Micro variants */ 140#define MCI_ST_SDIOITC (1 << 22) 141#define MCI_ST_CEATAENDC (1 << 23) 142#define MCI_ST_BUSYENDC (1 << 24) 143 144#define MMCIMASK0 0x03c 145#define MCI_CMDCRCFAILMASK (1 << 0) 146#define MCI_DATACRCFAILMASK (1 << 1) 147#define MCI_CMDTIMEOUTMASK (1 << 2) 148#define MCI_DATATIMEOUTMASK (1 << 3) 149#define MCI_TXUNDERRUNMASK (1 << 4) 150#define MCI_RXOVERRUNMASK (1 << 5) 151#define MCI_CMDRESPENDMASK (1 << 6) 152#define MCI_CMDSENTMASK (1 << 7) 153#define MCI_DATAENDMASK (1 << 8) 154#define MCI_STARTBITERRMASK (1 << 9) 155#define MCI_DATABLOCKENDMASK (1 << 10) 156#define MCI_CMDACTIVEMASK (1 << 11) 157#define MCI_TXACTIVEMASK (1 << 12) 158#define MCI_RXACTIVEMASK (1 << 13) 159#define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 160#define MCI_RXFIFOHALFFULLMASK (1 << 15) 161#define MCI_TXFIFOFULLMASK (1 << 16) 162#define MCI_RXFIFOFULLMASK (1 << 17) 163#define MCI_TXFIFOEMPTYMASK (1 << 18) 164#define MCI_RXFIFOEMPTYMASK (1 << 19) 165#define MCI_TXDATAAVLBLMASK (1 << 20) 166#define MCI_RXDATAAVLBLMASK (1 << 21) 167/* Extended status bits for the ST Micro variants */ 168#define MCI_ST_SDIOITMASK (1 << 22) 169#define MCI_ST_CEATAENDMASK (1 << 23) 170#define MCI_ST_BUSYEND (1 << 24) 171 172#define MMCIMASK1 0x040 173#define MMCIFIFOCNT 0x048 174#define MMCIFIFO 0x080 /* to 0x0bc */ 175 176#define MCI_IRQENABLE \ 177 (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ 178 MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ 179 MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK) 180 181/* These interrupts are directed to IRQ1 when two IRQ lines are available */ 182#define MCI_IRQ1MASK \ 183 (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ 184 MCI_TXFIFOHALFEMPTYMASK) 185 186#define NR_SG 128 187 188struct clk; 189struct variant_data; 190struct dma_chan; 191 192struct mmci_host_next { 193 struct dma_async_tx_descriptor *dma_desc; 194 struct dma_chan *dma_chan; 195 s32 cookie; 196}; 197 198struct mmci_host { 199 phys_addr_t phybase; 200 void __iomem *base; 201 struct mmc_request *mrq; 202 struct mmc_command *cmd; 203 struct mmc_data *data; 204 struct mmc_host *mmc; 205 struct clk *clk; 206 bool singleirq; 207 208 spinlock_t lock; 209 210 unsigned int mclk; 211 /* cached value of requested clk in set_ios */ 212 unsigned int clock_cache; 213 unsigned int cclk; 214 u32 pwr_reg; 215 u32 pwr_reg_add; 216 u32 clk_reg; 217 u32 datactrl_reg; 218 u32 busy_status; 219 bool vqmmc_enabled; 220 struct mmci_platform_data *plat; 221 struct variant_data *variant; 222 223 u8 hw_designer; 224 u8 hw_revision:4; 225 226 struct timer_list timer; 227 unsigned int oldstat; 228 229 /* pio stuff */ 230 struct sg_mapping_iter sg_miter; 231 unsigned int size; 232 int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain); 233 234#ifdef CONFIG_DMA_ENGINE 235 /* DMA stuff */ 236 struct dma_chan *dma_current; 237 struct dma_chan *dma_rx_channel; 238 struct dma_chan *dma_tx_channel; 239 struct dma_async_tx_descriptor *dma_desc_current; 240 struct mmci_host_next next_data; 241 242#define dma_inprogress(host) ((host)->dma_current) 243#else 244#define dma_inprogress(host) (0) 245#endif 246}; 247 248