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13#ifndef __SDHCI_HW_H
14#define __SDHCI_HW_H
15
16#include <linux/scatterlist.h>
17#include <linux/compiler.h>
18#include <linux/types.h>
19#include <linux/io.h>
20
21#include <linux/mmc/host.h>
22
23
24
25
26
27#define SDHCI_DMA_ADDRESS 0x00
28#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
29
30#define SDHCI_BLOCK_SIZE 0x04
31#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
32
33#define SDHCI_BLOCK_COUNT 0x06
34
35#define SDHCI_ARGUMENT 0x08
36
37#define SDHCI_TRANSFER_MODE 0x0C
38#define SDHCI_TRNS_DMA 0x01
39#define SDHCI_TRNS_BLK_CNT_EN 0x02
40#define SDHCI_TRNS_AUTO_CMD12 0x04
41#define SDHCI_TRNS_AUTO_CMD23 0x08
42#define SDHCI_TRNS_READ 0x10
43#define SDHCI_TRNS_MULTI 0x20
44
45#define SDHCI_COMMAND 0x0E
46#define SDHCI_CMD_RESP_MASK 0x03
47#define SDHCI_CMD_CRC 0x08
48#define SDHCI_CMD_INDEX 0x10
49#define SDHCI_CMD_DATA 0x20
50#define SDHCI_CMD_ABORTCMD 0xC0
51
52#define SDHCI_CMD_RESP_NONE 0x00
53#define SDHCI_CMD_RESP_LONG 0x01
54#define SDHCI_CMD_RESP_SHORT 0x02
55#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
56
57#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
58#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
59
60#define SDHCI_RESPONSE 0x10
61
62#define SDHCI_BUFFER 0x20
63
64#define SDHCI_PRESENT_STATE 0x24
65#define SDHCI_CMD_INHIBIT 0x00000001
66#define SDHCI_DATA_INHIBIT 0x00000002
67#define SDHCI_DOING_WRITE 0x00000100
68#define SDHCI_DOING_READ 0x00000200
69#define SDHCI_SPACE_AVAILABLE 0x00000400
70#define SDHCI_DATA_AVAILABLE 0x00000800
71#define SDHCI_CARD_PRESENT 0x00010000
72#define SDHCI_WRITE_PROTECT 0x00080000
73#define SDHCI_DATA_LVL_MASK 0x00F00000
74#define SDHCI_DATA_LVL_SHIFT 20
75#define SDHCI_DATA_0_LVL_MASK 0x00100000
76
77#define SDHCI_HOST_CONTROL 0x28
78#define SDHCI_CTRL_LED 0x01
79#define SDHCI_CTRL_4BITBUS 0x02
80#define SDHCI_CTRL_HISPD 0x04
81#define SDHCI_CTRL_DMA_MASK 0x18
82#define SDHCI_CTRL_SDMA 0x00
83#define SDHCI_CTRL_ADMA1 0x08
84#define SDHCI_CTRL_ADMA32 0x10
85#define SDHCI_CTRL_ADMA64 0x18
86#define SDHCI_CTRL_8BITBUS 0x20
87
88#define SDHCI_POWER_CONTROL 0x29
89#define SDHCI_POWER_ON 0x01
90#define SDHCI_POWER_180 0x0A
91#define SDHCI_POWER_300 0x0C
92#define SDHCI_POWER_330 0x0E
93
94#define SDHCI_BLOCK_GAP_CONTROL 0x2A
95
96#define SDHCI_WAKE_UP_CONTROL 0x2B
97#define SDHCI_WAKE_ON_INT 0x01
98#define SDHCI_WAKE_ON_INSERT 0x02
99#define SDHCI_WAKE_ON_REMOVE 0x04
100
101#define SDHCI_CLOCK_CONTROL 0x2C
102#define SDHCI_DIVIDER_SHIFT 8
103#define SDHCI_DIVIDER_HI_SHIFT 6
104#define SDHCI_DIV_MASK 0xFF
105#define SDHCI_DIV_MASK_LEN 8
106#define SDHCI_DIV_HI_MASK 0x300
107#define SDHCI_PROG_CLOCK_MODE 0x0020
108#define SDHCI_CLOCK_CARD_EN 0x0004
109#define SDHCI_CLOCK_INT_STABLE 0x0002
110#define SDHCI_CLOCK_INT_EN 0x0001
111
112#define SDHCI_TIMEOUT_CONTROL 0x2E
113
114#define SDHCI_SOFTWARE_RESET 0x2F
115#define SDHCI_RESET_ALL 0x01
116#define SDHCI_RESET_CMD 0x02
117#define SDHCI_RESET_DATA 0x04
118
119#define SDHCI_INT_STATUS 0x30
120#define SDHCI_INT_ENABLE 0x34
121#define SDHCI_SIGNAL_ENABLE 0x38
122#define SDHCI_INT_RESPONSE 0x00000001
123#define SDHCI_INT_DATA_END 0x00000002
124#define SDHCI_INT_BLK_GAP 0x00000004
125#define SDHCI_INT_DMA_END 0x00000008
126#define SDHCI_INT_SPACE_AVAIL 0x00000010
127#define SDHCI_INT_DATA_AVAIL 0x00000020
128#define SDHCI_INT_CARD_INSERT 0x00000040
129#define SDHCI_INT_CARD_REMOVE 0x00000080
130#define SDHCI_INT_CARD_INT 0x00000100
131#define SDHCI_INT_ERROR 0x00008000
132#define SDHCI_INT_TIMEOUT 0x00010000
133#define SDHCI_INT_CRC 0x00020000
134#define SDHCI_INT_END_BIT 0x00040000
135#define SDHCI_INT_INDEX 0x00080000
136#define SDHCI_INT_DATA_TIMEOUT 0x00100000
137#define SDHCI_INT_DATA_CRC 0x00200000
138#define SDHCI_INT_DATA_END_BIT 0x00400000
139#define SDHCI_INT_BUS_POWER 0x00800000
140#define SDHCI_INT_ACMD12ERR 0x01000000
141#define SDHCI_INT_ADMA_ERROR 0x02000000
142
143#define SDHCI_INT_NORMAL_MASK 0x00007FFF
144#define SDHCI_INT_ERROR_MASK 0xFFFF8000
145
146#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
147 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
148#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
149 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
150 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
151 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
152 SDHCI_INT_BLK_GAP)
153#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
154
155#define SDHCI_ACMD12_ERR 0x3C
156
157#define SDHCI_HOST_CONTROL2 0x3E
158#define SDHCI_CTRL_UHS_MASK 0x0007
159#define SDHCI_CTRL_UHS_SDR12 0x0000
160#define SDHCI_CTRL_UHS_SDR25 0x0001
161#define SDHCI_CTRL_UHS_SDR50 0x0002
162#define SDHCI_CTRL_UHS_SDR104 0x0003
163#define SDHCI_CTRL_UHS_DDR50 0x0004
164#define SDHCI_CTRL_HS400 0x0005
165#define SDHCI_CTRL_VDD_180 0x0008
166#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
167#define SDHCI_CTRL_DRV_TYPE_B 0x0000
168#define SDHCI_CTRL_DRV_TYPE_A 0x0010
169#define SDHCI_CTRL_DRV_TYPE_C 0x0020
170#define SDHCI_CTRL_DRV_TYPE_D 0x0030
171#define SDHCI_CTRL_EXEC_TUNING 0x0040
172#define SDHCI_CTRL_TUNED_CLK 0x0080
173#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
174
175#define SDHCI_CAPABILITIES 0x40
176#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
177#define SDHCI_TIMEOUT_CLK_SHIFT 0
178#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
179#define SDHCI_CLOCK_BASE_MASK 0x00003F00
180#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
181#define SDHCI_CLOCK_BASE_SHIFT 8
182#define SDHCI_MAX_BLOCK_MASK 0x00030000
183#define SDHCI_MAX_BLOCK_SHIFT 16
184#define SDHCI_CAN_DO_8BIT 0x00040000
185#define SDHCI_CAN_DO_ADMA2 0x00080000
186#define SDHCI_CAN_DO_ADMA1 0x00100000
187#define SDHCI_CAN_DO_HISPD 0x00200000
188#define SDHCI_CAN_DO_SDMA 0x00400000
189#define SDHCI_CAN_VDD_330 0x01000000
190#define SDHCI_CAN_VDD_300 0x02000000
191#define SDHCI_CAN_VDD_180 0x04000000
192#define SDHCI_CAN_64BIT 0x10000000
193
194#define SDHCI_SUPPORT_SDR50 0x00000001
195#define SDHCI_SUPPORT_SDR104 0x00000002
196#define SDHCI_SUPPORT_DDR50 0x00000004
197#define SDHCI_DRIVER_TYPE_A 0x00000010
198#define SDHCI_DRIVER_TYPE_C 0x00000020
199#define SDHCI_DRIVER_TYPE_D 0x00000040
200#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
201#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
202#define SDHCI_USE_SDR50_TUNING 0x00002000
203#define SDHCI_RETUNING_MODE_MASK 0x0000C000
204#define SDHCI_RETUNING_MODE_SHIFT 14
205#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
206#define SDHCI_CLOCK_MUL_SHIFT 16
207#define SDHCI_SUPPORT_HS400 0x80000000
208
209#define SDHCI_CAPABILITIES_1 0x44
210
211#define SDHCI_MAX_CURRENT 0x48
212#define SDHCI_MAX_CURRENT_LIMIT 0xFF
213#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF
214#define SDHCI_MAX_CURRENT_330_SHIFT 0
215#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00
216#define SDHCI_MAX_CURRENT_300_SHIFT 8
217#define SDHCI_MAX_CURRENT_180_MASK 0xFF0000
218#define SDHCI_MAX_CURRENT_180_SHIFT 16
219#define SDHCI_MAX_CURRENT_MULTIPLIER 4
220
221
222
223#define SDHCI_SET_ACMD12_ERROR 0x50
224#define SDHCI_SET_INT_ERROR 0x52
225
226#define SDHCI_ADMA_ERROR 0x54
227
228
229
230#define SDHCI_ADMA_ADDRESS 0x58
231#define SDHCI_ADMA_ADDRESS_HI 0x5C
232
233
234
235#define SDHCI_PRESET_FOR_SDR12 0x66
236#define SDHCI_PRESET_FOR_SDR25 0x68
237#define SDHCI_PRESET_FOR_SDR50 0x6A
238#define SDHCI_PRESET_FOR_SDR104 0x6C
239#define SDHCI_PRESET_FOR_DDR50 0x6E
240#define SDHCI_PRESET_FOR_HS400 0x74
241#define SDHCI_PRESET_DRV_MASK 0xC000
242#define SDHCI_PRESET_DRV_SHIFT 14
243#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400
244#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10
245#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF
246#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
247
248#define SDHCI_SLOT_INT_STATUS 0xFC
249
250#define SDHCI_HOST_VERSION 0xFE
251#define SDHCI_VENDOR_VER_MASK 0xFF00
252#define SDHCI_VENDOR_VER_SHIFT 8
253#define SDHCI_SPEC_VER_MASK 0x00FF
254#define SDHCI_SPEC_VER_SHIFT 0
255#define SDHCI_SPEC_100 0
256#define SDHCI_SPEC_200 1
257#define SDHCI_SPEC_300 2
258
259
260
261
262
263#define SDHCI_MAX_DIV_SPEC_200 256
264#define SDHCI_MAX_DIV_SPEC_300 2046
265
266
267
268
269#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
270#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
271
272
273#define SDHCI_ADMA2_32_DESC_SZ 8
274
275
276struct sdhci_adma2_32_desc {
277 __le16 cmd;
278 __le16 len;
279 __le32 addr;
280} __packed __aligned(4);
281
282
283#define SDHCI_ADMA2_ALIGN 4
284#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
285
286
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289
290
291#define SDHCI_ADMA2_DESC_ALIGN 8
292
293
294#define SDHCI_ADMA2_64_DESC_SZ 12
295
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297
298
299
300struct sdhci_adma2_64_desc {
301 __le16 cmd;
302 __le16 len;
303 __le32 addr_lo;
304 __le32 addr_hi;
305} __packed __aligned(4);
306
307#define ADMA2_TRAN_VALID 0x21
308#define ADMA2_NOP_END_VALID 0x3
309#define ADMA2_END 0x2
310
311
312
313
314
315#define SDHCI_MAX_SEGS 128
316
317enum sdhci_cookie {
318 COOKIE_UNMAPPED,
319 COOKIE_PRE_MAPPED,
320 COOKIE_MAPPED,
321};
322
323struct sdhci_host {
324
325 const char *hw_name;
326
327 unsigned int quirks;
328
329
330#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
331
332#define SDHCI_QUIRK_FORCE_DMA (1<<1)
333
334#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
335
336#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
337
338#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
339
340#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
341
342#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
343
344#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
345
346#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
347
348#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
349
350#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
351
352#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
353
354#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
355
356#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
357
358#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
359
360#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
361
362#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
363
364#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
365
366#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
367
368#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
369
370#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
371
372#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
373
374#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
375
376#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
377
378#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
379
380#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
381
382#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
383
384#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
385
386#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
387
388#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
389
390 unsigned int quirks2;
391
392#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
393#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
394
395#define SDHCI_QUIRK2_NO_1_8_V (1<<2)
396#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
397#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
398
399#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
400
401#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
402
403#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
404
405#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
406
407#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
408
409#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
410
411#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11)
412
413#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12)
414
415#define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13)
416
417#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
418
419#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
420
421 int irq;
422 void __iomem *ioaddr;
423
424 const struct sdhci_ops *ops;
425
426
427 struct mmc_host *mmc;
428 struct mmc_host_ops mmc_host_ops;
429 u64 dma_mask;
430
431#if IS_ENABLED(CONFIG_LEDS_CLASS)
432 struct led_classdev led;
433 char led_name[32];
434#endif
435
436 spinlock_t lock;
437
438 int flags;
439#define SDHCI_USE_SDMA (1<<0)
440#define SDHCI_USE_ADMA (1<<1)
441#define SDHCI_REQ_USE_DMA (1<<2)
442#define SDHCI_DEVICE_DEAD (1<<3)
443#define SDHCI_SDR50_NEEDS_TUNING (1<<4)
444#define SDHCI_AUTO_CMD12 (1<<6)
445#define SDHCI_AUTO_CMD23 (1<<7)
446#define SDHCI_PV_ENABLED (1<<8)
447#define SDHCI_SDIO_IRQ_ENABLED (1<<9)
448#define SDHCI_USE_64_BIT_DMA (1<<12)
449#define SDHCI_HS400_TUNING (1<<13)
450
451 unsigned int version;
452
453 unsigned int max_clk;
454 unsigned int timeout_clk;
455 unsigned int clk_mul;
456
457 unsigned int clock;
458 u8 pwr;
459
460 bool runtime_suspended;
461 bool bus_on;
462 bool preset_enabled;
463
464 struct mmc_request *mrq;
465 struct mmc_command *cmd;
466 struct mmc_data *data;
467 unsigned int data_early:1;
468 unsigned int busy_handle:1;
469
470 struct sg_mapping_iter sg_miter;
471 unsigned int blocks;
472
473 int sg_count;
474
475 void *adma_table;
476 void *align_buffer;
477
478 size_t adma_table_sz;
479 size_t align_buffer_sz;
480
481 dma_addr_t adma_addr;
482 dma_addr_t align_addr;
483
484 unsigned int desc_sz;
485
486 struct tasklet_struct finish_tasklet;
487
488 struct timer_list timer;
489
490 u32 caps;
491 u32 caps1;
492
493 unsigned int ocr_avail_sdio;
494 unsigned int ocr_avail_sd;
495 unsigned int ocr_avail_mmc;
496 u32 ocr_mask;
497
498 unsigned timing;
499
500 u32 thread_isr;
501
502
503 u32 ier;
504
505 wait_queue_head_t buf_ready_int;
506 unsigned int tuning_done;
507
508 unsigned int tuning_count;
509 unsigned int tuning_mode;
510#define SDHCI_TUNING_MODE_1 0
511
512 unsigned long private[0] ____cacheline_aligned;
513};
514
515struct sdhci_ops {
516#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
517 u32 (*read_l)(struct sdhci_host *host, int reg);
518 u16 (*read_w)(struct sdhci_host *host, int reg);
519 u8 (*read_b)(struct sdhci_host *host, int reg);
520 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
521 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
522 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
523#endif
524
525 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
526 void (*set_power)(struct sdhci_host *host, unsigned char mode,
527 unsigned short vdd);
528
529 int (*enable_dma)(struct sdhci_host *host);
530 unsigned int (*get_max_clock)(struct sdhci_host *host);
531 unsigned int (*get_min_clock)(struct sdhci_host *host);
532 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
533 unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
534 void (*set_timeout)(struct sdhci_host *host,
535 struct mmc_command *cmd);
536 void (*set_bus_width)(struct sdhci_host *host, int width);
537 void (*platform_send_init_74_clocks)(struct sdhci_host *host,
538 u8 power_mode);
539 unsigned int (*get_ro)(struct sdhci_host *host);
540 void (*reset)(struct sdhci_host *host, u8 mask);
541 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
542 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
543 void (*hw_reset)(struct sdhci_host *host);
544 void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
545 void (*platform_init)(struct sdhci_host *host);
546 void (*card_event)(struct sdhci_host *host);
547 void (*voltage_switch)(struct sdhci_host *host);
548 int (*select_drive_strength)(struct sdhci_host *host,
549 struct mmc_card *card,
550 unsigned int max_dtr, int host_drv,
551 int card_drv, int *drv_type);
552};
553
554#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
555
556static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
557{
558 if (unlikely(host->ops->write_l))
559 host->ops->write_l(host, val, reg);
560 else
561 writel(val, host->ioaddr + reg);
562}
563
564static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
565{
566 if (unlikely(host->ops->write_w))
567 host->ops->write_w(host, val, reg);
568 else
569 writew(val, host->ioaddr + reg);
570}
571
572static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
573{
574 if (unlikely(host->ops->write_b))
575 host->ops->write_b(host, val, reg);
576 else
577 writeb(val, host->ioaddr + reg);
578}
579
580static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
581{
582 if (unlikely(host->ops->read_l))
583 return host->ops->read_l(host, reg);
584 else
585 return readl(host->ioaddr + reg);
586}
587
588static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
589{
590 if (unlikely(host->ops->read_w))
591 return host->ops->read_w(host, reg);
592 else
593 return readw(host->ioaddr + reg);
594}
595
596static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
597{
598 if (unlikely(host->ops->read_b))
599 return host->ops->read_b(host, reg);
600 else
601 return readb(host->ioaddr + reg);
602}
603
604#else
605
606static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
607{
608 writel(val, host->ioaddr + reg);
609}
610
611static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
612{
613 writew(val, host->ioaddr + reg);
614}
615
616static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
617{
618 writeb(val, host->ioaddr + reg);
619}
620
621static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
622{
623 return readl(host->ioaddr + reg);
624}
625
626static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
627{
628 return readw(host->ioaddr + reg);
629}
630
631static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
632{
633 return readb(host->ioaddr + reg);
634}
635
636#endif
637
638extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
639 size_t priv_size);
640extern void sdhci_free_host(struct sdhci_host *host);
641
642static inline void *sdhci_priv(struct sdhci_host *host)
643{
644 return (void *)host->private;
645}
646
647extern void sdhci_card_detect(struct sdhci_host *host);
648extern int sdhci_add_host(struct sdhci_host *host);
649extern void sdhci_remove_host(struct sdhci_host *host, int dead);
650extern void sdhci_send_command(struct sdhci_host *host,
651 struct mmc_command *cmd);
652
653static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
654{
655 return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
656}
657
658u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
659 unsigned int *actual_clock);
660void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
661void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
662 unsigned short vdd);
663void sdhci_set_bus_width(struct sdhci_host *host, int width);
664void sdhci_reset(struct sdhci_host *host, u8 mask);
665void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
666
667#ifdef CONFIG_PM
668extern int sdhci_suspend_host(struct sdhci_host *host);
669extern int sdhci_resume_host(struct sdhci_host *host);
670extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
671extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
672extern int sdhci_runtime_resume_host(struct sdhci_host *host);
673#endif
674
675#endif
676