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59#include "e1000.h"
60
61
62
63union ich8_hws_flash_status {
64 struct ich8_hsfsts {
65 u16 flcdone:1;
66 u16 flcerr:1;
67 u16 dael:1;
68 u16 berasesz:2;
69 u16 flcinprog:1;
70 u16 reserved1:2;
71 u16 reserved2:6;
72 u16 fldesvalid:1;
73 u16 flockdn:1;
74 } hsf_status;
75 u16 regval;
76};
77
78
79
80union ich8_hws_flash_ctrl {
81 struct ich8_hsflctl {
82 u16 flcgo:1;
83 u16 flcycle:2;
84 u16 reserved:5;
85 u16 fldbcount:2;
86 u16 flockdn:6;
87 } hsf_ctrl;
88 u16 regval;
89};
90
91
92union ich8_hws_flash_regacc {
93 struct ich8_flracc {
94 u32 grra:8;
95 u32 grwa:8;
96 u32 gmrag:8;
97 u32 gmwag:8;
98 } hsf_flregacc;
99 u16 regval;
100};
101
102
103union ich8_flash_protected_range {
104 struct ich8_pr {
105 u32 base:13;
106 u32 reserved1:2;
107 u32 rpe:1;
108 u32 limit:13;
109 u32 reserved2:2;
110 u32 wpe:1;
111 } range;
112 u32 regval;
113};
114
115static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
116static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
117static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
118static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
119 u32 offset, u8 byte);
120static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
121 u8 *data);
122static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
123 u16 *data);
124static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
125 u8 size, u16 *data);
126static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
127 u32 *data);
128static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
129 u32 offset, u32 *data);
130static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
131 u32 offset, u32 data);
132static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
133 u32 offset, u32 dword);
134static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
135static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
136static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
137static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
138static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
139static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
140static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
141static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
142static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
143static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
144static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
145static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
146static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
147static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
148static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
149static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
150static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
151static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
152static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
153static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
154static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
155static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
156static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
157static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
158
159static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
160{
161 return readw(hw->flash_address + reg);
162}
163
164static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
165{
166 return readl(hw->flash_address + reg);
167}
168
169static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
170{
171 writew(val, hw->flash_address + reg);
172}
173
174static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
175{
176 writel(val, hw->flash_address + reg);
177}
178
179#define er16flash(reg) __er16flash(hw, (reg))
180#define er32flash(reg) __er32flash(hw, (reg))
181#define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
182#define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
183
184
185
186
187
188
189
190
191
192
193
194static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
195{
196 u16 phy_reg = 0;
197 u32 phy_id = 0;
198 s32 ret_val = 0;
199 u16 retry_count;
200 u32 mac_reg = 0;
201
202 for (retry_count = 0; retry_count < 2; retry_count++) {
203 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
204 if (ret_val || (phy_reg == 0xFFFF))
205 continue;
206 phy_id = (u32)(phy_reg << 16);
207
208 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
209 if (ret_val || (phy_reg == 0xFFFF)) {
210 phy_id = 0;
211 continue;
212 }
213 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
214 break;
215 }
216
217 if (hw->phy.id) {
218 if (hw->phy.id == phy_id)
219 goto out;
220 } else if (phy_id) {
221 hw->phy.id = phy_id;
222 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
223 goto out;
224 }
225
226
227
228
229 if (hw->mac.type < e1000_pch_lpt) {
230 hw->phy.ops.release(hw);
231 ret_val = e1000_set_mdio_slow_mode_hv(hw);
232 if (!ret_val)
233 ret_val = e1000e_get_phy_id(hw);
234 hw->phy.ops.acquire(hw);
235 }
236
237 if (ret_val)
238 return false;
239out:
240 if ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) {
241
242 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
243
244 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
245 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
246 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
247
248
249 mac_reg = er32(CTRL_EXT);
250 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
251 ew32(CTRL_EXT, mac_reg);
252 }
253 }
254
255 return true;
256}
257
258
259
260
261
262
263
264
265static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
266{
267 u32 mac_reg;
268
269
270 mac_reg = er32(FEXTNVM3);
271 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
272 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
273 ew32(FEXTNVM3, mac_reg);
274
275
276 mac_reg = er32(CTRL);
277 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
278 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
279 ew32(CTRL, mac_reg);
280 e1e_flush();
281 usleep_range(10, 20);
282 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
283 ew32(CTRL, mac_reg);
284 e1e_flush();
285
286 if (hw->mac.type < e1000_pch_lpt) {
287 msleep(50);
288 } else {
289 u16 count = 20;
290
291 do {
292 usleep_range(5000, 10000);
293 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
294
295 msleep(30);
296 }
297}
298
299
300
301
302
303
304
305
306static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
307{
308 struct e1000_adapter *adapter = hw->adapter;
309 u32 mac_reg, fwsm = er32(FWSM);
310 s32 ret_val;
311
312
313
314
315 e1000_gate_hw_phy_config_ich8lan(hw, true);
316
317
318
319
320 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
321 e1000_disable_ulp_lpt_lp(hw, true);
322
323 ret_val = hw->phy.ops.acquire(hw);
324 if (ret_val) {
325 e_dbg("Failed to initialize PHY flow\n");
326 goto out;
327 }
328
329
330
331
332
333 switch (hw->mac.type) {
334 case e1000_pch_lpt:
335 case e1000_pch_spt:
336 if (e1000_phy_is_accessible_pchlan(hw))
337 break;
338
339
340
341
342 mac_reg = er32(CTRL_EXT);
343 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
344 ew32(CTRL_EXT, mac_reg);
345
346
347
348
349
350 msleep(50);
351
352
353 case e1000_pch2lan:
354 if (e1000_phy_is_accessible_pchlan(hw))
355 break;
356
357
358 case e1000_pchlan:
359 if ((hw->mac.type == e1000_pchlan) &&
360 (fwsm & E1000_ICH_FWSM_FW_VALID))
361 break;
362
363 if (hw->phy.ops.check_reset_block(hw)) {
364 e_dbg("Required LANPHYPC toggle blocked by ME\n");
365 ret_val = -E1000_ERR_PHY;
366 break;
367 }
368
369
370 e1000_toggle_lanphypc_pch_lpt(hw);
371 if (hw->mac.type >= e1000_pch_lpt) {
372 if (e1000_phy_is_accessible_pchlan(hw))
373 break;
374
375
376
377
378 mac_reg = er32(CTRL_EXT);
379 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
380 ew32(CTRL_EXT, mac_reg);
381
382 if (e1000_phy_is_accessible_pchlan(hw))
383 break;
384
385 ret_val = -E1000_ERR_PHY;
386 }
387 break;
388 default:
389 break;
390 }
391
392 hw->phy.ops.release(hw);
393 if (!ret_val) {
394
395
396 if (hw->phy.ops.check_reset_block(hw)) {
397 e_err("Reset blocked by ME\n");
398 goto out;
399 }
400
401
402
403
404
405
406 ret_val = e1000e_phy_hw_reset_generic(hw);
407 if (ret_val)
408 goto out;
409
410
411
412
413
414
415
416 ret_val = hw->phy.ops.check_reset_block(hw);
417 if (ret_val)
418 e_err("ME blocked access to PHY after reset\n");
419 }
420
421out:
422
423 if ((hw->mac.type == e1000_pch2lan) &&
424 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
425 usleep_range(10000, 20000);
426 e1000_gate_hw_phy_config_ich8lan(hw, false);
427 }
428
429 return ret_val;
430}
431
432
433
434
435
436
437
438static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
439{
440 struct e1000_phy_info *phy = &hw->phy;
441 s32 ret_val;
442
443 phy->addr = 1;
444 phy->reset_delay_us = 100;
445
446 phy->ops.set_page = e1000_set_page_igp;
447 phy->ops.read_reg = e1000_read_phy_reg_hv;
448 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
449 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
450 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
451 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
452 phy->ops.write_reg = e1000_write_phy_reg_hv;
453 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
454 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
455 phy->ops.power_up = e1000_power_up_phy_copper;
456 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
457 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
458
459 phy->id = e1000_phy_unknown;
460
461 ret_val = e1000_init_phy_workarounds_pchlan(hw);
462 if (ret_val)
463 return ret_val;
464
465 if (phy->id == e1000_phy_unknown)
466 switch (hw->mac.type) {
467 default:
468 ret_val = e1000e_get_phy_id(hw);
469 if (ret_val)
470 return ret_val;
471 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
472 break;
473
474 case e1000_pch2lan:
475 case e1000_pch_lpt:
476 case e1000_pch_spt:
477
478
479
480 ret_val = e1000_set_mdio_slow_mode_hv(hw);
481 if (ret_val)
482 return ret_val;
483 ret_val = e1000e_get_phy_id(hw);
484 if (ret_val)
485 return ret_val;
486 break;
487 }
488 phy->type = e1000e_get_phy_type_from_id(phy->id);
489
490 switch (phy->type) {
491 case e1000_phy_82577:
492 case e1000_phy_82579:
493 case e1000_phy_i217:
494 phy->ops.check_polarity = e1000_check_polarity_82577;
495 phy->ops.force_speed_duplex =
496 e1000_phy_force_speed_duplex_82577;
497 phy->ops.get_cable_length = e1000_get_cable_length_82577;
498 phy->ops.get_info = e1000_get_phy_info_82577;
499 phy->ops.commit = e1000e_phy_sw_reset;
500 break;
501 case e1000_phy_82578:
502 phy->ops.check_polarity = e1000_check_polarity_m88;
503 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
504 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
505 phy->ops.get_info = e1000e_get_phy_info_m88;
506 break;
507 default:
508 ret_val = -E1000_ERR_PHY;
509 break;
510 }
511
512 return ret_val;
513}
514
515
516
517
518
519
520
521static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
522{
523 struct e1000_phy_info *phy = &hw->phy;
524 s32 ret_val;
525 u16 i = 0;
526
527 phy->addr = 1;
528 phy->reset_delay_us = 100;
529
530 phy->ops.power_up = e1000_power_up_phy_copper;
531 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
532
533
534
535
536 ret_val = e1000e_determine_phy_address(hw);
537 if (ret_val) {
538 phy->ops.write_reg = e1000e_write_phy_reg_bm;
539 phy->ops.read_reg = e1000e_read_phy_reg_bm;
540 ret_val = e1000e_determine_phy_address(hw);
541 if (ret_val) {
542 e_dbg("Cannot determine PHY addr. Erroring out\n");
543 return ret_val;
544 }
545 }
546
547 phy->id = 0;
548 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
549 (i++ < 100)) {
550 usleep_range(1000, 2000);
551 ret_val = e1000e_get_phy_id(hw);
552 if (ret_val)
553 return ret_val;
554 }
555
556
557 switch (phy->id) {
558 case IGP03E1000_E_PHY_ID:
559 phy->type = e1000_phy_igp_3;
560 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
561 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
562 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
563 phy->ops.get_info = e1000e_get_phy_info_igp;
564 phy->ops.check_polarity = e1000_check_polarity_igp;
565 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
566 break;
567 case IFE_E_PHY_ID:
568 case IFE_PLUS_E_PHY_ID:
569 case IFE_C_E_PHY_ID:
570 phy->type = e1000_phy_ife;
571 phy->autoneg_mask = E1000_ALL_NOT_GIG;
572 phy->ops.get_info = e1000_get_phy_info_ife;
573 phy->ops.check_polarity = e1000_check_polarity_ife;
574 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
575 break;
576 case BME1000_E_PHY_ID:
577 phy->type = e1000_phy_bm;
578 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
579 phy->ops.read_reg = e1000e_read_phy_reg_bm;
580 phy->ops.write_reg = e1000e_write_phy_reg_bm;
581 phy->ops.commit = e1000e_phy_sw_reset;
582 phy->ops.get_info = e1000e_get_phy_info_m88;
583 phy->ops.check_polarity = e1000_check_polarity_m88;
584 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
585 break;
586 default:
587 return -E1000_ERR_PHY;
588 }
589
590 return 0;
591}
592
593
594
595
596
597
598
599
600static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
601{
602 struct e1000_nvm_info *nvm = &hw->nvm;
603 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
604 u32 gfpreg, sector_base_addr, sector_end_addr;
605 u16 i;
606 u32 nvm_size;
607
608 nvm->type = e1000_nvm_flash_sw;
609
610 if (hw->mac.type == e1000_pch_spt) {
611
612
613
614
615
616
617 nvm->flash_base_addr = 0;
618 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
619 * NVM_SIZE_MULTIPLIER;
620 nvm->flash_bank_size = nvm_size / 2;
621
622 nvm->flash_bank_size /= sizeof(u16);
623
624 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
625 } else {
626
627 if (!hw->flash_address) {
628 e_dbg("ERROR: Flash registers not mapped\n");
629 return -E1000_ERR_CONFIG;
630 }
631
632 gfpreg = er32flash(ICH_FLASH_GFPREG);
633
634
635
636
637
638 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
639 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
640
641
642 nvm->flash_base_addr = sector_base_addr
643 << FLASH_SECTOR_ADDR_SHIFT;
644
645
646
647
648 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
649 << FLASH_SECTOR_ADDR_SHIFT);
650 nvm->flash_bank_size /= 2;
651
652 nvm->flash_bank_size /= sizeof(u16);
653 }
654
655 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
656
657
658 for (i = 0; i < nvm->word_size; i++) {
659 dev_spec->shadow_ram[i].modified = false;
660 dev_spec->shadow_ram[i].value = 0xFFFF;
661 }
662
663 return 0;
664}
665
666
667
668
669
670
671
672
673static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
674{
675 struct e1000_mac_info *mac = &hw->mac;
676
677
678 hw->phy.media_type = e1000_media_type_copper;
679
680
681 mac->mta_reg_count = 32;
682
683 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
684 if (mac->type == e1000_ich8lan)
685 mac->rar_entry_count--;
686
687 mac->has_fwsm = true;
688
689 mac->arc_subsystem_valid = false;
690
691 mac->adaptive_ifs = true;
692
693
694 switch (mac->type) {
695 case e1000_ich8lan:
696 case e1000_ich9lan:
697 case e1000_ich10lan:
698
699 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
700
701 mac->ops.id_led_init = e1000e_id_led_init_generic;
702
703 mac->ops.blink_led = e1000e_blink_led_generic;
704
705 mac->ops.setup_led = e1000e_setup_led_generic;
706
707 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
708
709 mac->ops.led_on = e1000_led_on_ich8lan;
710 mac->ops.led_off = e1000_led_off_ich8lan;
711 break;
712 case e1000_pch2lan:
713 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
714 mac->ops.rar_set = e1000_rar_set_pch2lan;
715
716 case e1000_pch_lpt:
717 case e1000_pch_spt:
718 case e1000_pchlan:
719
720 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
721
722 mac->ops.id_led_init = e1000_id_led_init_pchlan;
723
724 mac->ops.setup_led = e1000_setup_led_pchlan;
725
726 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
727
728 mac->ops.led_on = e1000_led_on_pchlan;
729 mac->ops.led_off = e1000_led_off_pchlan;
730 break;
731 default:
732 break;
733 }
734
735 if ((mac->type == e1000_pch_lpt) || (mac->type == e1000_pch_spt)) {
736 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
737 mac->ops.rar_set = e1000_rar_set_pch_lpt;
738 mac->ops.setup_physical_interface =
739 e1000_setup_copper_link_pch_lpt;
740 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
741 }
742
743
744 if (mac->type == e1000_ich8lan)
745 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
746
747 return 0;
748}
749
750
751
752
753
754
755
756
757
758
759static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
760 u16 *data, bool read)
761{
762 s32 ret_val;
763
764 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
765 if (ret_val)
766 return ret_val;
767
768 if (read)
769 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
770 else
771 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
772
773 return ret_val;
774}
775
776
777
778
779
780
781
782
783
784s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
785{
786 return __e1000_access_emi_reg_locked(hw, addr, data, true);
787}
788
789
790
791
792
793
794
795
796
797s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
798{
799 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
800}
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
817{
818 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
819 s32 ret_val;
820 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
821
822 switch (hw->phy.type) {
823 case e1000_phy_82579:
824 lpa = I82579_EEE_LP_ABILITY;
825 pcs_status = I82579_EEE_PCS_STATUS;
826 adv_addr = I82579_EEE_ADVERTISEMENT;
827 break;
828 case e1000_phy_i217:
829 lpa = I217_EEE_LP_ABILITY;
830 pcs_status = I217_EEE_PCS_STATUS;
831 adv_addr = I217_EEE_ADVERTISEMENT;
832 break;
833 default:
834 return 0;
835 }
836
837 ret_val = hw->phy.ops.acquire(hw);
838 if (ret_val)
839 return ret_val;
840
841 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
842 if (ret_val)
843 goto release;
844
845
846 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
847
848
849 if (!dev_spec->eee_disable) {
850
851 ret_val = e1000_read_emi_reg_locked(hw, lpa,
852 &dev_spec->eee_lp_ability);
853 if (ret_val)
854 goto release;
855
856
857 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
858 if (ret_val)
859 goto release;
860
861
862
863
864 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
865 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
866
867 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
868 e1e_rphy_locked(hw, MII_LPA, &data);
869 if (data & LPA_100FULL)
870 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
871 else
872
873
874
875
876 dev_spec->eee_lp_ability &=
877 ~I82579_EEE_100_SUPPORTED;
878 }
879 }
880
881 if (hw->phy.type == e1000_phy_82579) {
882 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
883 &data);
884 if (ret_val)
885 goto release;
886
887 data &= ~I82579_LPI_100_PLL_SHUT;
888 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
889 data);
890 }
891
892
893 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
894 if (ret_val)
895 goto release;
896
897 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
898release:
899 hw->phy.ops.release(hw);
900
901 return ret_val;
902}
903
904
905
906
907
908
909
910
911
912
913
914
915static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
916{
917 u32 fextnvm6 = er32(FEXTNVM6);
918 u32 status = er32(STATUS);
919 s32 ret_val = 0;
920 u16 reg;
921
922 if (link && (status & E1000_STATUS_SPEED_1000)) {
923 ret_val = hw->phy.ops.acquire(hw);
924 if (ret_val)
925 return ret_val;
926
927 ret_val =
928 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
929 ®);
930 if (ret_val)
931 goto release;
932
933 ret_val =
934 e1000e_write_kmrn_reg_locked(hw,
935 E1000_KMRNCTRLSTA_K1_CONFIG,
936 reg &
937 ~E1000_KMRNCTRLSTA_K1_ENABLE);
938 if (ret_val)
939 goto release;
940
941 usleep_range(10, 20);
942
943 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
944
945 ret_val =
946 e1000e_write_kmrn_reg_locked(hw,
947 E1000_KMRNCTRLSTA_K1_CONFIG,
948 reg);
949release:
950 hw->phy.ops.release(hw);
951 } else {
952
953 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
954
955 if ((hw->phy.revision > 5) || !link ||
956 ((status & E1000_STATUS_SPEED_100) &&
957 (status & E1000_STATUS_FD)))
958 goto update_fextnvm6;
959
960 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®);
961 if (ret_val)
962 return ret_val;
963
964
965 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
966
967 if (status & E1000_STATUS_SPEED_100) {
968
969 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
970
971
972 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
973 } else {
974
975 reg |= 50 <<
976 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
977
978
979 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
980 }
981
982 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
983 if (ret_val)
984 return ret_val;
985
986update_fextnvm6:
987 ew32(FEXTNVM6, fextnvm6);
988 }
989
990 return ret_val;
991}
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1010{
1011 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1012 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1013 u16 lat_enc = 0;
1014
1015 if (link) {
1016 u16 speed, duplex, scale = 0;
1017 u16 max_snoop, max_nosnoop;
1018 u16 max_ltr_enc;
1019 u64 value;
1020 u32 rxa;
1021
1022 if (!hw->adapter->max_frame_size) {
1023 e_dbg("max_frame_size not set.\n");
1024 return -E1000_ERR_CONFIG;
1025 }
1026
1027 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1028 if (!speed) {
1029 e_dbg("Speed not set.\n");
1030 return -E1000_ERR_CONFIG;
1031 }
1032
1033
1034 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044 rxa *= 512;
1045 value = (rxa > hw->adapter->max_frame_size) ?
1046 (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1047 0;
1048
1049 while (value > PCI_LTR_VALUE_MASK) {
1050 scale++;
1051 value = DIV_ROUND_UP(value, BIT(5));
1052 }
1053 if (scale > E1000_LTRV_SCALE_MAX) {
1054 e_dbg("Invalid LTR latency scale %d\n", scale);
1055 return -E1000_ERR_CONFIG;
1056 }
1057 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1058
1059
1060 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1061 &max_snoop);
1062 pci_read_config_word(hw->adapter->pdev,
1063 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1064 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1065
1066 if (lat_enc > max_ltr_enc)
1067 lat_enc = max_ltr_enc;
1068 }
1069
1070
1071 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1072 ew32(LTRV, reg);
1073
1074 return 0;
1075}
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1088{
1089 u32 mac_reg;
1090 s32 ret_val = 0;
1091 u16 phy_reg;
1092 u16 oem_reg = 0;
1093
1094 if ((hw->mac.type < e1000_pch_lpt) ||
1095 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1096 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1097 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1098 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1099 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1100 return 0;
1101
1102 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1103
1104 mac_reg = er32(H2ME);
1105 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1106 ew32(H2ME, mac_reg);
1107
1108 goto out;
1109 }
1110
1111 if (!to_sx) {
1112 int i = 0;
1113
1114
1115 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1116
1117 if (er32(STATUS) & E1000_STATUS_LU)
1118 return -E1000_ERR_PHY;
1119
1120 if (i++ == 100)
1121 break;
1122
1123 msleep(50);
1124 }
1125 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1126 (er32(FEXT) &
1127 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1128 }
1129
1130 ret_val = hw->phy.ops.acquire(hw);
1131 if (ret_val)
1132 goto out;
1133
1134
1135 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1136 if (ret_val)
1137 goto release;
1138 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1139 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1140
1141
1142 mac_reg = er32(CTRL_EXT);
1143 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1144 ew32(CTRL_EXT, mac_reg);
1145
1146
1147
1148
1149 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1150 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1151 &oem_reg);
1152 if (ret_val)
1153 goto release;
1154
1155 phy_reg = oem_reg;
1156 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1157
1158 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1159 phy_reg);
1160
1161 if (ret_val)
1162 goto release;
1163 }
1164
1165
1166
1167
1168 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1169 if (ret_val)
1170 goto release;
1171 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1172 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1173 if (to_sx) {
1174 if (er32(WUFC) & E1000_WUFC_LNKC)
1175 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1176 else
1177 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1178
1179 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1180 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1181 } else {
1182 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1183 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1184 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1185 }
1186 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1187
1188
1189 mac_reg = er32(FEXTNVM7);
1190 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1191 ew32(FEXTNVM7, mac_reg);
1192
1193
1194 phy_reg |= I218_ULP_CONFIG1_START;
1195 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1196
1197 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1198 to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1199 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1200 oem_reg);
1201 if (ret_val)
1202 goto release;
1203 }
1204
1205release:
1206 hw->phy.ops.release(hw);
1207out:
1208 if (ret_val)
1209 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1210 else
1211 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1212
1213 return ret_val;
1214}
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1232{
1233 s32 ret_val = 0;
1234 u32 mac_reg;
1235 u16 phy_reg;
1236 int i = 0;
1237
1238 if ((hw->mac.type < e1000_pch_lpt) ||
1239 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1240 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1241 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1242 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1243 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1244 return 0;
1245
1246 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1247 if (force) {
1248
1249 mac_reg = er32(H2ME);
1250 mac_reg &= ~E1000_H2ME_ULP;
1251 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1252 ew32(H2ME, mac_reg);
1253 }
1254
1255
1256 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1257 if (i++ == 30) {
1258 ret_val = -E1000_ERR_PHY;
1259 goto out;
1260 }
1261
1262 usleep_range(10000, 20000);
1263 }
1264 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1265
1266 if (force) {
1267 mac_reg = er32(H2ME);
1268 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1269 ew32(H2ME, mac_reg);
1270 } else {
1271
1272 mac_reg = er32(H2ME);
1273 mac_reg &= ~E1000_H2ME_ULP;
1274 ew32(H2ME, mac_reg);
1275 }
1276
1277 goto out;
1278 }
1279
1280 ret_val = hw->phy.ops.acquire(hw);
1281 if (ret_val)
1282 goto out;
1283
1284 if (force)
1285
1286 e1000_toggle_lanphypc_pch_lpt(hw);
1287
1288
1289 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1290 if (ret_val) {
1291
1292
1293
1294 mac_reg = er32(CTRL_EXT);
1295 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1296 ew32(CTRL_EXT, mac_reg);
1297
1298 msleep(50);
1299
1300 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1301 &phy_reg);
1302 if (ret_val)
1303 goto release;
1304 }
1305 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1306 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1307
1308
1309 mac_reg = er32(CTRL_EXT);
1310 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1311 ew32(CTRL_EXT, mac_reg);
1312
1313
1314
1315
1316 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1317 if (ret_val)
1318 goto release;
1319 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1320 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1321
1322
1323 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1324 if (ret_val)
1325 goto release;
1326 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1327 I218_ULP_CONFIG1_STICKY_ULP |
1328 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1329 I218_ULP_CONFIG1_WOL_HOST |
1330 I218_ULP_CONFIG1_INBAND_EXIT |
1331 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1332 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1333 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1334 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1335
1336
1337 phy_reg |= I218_ULP_CONFIG1_START;
1338 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1339
1340
1341 mac_reg = er32(FEXTNVM7);
1342 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1343 ew32(FEXTNVM7, mac_reg);
1344
1345release:
1346 hw->phy.ops.release(hw);
1347 if (force) {
1348 e1000_phy_hw_reset(hw);
1349 msleep(50);
1350 }
1351out:
1352 if (ret_val)
1353 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1354 else
1355 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1356
1357 return ret_val;
1358}
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1369{
1370 struct e1000_mac_info *mac = &hw->mac;
1371 s32 ret_val, tipg_reg = 0;
1372 u16 emi_addr, emi_val = 0;
1373 bool link;
1374 u16 phy_reg;
1375
1376
1377
1378
1379
1380
1381 if (!mac->get_link_status)
1382 return 0;
1383
1384
1385
1386
1387
1388 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1389 if (ret_val)
1390 return ret_val;
1391
1392 if (hw->mac.type == e1000_pchlan) {
1393 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1394 if (ret_val)
1395 return ret_val;
1396 }
1397
1398
1399
1400
1401
1402 if (((hw->mac.type == e1000_pch2lan) ||
1403 (hw->mac.type == e1000_pch_lpt) ||
1404 (hw->mac.type == e1000_pch_spt)) && link) {
1405 u16 speed, duplex;
1406
1407 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1408 tipg_reg = er32(TIPG);
1409 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1410
1411 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1412 tipg_reg |= 0xFF;
1413
1414 emi_val = 0;
1415 } else if (hw->mac.type == e1000_pch_spt &&
1416 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1417 tipg_reg |= 0xC;
1418 emi_val = 1;
1419 } else {
1420
1421
1422 tipg_reg |= 0x08;
1423 emi_val = 1;
1424 }
1425
1426 ew32(TIPG, tipg_reg);
1427
1428 ret_val = hw->phy.ops.acquire(hw);
1429 if (ret_val)
1430 return ret_val;
1431
1432 if (hw->mac.type == e1000_pch2lan)
1433 emi_addr = I82579_RX_CONFIG;
1434 else
1435 emi_addr = I217_RX_CONFIG;
1436 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1437
1438 if (hw->mac.type == e1000_pch_lpt ||
1439 hw->mac.type == e1000_pch_spt) {
1440 u16 phy_reg;
1441
1442 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1443 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1444 if (speed == SPEED_100 || speed == SPEED_10)
1445 phy_reg |= 0x3E8;
1446 else
1447 phy_reg |= 0xFA;
1448 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1449 }
1450 hw->phy.ops.release(hw);
1451
1452 if (ret_val)
1453 return ret_val;
1454
1455 if (hw->mac.type == e1000_pch_spt) {
1456 u16 data;
1457 u16 ptr_gap;
1458
1459 if (speed == SPEED_1000) {
1460 ret_val = hw->phy.ops.acquire(hw);
1461 if (ret_val)
1462 return ret_val;
1463
1464 ret_val = e1e_rphy_locked(hw,
1465 PHY_REG(776, 20),
1466 &data);
1467 if (ret_val) {
1468 hw->phy.ops.release(hw);
1469 return ret_val;
1470 }
1471
1472 ptr_gap = (data & (0x3FF << 2)) >> 2;
1473 if (ptr_gap < 0x18) {
1474 data &= ~(0x3FF << 2);
1475 data |= (0x18 << 2);
1476 ret_val =
1477 e1e_wphy_locked(hw,
1478 PHY_REG(776, 20),
1479 data);
1480 }
1481 hw->phy.ops.release(hw);
1482 if (ret_val)
1483 return ret_val;
1484 } else {
1485 ret_val = hw->phy.ops.acquire(hw);
1486 if (ret_val)
1487 return ret_val;
1488
1489 ret_val = e1e_wphy_locked(hw,
1490 PHY_REG(776, 20),
1491 0xC023);
1492 hw->phy.ops.release(hw);
1493 if (ret_val)
1494 return ret_val;
1495
1496 }
1497 }
1498 }
1499
1500
1501
1502
1503
1504
1505 if ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) {
1506 u32 mac_reg;
1507
1508 mac_reg = er32(FEXTNVM4);
1509 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1510 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1511 ew32(FEXTNVM4, mac_reg);
1512 }
1513
1514
1515 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1516 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1517 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1518 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1519 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1520 if (ret_val)
1521 return ret_val;
1522 }
1523 if ((hw->mac.type == e1000_pch_lpt) ||
1524 (hw->mac.type == e1000_pch_spt)) {
1525
1526
1527
1528 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1529 if (ret_val)
1530 return ret_val;
1531 }
1532
1533
1534 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1535
1536
1537 if (hw->mac.type == e1000_pch_spt) {
1538 u32 pcieanacfg = er32(PCIEANACFG);
1539 u32 fextnvm6 = er32(FEXTNVM6);
1540
1541 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1542 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1543 else
1544 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1545
1546 ew32(FEXTNVM6, fextnvm6);
1547 }
1548
1549 if (!link)
1550 return 0;
1551
1552 mac->get_link_status = false;
1553
1554 switch (hw->mac.type) {
1555 case e1000_pch2lan:
1556 ret_val = e1000_k1_workaround_lv(hw);
1557 if (ret_val)
1558 return ret_val;
1559
1560 case e1000_pchlan:
1561 if (hw->phy.type == e1000_phy_82578) {
1562 ret_val = e1000_link_stall_workaround_hv(hw);
1563 if (ret_val)
1564 return ret_val;
1565 }
1566
1567
1568
1569
1570
1571
1572 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1573 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1574
1575 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1576 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1577
1578 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1579 break;
1580 default:
1581 break;
1582 }
1583
1584
1585
1586
1587 e1000e_check_downshift(hw);
1588
1589
1590 if (hw->phy.type > e1000_phy_82579) {
1591 ret_val = e1000_set_eee_pchlan(hw);
1592 if (ret_val)
1593 return ret_val;
1594 }
1595
1596
1597
1598
1599 if (!mac->autoneg)
1600 return -E1000_ERR_CONFIG;
1601
1602
1603
1604
1605
1606 mac->ops.config_collision_dist(hw);
1607
1608
1609
1610
1611
1612
1613 ret_val = e1000e_config_fc_after_link_up(hw);
1614 if (ret_val)
1615 e_dbg("Error configuring flow control\n");
1616
1617 return ret_val;
1618}
1619
1620static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1621{
1622 struct e1000_hw *hw = &adapter->hw;
1623 s32 rc;
1624
1625 rc = e1000_init_mac_params_ich8lan(hw);
1626 if (rc)
1627 return rc;
1628
1629 rc = e1000_init_nvm_params_ich8lan(hw);
1630 if (rc)
1631 return rc;
1632
1633 switch (hw->mac.type) {
1634 case e1000_ich8lan:
1635 case e1000_ich9lan:
1636 case e1000_ich10lan:
1637 rc = e1000_init_phy_params_ich8lan(hw);
1638 break;
1639 case e1000_pchlan:
1640 case e1000_pch2lan:
1641 case e1000_pch_lpt:
1642 case e1000_pch_spt:
1643 rc = e1000_init_phy_params_pchlan(hw);
1644 break;
1645 default:
1646 break;
1647 }
1648 if (rc)
1649 return rc;
1650
1651
1652
1653
1654 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1655 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1656 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1657 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1658 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1659
1660 hw->mac.ops.blink_led = NULL;
1661 }
1662
1663 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1664 (adapter->hw.phy.type != e1000_phy_ife))
1665 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1666
1667
1668 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1669 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1670 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1671
1672 return 0;
1673}
1674
1675static DEFINE_MUTEX(nvm_mutex);
1676
1677
1678
1679
1680
1681
1682
1683static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1684{
1685 mutex_lock(&nvm_mutex);
1686
1687 return 0;
1688}
1689
1690
1691
1692
1693
1694
1695
1696static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1697{
1698 mutex_unlock(&nvm_mutex);
1699}
1700
1701
1702
1703
1704
1705
1706
1707
1708static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1709{
1710 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1711 s32 ret_val = 0;
1712
1713 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1714 &hw->adapter->state)) {
1715 e_dbg("contention for Phy access\n");
1716 return -E1000_ERR_PHY;
1717 }
1718
1719 while (timeout) {
1720 extcnf_ctrl = er32(EXTCNF_CTRL);
1721 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1722 break;
1723
1724 mdelay(1);
1725 timeout--;
1726 }
1727
1728 if (!timeout) {
1729 e_dbg("SW has already locked the resource.\n");
1730 ret_val = -E1000_ERR_CONFIG;
1731 goto out;
1732 }
1733
1734 timeout = SW_FLAG_TIMEOUT;
1735
1736 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1737 ew32(EXTCNF_CTRL, extcnf_ctrl);
1738
1739 while (timeout) {
1740 extcnf_ctrl = er32(EXTCNF_CTRL);
1741 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1742 break;
1743
1744 mdelay(1);
1745 timeout--;
1746 }
1747
1748 if (!timeout) {
1749 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1750 er32(FWSM), extcnf_ctrl);
1751 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1752 ew32(EXTCNF_CTRL, extcnf_ctrl);
1753 ret_val = -E1000_ERR_CONFIG;
1754 goto out;
1755 }
1756
1757out:
1758 if (ret_val)
1759 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1760
1761 return ret_val;
1762}
1763
1764
1765
1766
1767
1768
1769
1770
1771static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1772{
1773 u32 extcnf_ctrl;
1774
1775 extcnf_ctrl = er32(EXTCNF_CTRL);
1776
1777 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1778 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1779 ew32(EXTCNF_CTRL, extcnf_ctrl);
1780 } else {
1781 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1782 }
1783
1784 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1785}
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1796{
1797 u32 fwsm;
1798
1799 fwsm = er32(FWSM);
1800 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1801 ((fwsm & E1000_FWSM_MODE_MASK) ==
1802 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1803}
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1814{
1815 u32 fwsm;
1816
1817 fwsm = er32(FWSM);
1818 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1819 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1820}
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1834{
1835 u32 rar_low, rar_high;
1836
1837
1838
1839
1840 rar_low = ((u32)addr[0] |
1841 ((u32)addr[1] << 8) |
1842 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1843
1844 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1845
1846
1847 if (rar_low || rar_high)
1848 rar_high |= E1000_RAH_AV;
1849
1850 if (index == 0) {
1851 ew32(RAL(index), rar_low);
1852 e1e_flush();
1853 ew32(RAH(index), rar_high);
1854 e1e_flush();
1855 return 0;
1856 }
1857
1858
1859
1860
1861 if (index < (u32)(hw->mac.rar_entry_count)) {
1862 s32 ret_val;
1863
1864 ret_val = e1000_acquire_swflag_ich8lan(hw);
1865 if (ret_val)
1866 goto out;
1867
1868 ew32(SHRAL(index - 1), rar_low);
1869 e1e_flush();
1870 ew32(SHRAH(index - 1), rar_high);
1871 e1e_flush();
1872
1873 e1000_release_swflag_ich8lan(hw);
1874
1875
1876 if ((er32(SHRAL(index - 1)) == rar_low) &&
1877 (er32(SHRAH(index - 1)) == rar_high))
1878 return 0;
1879
1880 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1881 (index - 1), er32(FWSM));
1882 }
1883
1884out:
1885 e_dbg("Failed to write receive address at index %d\n", index);
1886 return -E1000_ERR_CONFIG;
1887}
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1900{
1901 u32 wlock_mac;
1902 u32 num_entries;
1903
1904 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1905 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1906
1907 switch (wlock_mac) {
1908 case 0:
1909
1910 num_entries = hw->mac.rar_entry_count;
1911 break;
1912 case 1:
1913
1914 num_entries = 1;
1915 break;
1916 default:
1917
1918 num_entries = wlock_mac + 1;
1919 break;
1920 }
1921
1922 return num_entries;
1923}
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1937{
1938 u32 rar_low, rar_high;
1939 u32 wlock_mac;
1940
1941
1942
1943
1944 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1945 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1946
1947 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1948
1949
1950 if (rar_low || rar_high)
1951 rar_high |= E1000_RAH_AV;
1952
1953 if (index == 0) {
1954 ew32(RAL(index), rar_low);
1955 e1e_flush();
1956 ew32(RAH(index), rar_high);
1957 e1e_flush();
1958 return 0;
1959 }
1960
1961
1962
1963
1964 if (index < hw->mac.rar_entry_count) {
1965 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1966 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1967
1968
1969 if (wlock_mac == 1)
1970 goto out;
1971
1972 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1973 s32 ret_val;
1974
1975 ret_val = e1000_acquire_swflag_ich8lan(hw);
1976
1977 if (ret_val)
1978 goto out;
1979
1980 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1981 e1e_flush();
1982 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1983 e1e_flush();
1984
1985 e1000_release_swflag_ich8lan(hw);
1986
1987
1988 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1989 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1990 return 0;
1991 }
1992 }
1993
1994out:
1995 e_dbg("Failed to write receive address at index %d\n", index);
1996 return -E1000_ERR_CONFIG;
1997}
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2008{
2009 bool blocked = false;
2010 int i = 0;
2011
2012 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2013 (i++ < 30))
2014 usleep_range(10000, 20000);
2015 return blocked ? E1000_BLK_PHY_RESET : 0;
2016}
2017
2018
2019
2020
2021
2022
2023
2024
2025static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2026{
2027 u16 phy_data;
2028 u32 strap = er32(STRAP);
2029 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2030 E1000_STRAP_SMT_FREQ_SHIFT;
2031 s32 ret_val;
2032
2033 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2034
2035 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2036 if (ret_val)
2037 return ret_val;
2038
2039 phy_data &= ~HV_SMB_ADDR_MASK;
2040 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2041 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2042
2043 if (hw->phy.type == e1000_phy_i217) {
2044
2045 if (freq--) {
2046 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2047 phy_data |= (freq & BIT(0)) <<
2048 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2049 phy_data |= (freq & BIT(1)) <<
2050 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2051 } else {
2052 e_dbg("Unsupported SMB frequency in PHY\n");
2053 }
2054 }
2055
2056 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2057}
2058
2059
2060
2061
2062
2063
2064
2065
2066static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2067{
2068 struct e1000_phy_info *phy = &hw->phy;
2069 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2070 s32 ret_val = 0;
2071 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2072
2073
2074
2075
2076
2077
2078
2079 switch (hw->mac.type) {
2080 case e1000_ich8lan:
2081 if (phy->type != e1000_phy_igp_3)
2082 return ret_val;
2083
2084 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2085 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2086 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2087 break;
2088 }
2089
2090 case e1000_pchlan:
2091 case e1000_pch2lan:
2092 case e1000_pch_lpt:
2093 case e1000_pch_spt:
2094 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2095 break;
2096 default:
2097 return ret_val;
2098 }
2099
2100 ret_val = hw->phy.ops.acquire(hw);
2101 if (ret_val)
2102 return ret_val;
2103
2104 data = er32(FEXTNVM);
2105 if (!(data & sw_cfg_mask))
2106 goto release;
2107
2108
2109
2110
2111 data = er32(EXTCNF_CTRL);
2112 if ((hw->mac.type < e1000_pch2lan) &&
2113 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2114 goto release;
2115
2116 cnf_size = er32(EXTCNF_SIZE);
2117 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2118 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2119 if (!cnf_size)
2120 goto release;
2121
2122 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2123 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2124
2125 if (((hw->mac.type == e1000_pchlan) &&
2126 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2127 (hw->mac.type > e1000_pchlan)) {
2128
2129
2130
2131
2132
2133 ret_val = e1000_write_smbus_addr(hw);
2134 if (ret_val)
2135 goto release;
2136
2137 data = er32(LEDCTL);
2138 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2139 (u16)data);
2140 if (ret_val)
2141 goto release;
2142 }
2143
2144
2145
2146
2147 word_addr = (u16)(cnf_base_addr << 1);
2148
2149 for (i = 0; i < cnf_size; i++) {
2150 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data);
2151 if (ret_val)
2152 goto release;
2153
2154 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2155 1, ®_addr);
2156 if (ret_val)
2157 goto release;
2158
2159
2160 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2161 phy_page = reg_data;
2162 continue;
2163 }
2164
2165 reg_addr &= PHY_REG_MASK;
2166 reg_addr |= phy_page;
2167
2168 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2169 if (ret_val)
2170 goto release;
2171 }
2172
2173release:
2174 hw->phy.ops.release(hw);
2175 return ret_val;
2176}
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2189{
2190 s32 ret_val = 0;
2191 u16 status_reg = 0;
2192 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2193
2194 if (hw->mac.type != e1000_pchlan)
2195 return 0;
2196
2197
2198 ret_val = hw->phy.ops.acquire(hw);
2199 if (ret_val)
2200 return ret_val;
2201
2202
2203 if (link) {
2204 if (hw->phy.type == e1000_phy_82578) {
2205 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2206 &status_reg);
2207 if (ret_val)
2208 goto release;
2209
2210 status_reg &= (BM_CS_STATUS_LINK_UP |
2211 BM_CS_STATUS_RESOLVED |
2212 BM_CS_STATUS_SPEED_MASK);
2213
2214 if (status_reg == (BM_CS_STATUS_LINK_UP |
2215 BM_CS_STATUS_RESOLVED |
2216 BM_CS_STATUS_SPEED_1000))
2217 k1_enable = false;
2218 }
2219
2220 if (hw->phy.type == e1000_phy_82577) {
2221 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2222 if (ret_val)
2223 goto release;
2224
2225 status_reg &= (HV_M_STATUS_LINK_UP |
2226 HV_M_STATUS_AUTONEG_COMPLETE |
2227 HV_M_STATUS_SPEED_MASK);
2228
2229 if (status_reg == (HV_M_STATUS_LINK_UP |
2230 HV_M_STATUS_AUTONEG_COMPLETE |
2231 HV_M_STATUS_SPEED_1000))
2232 k1_enable = false;
2233 }
2234
2235
2236 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2237 if (ret_val)
2238 goto release;
2239
2240 } else {
2241
2242 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2243 if (ret_val)
2244 goto release;
2245 }
2246
2247 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2248
2249release:
2250 hw->phy.ops.release(hw);
2251
2252 return ret_val;
2253}
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2266{
2267 s32 ret_val;
2268 u32 ctrl_reg = 0;
2269 u32 ctrl_ext = 0;
2270 u32 reg = 0;
2271 u16 kmrn_reg = 0;
2272
2273 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2274 &kmrn_reg);
2275 if (ret_val)
2276 return ret_val;
2277
2278 if (k1_enable)
2279 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2280 else
2281 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2282
2283 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2284 kmrn_reg);
2285 if (ret_val)
2286 return ret_val;
2287
2288 usleep_range(20, 40);
2289 ctrl_ext = er32(CTRL_EXT);
2290 ctrl_reg = er32(CTRL);
2291
2292 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2293 reg |= E1000_CTRL_FRCSPD;
2294 ew32(CTRL, reg);
2295
2296 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2297 e1e_flush();
2298 usleep_range(20, 40);
2299 ew32(CTRL, ctrl_reg);
2300 ew32(CTRL_EXT, ctrl_ext);
2301 e1e_flush();
2302 usleep_range(20, 40);
2303
2304 return 0;
2305}
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2317{
2318 s32 ret_val = 0;
2319 u32 mac_reg;
2320 u16 oem_reg;
2321
2322 if (hw->mac.type < e1000_pchlan)
2323 return ret_val;
2324
2325 ret_val = hw->phy.ops.acquire(hw);
2326 if (ret_val)
2327 return ret_val;
2328
2329 if (hw->mac.type == e1000_pchlan) {
2330 mac_reg = er32(EXTCNF_CTRL);
2331 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2332 goto release;
2333 }
2334
2335 mac_reg = er32(FEXTNVM);
2336 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2337 goto release;
2338
2339 mac_reg = er32(PHY_CTRL);
2340
2341 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2342 if (ret_val)
2343 goto release;
2344
2345 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2346
2347 if (d0_state) {
2348 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2349 oem_reg |= HV_OEM_BITS_GBE_DIS;
2350
2351 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2352 oem_reg |= HV_OEM_BITS_LPLU;
2353 } else {
2354 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2355 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2356 oem_reg |= HV_OEM_BITS_GBE_DIS;
2357
2358 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2359 E1000_PHY_CTRL_NOND0A_LPLU))
2360 oem_reg |= HV_OEM_BITS_LPLU;
2361 }
2362
2363
2364 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2365 !hw->phy.ops.check_reset_block(hw))
2366 oem_reg |= HV_OEM_BITS_RESTART_AN;
2367
2368 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2369
2370release:
2371 hw->phy.ops.release(hw);
2372
2373 return ret_val;
2374}
2375
2376
2377
2378
2379
2380static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2381{
2382 s32 ret_val;
2383 u16 data;
2384
2385 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2386 if (ret_val)
2387 return ret_val;
2388
2389 data |= HV_KMRN_MDIO_SLOW;
2390
2391 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2392
2393 return ret_val;
2394}
2395
2396
2397
2398
2399
2400static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2401{
2402 s32 ret_val = 0;
2403 u16 phy_data;
2404
2405 if (hw->mac.type != e1000_pchlan)
2406 return 0;
2407
2408
2409 if (hw->phy.type == e1000_phy_82577) {
2410 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2411 if (ret_val)
2412 return ret_val;
2413 }
2414
2415 if (((hw->phy.type == e1000_phy_82577) &&
2416 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2417 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2418
2419 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2420 if (ret_val)
2421 return ret_val;
2422
2423
2424 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2425 if (ret_val)
2426 return ret_val;
2427 }
2428
2429 if (hw->phy.type == e1000_phy_82578) {
2430
2431
2432
2433 if (hw->phy.revision < 2) {
2434 e1000e_phy_sw_reset(hw);
2435 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2436 }
2437 }
2438
2439
2440 ret_val = hw->phy.ops.acquire(hw);
2441 if (ret_val)
2442 return ret_val;
2443
2444 hw->phy.addr = 1;
2445 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2446 hw->phy.ops.release(hw);
2447 if (ret_val)
2448 return ret_val;
2449
2450
2451
2452
2453 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2454 if (ret_val)
2455 return ret_val;
2456
2457
2458 ret_val = hw->phy.ops.acquire(hw);
2459 if (ret_val)
2460 return ret_val;
2461 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2462 if (ret_val)
2463 goto release;
2464 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2465 if (ret_val)
2466 goto release;
2467
2468
2469 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2470release:
2471 hw->phy.ops.release(hw);
2472
2473 return ret_val;
2474}
2475
2476
2477
2478
2479
2480void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2481{
2482 u32 mac_reg;
2483 u16 i, phy_reg = 0;
2484 s32 ret_val;
2485
2486 ret_val = hw->phy.ops.acquire(hw);
2487 if (ret_val)
2488 return;
2489 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2490 if (ret_val)
2491 goto release;
2492
2493
2494 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2495 mac_reg = er32(RAL(i));
2496 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2497 (u16)(mac_reg & 0xFFFF));
2498 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2499 (u16)((mac_reg >> 16) & 0xFFFF));
2500
2501 mac_reg = er32(RAH(i));
2502 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2503 (u16)(mac_reg & 0xFFFF));
2504 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2505 (u16)((mac_reg & E1000_RAH_AV)
2506 >> 16));
2507 }
2508
2509 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2510
2511release:
2512 hw->phy.ops.release(hw);
2513}
2514
2515
2516
2517
2518
2519
2520
2521s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2522{
2523 s32 ret_val = 0;
2524 u16 phy_reg, data;
2525 u32 mac_reg;
2526 u16 i;
2527
2528 if (hw->mac.type < e1000_pch2lan)
2529 return 0;
2530
2531
2532 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2533 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2534 if (ret_val)
2535 return ret_val;
2536
2537 if (enable) {
2538
2539
2540
2541 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2542 u8 mac_addr[ETH_ALEN] = { 0 };
2543 u32 addr_high, addr_low;
2544
2545 addr_high = er32(RAH(i));
2546 if (!(addr_high & E1000_RAH_AV))
2547 continue;
2548 addr_low = er32(RAL(i));
2549 mac_addr[0] = (addr_low & 0xFF);
2550 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2551 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2552 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2553 mac_addr[4] = (addr_high & 0xFF);
2554 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2555
2556 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2557 }
2558
2559
2560 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2561
2562
2563 mac_reg = er32(FFLT_DBG);
2564 mac_reg &= ~BIT(14);
2565 mac_reg |= (7 << 15);
2566 ew32(FFLT_DBG, mac_reg);
2567
2568 mac_reg = er32(RCTL);
2569 mac_reg |= E1000_RCTL_SECRC;
2570 ew32(RCTL, mac_reg);
2571
2572 ret_val = e1000e_read_kmrn_reg(hw,
2573 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2574 &data);
2575 if (ret_val)
2576 return ret_val;
2577 ret_val = e1000e_write_kmrn_reg(hw,
2578 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2579 data | BIT(0));
2580 if (ret_val)
2581 return ret_val;
2582 ret_val = e1000e_read_kmrn_reg(hw,
2583 E1000_KMRNCTRLSTA_HD_CTRL,
2584 &data);
2585 if (ret_val)
2586 return ret_val;
2587 data &= ~(0xF << 8);
2588 data |= (0xB << 8);
2589 ret_val = e1000e_write_kmrn_reg(hw,
2590 E1000_KMRNCTRLSTA_HD_CTRL,
2591 data);
2592 if (ret_val)
2593 return ret_val;
2594
2595
2596 e1e_rphy(hw, PHY_REG(769, 23), &data);
2597 data &= ~(0x7F << 5);
2598 data |= (0x37 << 5);
2599 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2600 if (ret_val)
2601 return ret_val;
2602 e1e_rphy(hw, PHY_REG(769, 16), &data);
2603 data &= ~BIT(13);
2604 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2605 if (ret_val)
2606 return ret_val;
2607 e1e_rphy(hw, PHY_REG(776, 20), &data);
2608 data &= ~(0x3FF << 2);
2609 data |= (E1000_TX_PTR_GAP << 2);
2610 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2611 if (ret_val)
2612 return ret_val;
2613 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2614 if (ret_val)
2615 return ret_val;
2616 e1e_rphy(hw, HV_PM_CTRL, &data);
2617 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2618 if (ret_val)
2619 return ret_val;
2620 } else {
2621
2622 mac_reg = er32(FFLT_DBG);
2623 mac_reg &= ~(0xF << 14);
2624 ew32(FFLT_DBG, mac_reg);
2625
2626 mac_reg = er32(RCTL);
2627 mac_reg &= ~E1000_RCTL_SECRC;
2628 ew32(RCTL, mac_reg);
2629
2630 ret_val = e1000e_read_kmrn_reg(hw,
2631 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2632 &data);
2633 if (ret_val)
2634 return ret_val;
2635 ret_val = e1000e_write_kmrn_reg(hw,
2636 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2637 data & ~BIT(0));
2638 if (ret_val)
2639 return ret_val;
2640 ret_val = e1000e_read_kmrn_reg(hw,
2641 E1000_KMRNCTRLSTA_HD_CTRL,
2642 &data);
2643 if (ret_val)
2644 return ret_val;
2645 data &= ~(0xF << 8);
2646 data |= (0xB << 8);
2647 ret_val = e1000e_write_kmrn_reg(hw,
2648 E1000_KMRNCTRLSTA_HD_CTRL,
2649 data);
2650 if (ret_val)
2651 return ret_val;
2652
2653
2654 e1e_rphy(hw, PHY_REG(769, 23), &data);
2655 data &= ~(0x7F << 5);
2656 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2657 if (ret_val)
2658 return ret_val;
2659 e1e_rphy(hw, PHY_REG(769, 16), &data);
2660 data |= BIT(13);
2661 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2662 if (ret_val)
2663 return ret_val;
2664 e1e_rphy(hw, PHY_REG(776, 20), &data);
2665 data &= ~(0x3FF << 2);
2666 data |= (0x8 << 2);
2667 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2668 if (ret_val)
2669 return ret_val;
2670 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2671 if (ret_val)
2672 return ret_val;
2673 e1e_rphy(hw, HV_PM_CTRL, &data);
2674 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2675 if (ret_val)
2676 return ret_val;
2677 }
2678
2679
2680 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2681}
2682
2683
2684
2685
2686
2687static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2688{
2689 s32 ret_val = 0;
2690
2691 if (hw->mac.type != e1000_pch2lan)
2692 return 0;
2693
2694
2695 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2696 if (ret_val)
2697 return ret_val;
2698
2699 ret_val = hw->phy.ops.acquire(hw);
2700 if (ret_val)
2701 return ret_val;
2702
2703 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2704 if (ret_val)
2705 goto release;
2706
2707 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2708release:
2709 hw->phy.ops.release(hw);
2710
2711 return ret_val;
2712}
2713
2714
2715
2716
2717
2718
2719
2720
2721static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2722{
2723 s32 ret_val = 0;
2724 u16 status_reg = 0;
2725
2726 if (hw->mac.type != e1000_pch2lan)
2727 return 0;
2728
2729
2730 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2731 if (ret_val)
2732 return ret_val;
2733
2734 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2735 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2736 if (status_reg &
2737 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2738 u16 pm_phy_reg;
2739
2740
2741 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2742 if (ret_val)
2743 return ret_val;
2744 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2745 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2746 if (ret_val)
2747 return ret_val;
2748 } else {
2749 u32 mac_reg;
2750
2751 mac_reg = er32(FEXTNVM4);
2752 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2753 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2754 ew32(FEXTNVM4, mac_reg);
2755 }
2756 }
2757
2758 return ret_val;
2759}
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2770{
2771 u32 extcnf_ctrl;
2772
2773 if (hw->mac.type < e1000_pch2lan)
2774 return;
2775
2776 extcnf_ctrl = er32(EXTCNF_CTRL);
2777
2778 if (gate)
2779 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2780 else
2781 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2782
2783 ew32(EXTCNF_CTRL, extcnf_ctrl);
2784}
2785
2786
2787
2788
2789
2790
2791
2792
2793static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2794{
2795 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2796
2797
2798 do {
2799 data = er32(STATUS);
2800 data &= E1000_STATUS_LAN_INIT_DONE;
2801 usleep_range(100, 200);
2802 } while ((!data) && --loop);
2803
2804
2805
2806
2807
2808 if (loop == 0)
2809 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2810
2811
2812 data = er32(STATUS);
2813 data &= ~E1000_STATUS_LAN_INIT_DONE;
2814 ew32(STATUS, data);
2815}
2816
2817
2818
2819
2820
2821static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2822{
2823 s32 ret_val = 0;
2824 u16 reg;
2825
2826 if (hw->phy.ops.check_reset_block(hw))
2827 return 0;
2828
2829
2830 usleep_range(10000, 20000);
2831
2832
2833 switch (hw->mac.type) {
2834 case e1000_pchlan:
2835 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2836 if (ret_val)
2837 return ret_val;
2838 break;
2839 case e1000_pch2lan:
2840 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2841 if (ret_val)
2842 return ret_val;
2843 break;
2844 default:
2845 break;
2846 }
2847
2848
2849 if (hw->mac.type >= e1000_pchlan) {
2850 e1e_rphy(hw, BM_PORT_GEN_CFG, ®);
2851 reg &= ~BM_WUC_HOST_WU_BIT;
2852 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2853 }
2854
2855
2856 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2857 if (ret_val)
2858 return ret_val;
2859
2860
2861 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2862
2863 if (hw->mac.type == e1000_pch2lan) {
2864
2865 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2866 usleep_range(10000, 20000);
2867 e1000_gate_hw_phy_config_ich8lan(hw, false);
2868 }
2869
2870
2871 ret_val = hw->phy.ops.acquire(hw);
2872 if (ret_val)
2873 return ret_val;
2874 ret_val = e1000_write_emi_reg_locked(hw,
2875 I82579_LPI_UPDATE_TIMER,
2876 0x1387);
2877 hw->phy.ops.release(hw);
2878 }
2879
2880 return ret_val;
2881}
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2892{
2893 s32 ret_val = 0;
2894
2895
2896 if ((hw->mac.type == e1000_pch2lan) &&
2897 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2898 e1000_gate_hw_phy_config_ich8lan(hw, true);
2899
2900 ret_val = e1000e_phy_hw_reset_generic(hw);
2901 if (ret_val)
2902 return ret_val;
2903
2904 return e1000_post_phy_reset_ich8lan(hw);
2905}
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2919{
2920 s32 ret_val;
2921 u16 oem_reg;
2922
2923 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2924 if (ret_val)
2925 return ret_val;
2926
2927 if (active)
2928 oem_reg |= HV_OEM_BITS_LPLU;
2929 else
2930 oem_reg &= ~HV_OEM_BITS_LPLU;
2931
2932 if (!hw->phy.ops.check_reset_block(hw))
2933 oem_reg |= HV_OEM_BITS_RESTART_AN;
2934
2935 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2936}
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2952{
2953 struct e1000_phy_info *phy = &hw->phy;
2954 u32 phy_ctrl;
2955 s32 ret_val = 0;
2956 u16 data;
2957
2958 if (phy->type == e1000_phy_ife)
2959 return 0;
2960
2961 phy_ctrl = er32(PHY_CTRL);
2962
2963 if (active) {
2964 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2965 ew32(PHY_CTRL, phy_ctrl);
2966
2967 if (phy->type != e1000_phy_igp_3)
2968 return 0;
2969
2970
2971
2972
2973 if (hw->mac.type == e1000_ich8lan)
2974 e1000e_gig_downshift_workaround_ich8lan(hw);
2975
2976
2977 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2978 if (ret_val)
2979 return ret_val;
2980 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2981 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2982 if (ret_val)
2983 return ret_val;
2984 } else {
2985 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2986 ew32(PHY_CTRL, phy_ctrl);
2987
2988 if (phy->type != e1000_phy_igp_3)
2989 return 0;
2990
2991
2992
2993
2994
2995
2996 if (phy->smart_speed == e1000_smart_speed_on) {
2997 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2998 &data);
2999 if (ret_val)
3000 return ret_val;
3001
3002 data |= IGP01E1000_PSCFR_SMART_SPEED;
3003 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3004 data);
3005 if (ret_val)
3006 return ret_val;
3007 } else if (phy->smart_speed == e1000_smart_speed_off) {
3008 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3009 &data);
3010 if (ret_val)
3011 return ret_val;
3012
3013 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3014 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3015 data);
3016 if (ret_val)
3017 return ret_val;
3018 }
3019 }
3020
3021 return 0;
3022}
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3038{
3039 struct e1000_phy_info *phy = &hw->phy;
3040 u32 phy_ctrl;
3041 s32 ret_val = 0;
3042 u16 data;
3043
3044 phy_ctrl = er32(PHY_CTRL);
3045
3046 if (!active) {
3047 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3048 ew32(PHY_CTRL, phy_ctrl);
3049
3050 if (phy->type != e1000_phy_igp_3)
3051 return 0;
3052
3053
3054
3055
3056
3057
3058 if (phy->smart_speed == e1000_smart_speed_on) {
3059 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3060 &data);
3061 if (ret_val)
3062 return ret_val;
3063
3064 data |= IGP01E1000_PSCFR_SMART_SPEED;
3065 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3066 data);
3067 if (ret_val)
3068 return ret_val;
3069 } else if (phy->smart_speed == e1000_smart_speed_off) {
3070 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3071 &data);
3072 if (ret_val)
3073 return ret_val;
3074
3075 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3076 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3077 data);
3078 if (ret_val)
3079 return ret_val;
3080 }
3081 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3082 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3083 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3084 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3085 ew32(PHY_CTRL, phy_ctrl);
3086
3087 if (phy->type != e1000_phy_igp_3)
3088 return 0;
3089
3090
3091
3092
3093 if (hw->mac.type == e1000_ich8lan)
3094 e1000e_gig_downshift_workaround_ich8lan(hw);
3095
3096
3097 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3098 if (ret_val)
3099 return ret_val;
3100
3101 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3102 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3103 }
3104
3105 return ret_val;
3106}
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3117{
3118 u32 eecd;
3119 struct e1000_nvm_info *nvm = &hw->nvm;
3120 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3121 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3122 u32 nvm_dword = 0;
3123 u8 sig_byte = 0;
3124 s32 ret_val;
3125
3126 switch (hw->mac.type) {
3127 case e1000_pch_spt:
3128 bank1_offset = nvm->flash_bank_size;
3129 act_offset = E1000_ICH_NVM_SIG_WORD;
3130
3131
3132 *bank = 0;
3133
3134
3135 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3136 &nvm_dword);
3137 if (ret_val)
3138 return ret_val;
3139 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3140 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3141 E1000_ICH_NVM_SIG_VALUE) {
3142 *bank = 0;
3143 return 0;
3144 }
3145
3146
3147 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3148 bank1_offset,
3149 &nvm_dword);
3150 if (ret_val)
3151 return ret_val;
3152 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3153 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3154 E1000_ICH_NVM_SIG_VALUE) {
3155 *bank = 1;
3156 return 0;
3157 }
3158
3159 e_dbg("ERROR: No valid NVM bank present\n");
3160 return -E1000_ERR_NVM;
3161 case e1000_ich8lan:
3162 case e1000_ich9lan:
3163 eecd = er32(EECD);
3164 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3165 E1000_EECD_SEC1VAL_VALID_MASK) {
3166 if (eecd & E1000_EECD_SEC1VAL)
3167 *bank = 1;
3168 else
3169 *bank = 0;
3170
3171 return 0;
3172 }
3173 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3174
3175 default:
3176
3177 *bank = 0;
3178
3179
3180 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3181 &sig_byte);
3182 if (ret_val)
3183 return ret_val;
3184 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3185 E1000_ICH_NVM_SIG_VALUE) {
3186 *bank = 0;
3187 return 0;
3188 }
3189
3190
3191 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3192 bank1_offset,
3193 &sig_byte);
3194 if (ret_val)
3195 return ret_val;
3196 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3197 E1000_ICH_NVM_SIG_VALUE) {
3198 *bank = 1;
3199 return 0;
3200 }
3201
3202 e_dbg("ERROR: No valid NVM bank present\n");
3203 return -E1000_ERR_NVM;
3204 }
3205}
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3217 u16 *data)
3218{
3219 struct e1000_nvm_info *nvm = &hw->nvm;
3220 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3221 u32 act_offset;
3222 s32 ret_val = 0;
3223 u32 bank = 0;
3224 u32 dword = 0;
3225 u16 offset_to_read;
3226 u16 i;
3227
3228 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3229 (words == 0)) {
3230 e_dbg("nvm parameter(s) out of bounds\n");
3231 ret_val = -E1000_ERR_NVM;
3232 goto out;
3233 }
3234
3235 nvm->ops.acquire(hw);
3236
3237 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3238 if (ret_val) {
3239 e_dbg("Could not detect valid bank, assuming bank 0\n");
3240 bank = 0;
3241 }
3242
3243 act_offset = (bank) ? nvm->flash_bank_size : 0;
3244 act_offset += offset;
3245
3246 ret_val = 0;
3247
3248 for (i = 0; i < words; i += 2) {
3249 if (words - i == 1) {
3250 if (dev_spec->shadow_ram[offset + i].modified) {
3251 data[i] =
3252 dev_spec->shadow_ram[offset + i].value;
3253 } else {
3254 offset_to_read = act_offset + i -
3255 ((act_offset + i) % 2);
3256 ret_val =
3257 e1000_read_flash_dword_ich8lan(hw,
3258 offset_to_read,
3259 &dword);
3260 if (ret_val)
3261 break;
3262 if ((act_offset + i) % 2 == 0)
3263 data[i] = (u16)(dword & 0xFFFF);
3264 else
3265 data[i] = (u16)((dword >> 16) & 0xFFFF);
3266 }
3267 } else {
3268 offset_to_read = act_offset + i;
3269 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3270 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3271 ret_val =
3272 e1000_read_flash_dword_ich8lan(hw,
3273 offset_to_read,
3274 &dword);
3275 if (ret_val)
3276 break;
3277 }
3278 if (dev_spec->shadow_ram[offset + i].modified)
3279 data[i] =
3280 dev_spec->shadow_ram[offset + i].value;
3281 else
3282 data[i] = (u16)(dword & 0xFFFF);
3283 if (dev_spec->shadow_ram[offset + i].modified)
3284 data[i + 1] =
3285 dev_spec->shadow_ram[offset + i + 1].value;
3286 else
3287 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3288 }
3289 }
3290
3291 nvm->ops.release(hw);
3292
3293out:
3294 if (ret_val)
3295 e_dbg("NVM read error: %d\n", ret_val);
3296
3297 return ret_val;
3298}
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3310 u16 *data)
3311{
3312 struct e1000_nvm_info *nvm = &hw->nvm;
3313 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3314 u32 act_offset;
3315 s32 ret_val = 0;
3316 u32 bank = 0;
3317 u16 i, word;
3318
3319 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3320 (words == 0)) {
3321 e_dbg("nvm parameter(s) out of bounds\n");
3322 ret_val = -E1000_ERR_NVM;
3323 goto out;
3324 }
3325
3326 nvm->ops.acquire(hw);
3327
3328 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3329 if (ret_val) {
3330 e_dbg("Could not detect valid bank, assuming bank 0\n");
3331 bank = 0;
3332 }
3333
3334 act_offset = (bank) ? nvm->flash_bank_size : 0;
3335 act_offset += offset;
3336
3337 ret_val = 0;
3338 for (i = 0; i < words; i++) {
3339 if (dev_spec->shadow_ram[offset + i].modified) {
3340 data[i] = dev_spec->shadow_ram[offset + i].value;
3341 } else {
3342 ret_val = e1000_read_flash_word_ich8lan(hw,
3343 act_offset + i,
3344 &word);
3345 if (ret_val)
3346 break;
3347 data[i] = word;
3348 }
3349 }
3350
3351 nvm->ops.release(hw);
3352
3353out:
3354 if (ret_val)
3355 e_dbg("NVM read error: %d\n", ret_val);
3356
3357 return ret_val;
3358}
3359
3360
3361
3362
3363
3364
3365
3366
3367static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3368{
3369 union ich8_hws_flash_status hsfsts;
3370 s32 ret_val = -E1000_ERR_NVM;
3371
3372 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3373
3374
3375 if (!hsfsts.hsf_status.fldesvalid) {
3376 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3377 return -E1000_ERR_NVM;
3378 }
3379
3380
3381 hsfsts.hsf_status.flcerr = 1;
3382 hsfsts.hsf_status.dael = 1;
3383 if (hw->mac.type == e1000_pch_spt)
3384 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3385 else
3386 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396 if (!hsfsts.hsf_status.flcinprog) {
3397
3398
3399
3400
3401 hsfsts.hsf_status.flcdone = 1;
3402 if (hw->mac.type == e1000_pch_spt)
3403 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3404 else
3405 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3406 ret_val = 0;
3407 } else {
3408 s32 i;
3409
3410
3411
3412
3413 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3414 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3415 if (!hsfsts.hsf_status.flcinprog) {
3416 ret_val = 0;
3417 break;
3418 }
3419 udelay(1);
3420 }
3421 if (!ret_val) {
3422
3423
3424
3425 hsfsts.hsf_status.flcdone = 1;
3426 if (hw->mac.type == e1000_pch_spt)
3427 ew32flash(ICH_FLASH_HSFSTS,
3428 hsfsts.regval & 0xFFFF);
3429 else
3430 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3431 } else {
3432 e_dbg("Flash controller busy, cannot get access\n");
3433 }
3434 }
3435
3436 return ret_val;
3437}
3438
3439
3440
3441
3442
3443
3444
3445
3446static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3447{
3448 union ich8_hws_flash_ctrl hsflctl;
3449 union ich8_hws_flash_status hsfsts;
3450 u32 i = 0;
3451
3452
3453 if (hw->mac.type == e1000_pch_spt)
3454 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3455 else
3456 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3457 hsflctl.hsf_ctrl.flcgo = 1;
3458
3459 if (hw->mac.type == e1000_pch_spt)
3460 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3461 else
3462 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3463
3464
3465 do {
3466 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3467 if (hsfsts.hsf_status.flcdone)
3468 break;
3469 udelay(1);
3470 } while (i++ < timeout);
3471
3472 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3473 return 0;
3474
3475 return -E1000_ERR_NVM;
3476}
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3488 u32 *data)
3489{
3490
3491 offset <<= 1;
3492 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3493}
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3505 u16 *data)
3506{
3507
3508 offset <<= 1;
3509
3510 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3511}
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3522 u8 *data)
3523{
3524 s32 ret_val;
3525 u16 word = 0;
3526
3527
3528
3529
3530 if (hw->mac.type == e1000_pch_spt)
3531 return -E1000_ERR_NVM;
3532 else
3533 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3534
3535 if (ret_val)
3536 return ret_val;
3537
3538 *data = (u8)word;
3539
3540 return 0;
3541}
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3553 u8 size, u16 *data)
3554{
3555 union ich8_hws_flash_status hsfsts;
3556 union ich8_hws_flash_ctrl hsflctl;
3557 u32 flash_linear_addr;
3558 u32 flash_data = 0;
3559 s32 ret_val = -E1000_ERR_NVM;
3560 u8 count = 0;
3561
3562 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3563 return -E1000_ERR_NVM;
3564
3565 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3566 hw->nvm.flash_base_addr);
3567
3568 do {
3569 udelay(1);
3570
3571 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3572 if (ret_val)
3573 break;
3574
3575 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3576
3577 hsflctl.hsf_ctrl.fldbcount = size - 1;
3578 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3579 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3580
3581 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3582
3583 ret_val =
3584 e1000_flash_cycle_ich8lan(hw,
3585 ICH_FLASH_READ_COMMAND_TIMEOUT);
3586
3587
3588
3589
3590
3591
3592 if (!ret_val) {
3593 flash_data = er32flash(ICH_FLASH_FDATA0);
3594 if (size == 1)
3595 *data = (u8)(flash_data & 0x000000FF);
3596 else if (size == 2)
3597 *data = (u16)(flash_data & 0x0000FFFF);
3598 break;
3599 } else {
3600
3601
3602
3603
3604
3605 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3606 if (hsfsts.hsf_status.flcerr) {
3607
3608 continue;
3609 } else if (!hsfsts.hsf_status.flcdone) {
3610 e_dbg("Timeout error - flash cycle did not complete.\n");
3611 break;
3612 }
3613 }
3614 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3615
3616 return ret_val;
3617}
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3629 u32 *data)
3630{
3631 union ich8_hws_flash_status hsfsts;
3632 union ich8_hws_flash_ctrl hsflctl;
3633 u32 flash_linear_addr;
3634 s32 ret_val = -E1000_ERR_NVM;
3635 u8 count = 0;
3636
3637 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3638 hw->mac.type != e1000_pch_spt)
3639 return -E1000_ERR_NVM;
3640 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3641 hw->nvm.flash_base_addr);
3642
3643 do {
3644 udelay(1);
3645
3646 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3647 if (ret_val)
3648 break;
3649
3650
3651
3652 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3653
3654
3655 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3656 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3657
3658
3659
3660 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3661 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3662
3663 ret_val =
3664 e1000_flash_cycle_ich8lan(hw,
3665 ICH_FLASH_READ_COMMAND_TIMEOUT);
3666
3667
3668
3669
3670
3671
3672 if (!ret_val) {
3673 *data = er32flash(ICH_FLASH_FDATA0);
3674 break;
3675 } else {
3676
3677
3678
3679
3680
3681 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3682 if (hsfsts.hsf_status.flcerr) {
3683
3684 continue;
3685 } else if (!hsfsts.hsf_status.flcdone) {
3686 e_dbg("Timeout error - flash cycle did not complete.\n");
3687 break;
3688 }
3689 }
3690 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3691
3692 return ret_val;
3693}
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3705 u16 *data)
3706{
3707 struct e1000_nvm_info *nvm = &hw->nvm;
3708 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3709 u16 i;
3710
3711 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3712 (words == 0)) {
3713 e_dbg("nvm parameter(s) out of bounds\n");
3714 return -E1000_ERR_NVM;
3715 }
3716
3717 nvm->ops.acquire(hw);
3718
3719 for (i = 0; i < words; i++) {
3720 dev_spec->shadow_ram[offset + i].modified = true;
3721 dev_spec->shadow_ram[offset + i].value = data[i];
3722 }
3723
3724 nvm->ops.release(hw);
3725
3726 return 0;
3727}
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3741{
3742 struct e1000_nvm_info *nvm = &hw->nvm;
3743 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3744 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3745 s32 ret_val;
3746 u32 dword = 0;
3747
3748 ret_val = e1000e_update_nvm_checksum_generic(hw);
3749 if (ret_val)
3750 goto out;
3751
3752 if (nvm->type != e1000_nvm_flash_sw)
3753 goto out;
3754
3755 nvm->ops.acquire(hw);
3756
3757
3758
3759
3760
3761 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3762 if (ret_val) {
3763 e_dbg("Could not detect valid bank, assuming bank 0\n");
3764 bank = 0;
3765 }
3766
3767 if (bank == 0) {
3768 new_bank_offset = nvm->flash_bank_size;
3769 old_bank_offset = 0;
3770 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3771 if (ret_val)
3772 goto release;
3773 } else {
3774 old_bank_offset = nvm->flash_bank_size;
3775 new_bank_offset = 0;
3776 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3777 if (ret_val)
3778 goto release;
3779 }
3780 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3781
3782
3783
3784
3785 ret_val = e1000_read_flash_dword_ich8lan(hw,
3786 i + old_bank_offset,
3787 &dword);
3788
3789 if (dev_spec->shadow_ram[i].modified) {
3790 dword &= 0xffff0000;
3791 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3792 }
3793 if (dev_spec->shadow_ram[i + 1].modified) {
3794 dword &= 0x0000ffff;
3795 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3796 << 16);
3797 }
3798 if (ret_val)
3799 break;
3800
3801
3802
3803
3804
3805
3806
3807
3808 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3809 dword |= E1000_ICH_NVM_SIG_MASK << 16;
3810
3811
3812 act_offset = (i + new_bank_offset) << 1;
3813
3814 usleep_range(100, 200);
3815
3816
3817 act_offset = i + new_bank_offset;
3818 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3819 dword);
3820 if (ret_val)
3821 break;
3822 }
3823
3824
3825
3826
3827 if (ret_val) {
3828
3829 e_dbg("Flash commit failed.\n");
3830 goto release;
3831 }
3832
3833
3834
3835
3836
3837
3838 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3839
3840
3841 --act_offset;
3842 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3843
3844 if (ret_val)
3845 goto release;
3846
3847 dword &= 0xBFFFFFFF;
3848 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3849
3850 if (ret_val)
3851 goto release;
3852
3853
3854
3855
3856
3857
3858 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3859
3860
3861 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3862 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3863
3864 if (ret_val)
3865 goto release;
3866
3867 dword &= 0x00FFFFFF;
3868 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3869
3870 if (ret_val)
3871 goto release;
3872
3873
3874 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3875 dev_spec->shadow_ram[i].modified = false;
3876 dev_spec->shadow_ram[i].value = 0xFFFF;
3877 }
3878
3879release:
3880 nvm->ops.release(hw);
3881
3882
3883
3884
3885 if (!ret_val) {
3886 nvm->ops.reload(hw);
3887 usleep_range(10000, 20000);
3888 }
3889
3890out:
3891 if (ret_val)
3892 e_dbg("NVM update error: %d\n", ret_val);
3893
3894 return ret_val;
3895}
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3909{
3910 struct e1000_nvm_info *nvm = &hw->nvm;
3911 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3912 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3913 s32 ret_val;
3914 u16 data = 0;
3915
3916 ret_val = e1000e_update_nvm_checksum_generic(hw);
3917 if (ret_val)
3918 goto out;
3919
3920 if (nvm->type != e1000_nvm_flash_sw)
3921 goto out;
3922
3923 nvm->ops.acquire(hw);
3924
3925
3926
3927
3928
3929 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3930 if (ret_val) {
3931 e_dbg("Could not detect valid bank, assuming bank 0\n");
3932 bank = 0;
3933 }
3934
3935 if (bank == 0) {
3936 new_bank_offset = nvm->flash_bank_size;
3937 old_bank_offset = 0;
3938 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3939 if (ret_val)
3940 goto release;
3941 } else {
3942 old_bank_offset = nvm->flash_bank_size;
3943 new_bank_offset = 0;
3944 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3945 if (ret_val)
3946 goto release;
3947 }
3948 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3949 if (dev_spec->shadow_ram[i].modified) {
3950 data = dev_spec->shadow_ram[i].value;
3951 } else {
3952 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3953 old_bank_offset,
3954 &data);
3955 if (ret_val)
3956 break;
3957 }
3958
3959
3960
3961
3962
3963
3964
3965
3966 if (i == E1000_ICH_NVM_SIG_WORD)
3967 data |= E1000_ICH_NVM_SIG_MASK;
3968
3969
3970 act_offset = (i + new_bank_offset) << 1;
3971
3972 usleep_range(100, 200);
3973
3974 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3975 act_offset,
3976 (u8)data);
3977 if (ret_val)
3978 break;
3979
3980 usleep_range(100, 200);
3981 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3982 act_offset + 1,
3983 (u8)(data >> 8));
3984 if (ret_val)
3985 break;
3986 }
3987
3988
3989
3990
3991 if (ret_val) {
3992
3993 e_dbg("Flash commit failed.\n");
3994 goto release;
3995 }
3996
3997
3998
3999
4000
4001
4002 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4003 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4004 if (ret_val)
4005 goto release;
4006
4007 data &= 0xBFFF;
4008 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4009 act_offset * 2 + 1,
4010 (u8)(data >> 8));
4011 if (ret_val)
4012 goto release;
4013
4014
4015
4016
4017
4018
4019 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4020 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4021 if (ret_val)
4022 goto release;
4023
4024
4025 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4026 dev_spec->shadow_ram[i].modified = false;
4027 dev_spec->shadow_ram[i].value = 0xFFFF;
4028 }
4029
4030release:
4031 nvm->ops.release(hw);
4032
4033
4034
4035
4036 if (!ret_val) {
4037 nvm->ops.reload(hw);
4038 usleep_range(10000, 20000);
4039 }
4040
4041out:
4042 if (ret_val)
4043 e_dbg("NVM update error: %d\n", ret_val);
4044
4045 return ret_val;
4046}
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4057{
4058 s32 ret_val;
4059 u16 data;
4060 u16 word;
4061 u16 valid_csum_mask;
4062
4063
4064
4065
4066
4067
4068 switch (hw->mac.type) {
4069 case e1000_pch_lpt:
4070 case e1000_pch_spt:
4071 word = NVM_COMPAT;
4072 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4073 break;
4074 default:
4075 word = NVM_FUTURE_INIT_WORD1;
4076 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4077 break;
4078 }
4079
4080 ret_val = e1000_read_nvm(hw, word, 1, &data);
4081 if (ret_val)
4082 return ret_val;
4083
4084 if (!(data & valid_csum_mask)) {
4085 data |= valid_csum_mask;
4086 ret_val = e1000_write_nvm(hw, word, 1, &data);
4087 if (ret_val)
4088 return ret_val;
4089 ret_val = e1000e_update_nvm_checksum(hw);
4090 if (ret_val)
4091 return ret_val;
4092 }
4093
4094 return e1000e_validate_nvm_checksum_generic(hw);
4095}
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4108{
4109 struct e1000_nvm_info *nvm = &hw->nvm;
4110 union ich8_flash_protected_range pr0;
4111 union ich8_hws_flash_status hsfsts;
4112 u32 gfpreg;
4113
4114 nvm->ops.acquire(hw);
4115
4116 gfpreg = er32flash(ICH_FLASH_GFPREG);
4117
4118
4119 pr0.regval = er32flash(ICH_FLASH_PR0);
4120 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4121 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4122 pr0.range.wpe = true;
4123 ew32flash(ICH_FLASH_PR0, pr0.regval);
4124
4125
4126
4127
4128
4129
4130 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4131 hsfsts.hsf_status.flockdn = true;
4132 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4133
4134 nvm->ops.release(hw);
4135}
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4147 u8 size, u16 data)
4148{
4149 union ich8_hws_flash_status hsfsts;
4150 union ich8_hws_flash_ctrl hsflctl;
4151 u32 flash_linear_addr;
4152 u32 flash_data = 0;
4153 s32 ret_val;
4154 u8 count = 0;
4155
4156 if (hw->mac.type == e1000_pch_spt) {
4157 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4158 return -E1000_ERR_NVM;
4159 } else {
4160 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4161 return -E1000_ERR_NVM;
4162 }
4163
4164 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4165 hw->nvm.flash_base_addr);
4166
4167 do {
4168 udelay(1);
4169
4170 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4171 if (ret_val)
4172 break;
4173
4174
4175
4176 if (hw->mac.type == e1000_pch_spt)
4177 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4178 else
4179 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4180
4181
4182 hsflctl.hsf_ctrl.fldbcount = size - 1;
4183 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4184
4185
4186
4187
4188 if (hw->mac.type == e1000_pch_spt)
4189 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4190 else
4191 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4192
4193 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4194
4195 if (size == 1)
4196 flash_data = (u32)data & 0x00FF;
4197 else
4198 flash_data = (u32)data;
4199
4200 ew32flash(ICH_FLASH_FDATA0, flash_data);
4201
4202
4203
4204
4205 ret_val =
4206 e1000_flash_cycle_ich8lan(hw,
4207 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4208 if (!ret_val)
4209 break;
4210
4211
4212
4213
4214
4215
4216 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4217 if (hsfsts.hsf_status.flcerr)
4218
4219 continue;
4220 if (!hsfsts.hsf_status.flcdone) {
4221 e_dbg("Timeout error - flash cycle did not complete.\n");
4222 break;
4223 }
4224 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4225
4226 return ret_val;
4227}
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4238 u32 data)
4239{
4240 union ich8_hws_flash_status hsfsts;
4241 union ich8_hws_flash_ctrl hsflctl;
4242 u32 flash_linear_addr;
4243 s32 ret_val;
4244 u8 count = 0;
4245
4246 if (hw->mac.type == e1000_pch_spt) {
4247 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4248 return -E1000_ERR_NVM;
4249 }
4250 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4251 hw->nvm.flash_base_addr);
4252 do {
4253 udelay(1);
4254
4255 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4256 if (ret_val)
4257 break;
4258
4259
4260
4261
4262 if (hw->mac.type == e1000_pch_spt)
4263 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4264 >> 16;
4265 else
4266 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4267
4268 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4269 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4270
4271
4272
4273
4274
4275 if (hw->mac.type == e1000_pch_spt)
4276 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4277 else
4278 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4279
4280 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4281
4282 ew32flash(ICH_FLASH_FDATA0, data);
4283
4284
4285
4286
4287 ret_val =
4288 e1000_flash_cycle_ich8lan(hw,
4289 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4290
4291 if (!ret_val)
4292 break;
4293
4294
4295
4296
4297
4298
4299 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4300
4301 if (hsfsts.hsf_status.flcerr)
4302
4303 continue;
4304 if (!hsfsts.hsf_status.flcdone) {
4305 e_dbg("Timeout error - flash cycle did not complete.\n");
4306 break;
4307 }
4308 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4309
4310 return ret_val;
4311}
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4322 u8 data)
4323{
4324 u16 word = (u16)data;
4325
4326 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4327}
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4339 u32 offset, u32 dword)
4340{
4341 s32 ret_val;
4342 u16 program_retries;
4343
4344
4345 offset <<= 1;
4346 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4347
4348 if (!ret_val)
4349 return ret_val;
4350 for (program_retries = 0; program_retries < 100; program_retries++) {
4351 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4352 usleep_range(100, 200);
4353 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4354 if (!ret_val)
4355 break;
4356 }
4357 if (program_retries == 100)
4358 return -E1000_ERR_NVM;
4359
4360 return 0;
4361}
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4373 u32 offset, u8 byte)
4374{
4375 s32 ret_val;
4376 u16 program_retries;
4377
4378 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4379 if (!ret_val)
4380 return ret_val;
4381
4382 for (program_retries = 0; program_retries < 100; program_retries++) {
4383 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4384 usleep_range(100, 200);
4385 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4386 if (!ret_val)
4387 break;
4388 }
4389 if (program_retries == 100)
4390 return -E1000_ERR_NVM;
4391
4392 return 0;
4393}
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4404{
4405 struct e1000_nvm_info *nvm = &hw->nvm;
4406 union ich8_hws_flash_status hsfsts;
4407 union ich8_hws_flash_ctrl hsflctl;
4408 u32 flash_linear_addr;
4409
4410 u32 flash_bank_size = nvm->flash_bank_size * 2;
4411 s32 ret_val;
4412 s32 count = 0;
4413 s32 j, iteration, sector_size;
4414
4415 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429 switch (hsfsts.hsf_status.berasesz) {
4430 case 0:
4431
4432 sector_size = ICH_FLASH_SEG_SIZE_256;
4433 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4434 break;
4435 case 1:
4436 sector_size = ICH_FLASH_SEG_SIZE_4K;
4437 iteration = 1;
4438 break;
4439 case 2:
4440 sector_size = ICH_FLASH_SEG_SIZE_8K;
4441 iteration = 1;
4442 break;
4443 case 3:
4444 sector_size = ICH_FLASH_SEG_SIZE_64K;
4445 iteration = 1;
4446 break;
4447 default:
4448 return -E1000_ERR_NVM;
4449 }
4450
4451
4452 flash_linear_addr = hw->nvm.flash_base_addr;
4453 flash_linear_addr += (bank) ? flash_bank_size : 0;
4454
4455 for (j = 0; j < iteration; j++) {
4456 do {
4457 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4458
4459
4460 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4461 if (ret_val)
4462 return ret_val;
4463
4464
4465
4466
4467 if (hw->mac.type == e1000_pch_spt)
4468 hsflctl.regval =
4469 er32flash(ICH_FLASH_HSFSTS) >> 16;
4470 else
4471 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4472
4473 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4474 if (hw->mac.type == e1000_pch_spt)
4475 ew32flash(ICH_FLASH_HSFSTS,
4476 hsflctl.regval << 16);
4477 else
4478 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4479
4480
4481
4482
4483
4484 flash_linear_addr += (j * sector_size);
4485 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4486
4487 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4488 if (!ret_val)
4489 break;
4490
4491
4492
4493
4494
4495 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4496 if (hsfsts.hsf_status.flcerr)
4497
4498 continue;
4499 else if (!hsfsts.hsf_status.flcdone)
4500 return ret_val;
4501 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4502 }
4503
4504 return 0;
4505}
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4517{
4518 s32 ret_val;
4519
4520 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4521 if (ret_val) {
4522 e_dbg("NVM Read Error\n");
4523 return ret_val;
4524 }
4525
4526 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4527 *data = ID_LED_DEFAULT_ICH8LAN;
4528
4529 return 0;
4530}
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4546{
4547 struct e1000_mac_info *mac = &hw->mac;
4548 s32 ret_val;
4549 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4550 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4551 u16 data, i, temp, shift;
4552
4553
4554 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4555 if (ret_val)
4556 return ret_val;
4557
4558 mac->ledctl_default = er32(LEDCTL);
4559 mac->ledctl_mode1 = mac->ledctl_default;
4560 mac->ledctl_mode2 = mac->ledctl_default;
4561
4562 for (i = 0; i < 4; i++) {
4563 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4564 shift = (i * 5);
4565 switch (temp) {
4566 case ID_LED_ON1_DEF2:
4567 case ID_LED_ON1_ON2:
4568 case ID_LED_ON1_OFF2:
4569 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4570 mac->ledctl_mode1 |= (ledctl_on << shift);
4571 break;
4572 case ID_LED_OFF1_DEF2:
4573 case ID_LED_OFF1_ON2:
4574 case ID_LED_OFF1_OFF2:
4575 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4576 mac->ledctl_mode1 |= (ledctl_off << shift);
4577 break;
4578 default:
4579
4580 break;
4581 }
4582 switch (temp) {
4583 case ID_LED_DEF1_ON2:
4584 case ID_LED_ON1_ON2:
4585 case ID_LED_OFF1_ON2:
4586 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4587 mac->ledctl_mode2 |= (ledctl_on << shift);
4588 break;
4589 case ID_LED_DEF1_OFF2:
4590 case ID_LED_ON1_OFF2:
4591 case ID_LED_OFF1_OFF2:
4592 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4593 mac->ledctl_mode2 |= (ledctl_off << shift);
4594 break;
4595 default:
4596
4597 break;
4598 }
4599 }
4600
4601 return 0;
4602}
4603
4604
4605
4606
4607
4608
4609
4610
4611static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4612{
4613 struct e1000_bus_info *bus = &hw->bus;
4614 s32 ret_val;
4615
4616 ret_val = e1000e_get_bus_info_pcie(hw);
4617
4618
4619
4620
4621
4622
4623 if (bus->width == e1000_bus_width_unknown)
4624 bus->width = e1000_bus_width_pcie_x1;
4625
4626 return ret_val;
4627}
4628
4629
4630
4631
4632
4633
4634
4635
4636static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4637{
4638 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4639 u16 kum_cfg;
4640 u32 ctrl, reg;
4641 s32 ret_val;
4642
4643
4644
4645
4646 ret_val = e1000e_disable_pcie_master(hw);
4647 if (ret_val)
4648 e_dbg("PCI-E Master disable polling has failed.\n");
4649
4650 e_dbg("Masking off all interrupts\n");
4651 ew32(IMC, 0xffffffff);
4652
4653
4654
4655
4656
4657 ew32(RCTL, 0);
4658 ew32(TCTL, E1000_TCTL_PSP);
4659 e1e_flush();
4660
4661 usleep_range(10000, 20000);
4662
4663
4664 if (hw->mac.type == e1000_ich8lan) {
4665
4666 ew32(PBA, E1000_PBA_8K);
4667
4668 ew32(PBS, E1000_PBS_16K);
4669 }
4670
4671 if (hw->mac.type == e1000_pchlan) {
4672
4673 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4674 if (ret_val)
4675 return ret_val;
4676
4677 if (kum_cfg & E1000_NVM_K1_ENABLE)
4678 dev_spec->nvm_k1_enabled = true;
4679 else
4680 dev_spec->nvm_k1_enabled = false;
4681 }
4682
4683 ctrl = er32(CTRL);
4684
4685 if (!hw->phy.ops.check_reset_block(hw)) {
4686
4687
4688
4689
4690 ctrl |= E1000_CTRL_PHY_RST;
4691
4692
4693
4694
4695 if ((hw->mac.type == e1000_pch2lan) &&
4696 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4697 e1000_gate_hw_phy_config_ich8lan(hw, true);
4698 }
4699 ret_val = e1000_acquire_swflag_ich8lan(hw);
4700 e_dbg("Issuing a global reset to ich8lan\n");
4701 ew32(CTRL, (ctrl | E1000_CTRL_RST));
4702
4703 msleep(20);
4704
4705
4706 if (hw->mac.type == e1000_pch2lan) {
4707 reg = er32(FEXTNVM3);
4708 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4709 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4710 ew32(FEXTNVM3, reg);
4711 }
4712
4713 if (!ret_val)
4714 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4715
4716 if (ctrl & E1000_CTRL_PHY_RST) {
4717 ret_val = hw->phy.ops.get_cfg_done(hw);
4718 if (ret_val)
4719 return ret_val;
4720
4721 ret_val = e1000_post_phy_reset_ich8lan(hw);
4722 if (ret_val)
4723 return ret_val;
4724 }
4725
4726
4727
4728
4729
4730 if (hw->mac.type == e1000_pchlan)
4731 ew32(CRC_OFFSET, 0x65656565);
4732
4733 ew32(IMC, 0xffffffff);
4734 er32(ICR);
4735
4736 reg = er32(KABGTXD);
4737 reg |= E1000_KABGTXD_BGSQLBIAS;
4738 ew32(KABGTXD, reg);
4739
4740 return 0;
4741}
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4756{
4757 struct e1000_mac_info *mac = &hw->mac;
4758 u32 ctrl_ext, txdctl, snoop;
4759 s32 ret_val;
4760 u16 i;
4761
4762 e1000_initialize_hw_bits_ich8lan(hw);
4763
4764
4765 ret_val = mac->ops.id_led_init(hw);
4766
4767 if (ret_val)
4768 e_dbg("Error initializing identification LED\n");
4769
4770
4771 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4772
4773
4774 e_dbg("Zeroing the MTA\n");
4775 for (i = 0; i < mac->mta_reg_count; i++)
4776 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4777
4778
4779
4780
4781
4782 if (hw->phy.type == e1000_phy_82578) {
4783 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4784 i &= ~BM_WUC_HOST_WU_BIT;
4785 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4786 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4787 if (ret_val)
4788 return ret_val;
4789 }
4790
4791
4792 ret_val = mac->ops.setup_link(hw);
4793
4794
4795 txdctl = er32(TXDCTL(0));
4796 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4797 E1000_TXDCTL_FULL_TX_DESC_WB);
4798 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4799 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4800 ew32(TXDCTL(0), txdctl);
4801 txdctl = er32(TXDCTL(1));
4802 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4803 E1000_TXDCTL_FULL_TX_DESC_WB);
4804 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4805 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4806 ew32(TXDCTL(1), txdctl);
4807
4808
4809
4810
4811 if (mac->type == e1000_ich8lan)
4812 snoop = PCIE_ICH8_SNOOP_ALL;
4813 else
4814 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4815 e1000e_set_pcie_no_snoop(hw, snoop);
4816
4817 ctrl_ext = er32(CTRL_EXT);
4818 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4819 ew32(CTRL_EXT, ctrl_ext);
4820
4821
4822
4823
4824
4825
4826 e1000_clear_hw_cntrs_ich8lan(hw);
4827
4828 return ret_val;
4829}
4830
4831
4832
4833
4834
4835
4836
4837
4838static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4839{
4840 u32 reg;
4841
4842
4843 reg = er32(CTRL_EXT);
4844 reg |= BIT(22);
4845
4846 if (hw->mac.type >= e1000_pchlan)
4847 reg |= E1000_CTRL_EXT_PHYPDEN;
4848 ew32(CTRL_EXT, reg);
4849
4850
4851 reg = er32(TXDCTL(0));
4852 reg |= BIT(22);
4853 ew32(TXDCTL(0), reg);
4854
4855
4856 reg = er32(TXDCTL(1));
4857 reg |= BIT(22);
4858 ew32(TXDCTL(1), reg);
4859
4860
4861 reg = er32(TARC(0));
4862 if (hw->mac.type == e1000_ich8lan)
4863 reg |= BIT(28) | BIT(29);
4864 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4865 ew32(TARC(0), reg);
4866
4867
4868 reg = er32(TARC(1));
4869 if (er32(TCTL) & E1000_TCTL_MULR)
4870 reg &= ~BIT(28);
4871 else
4872 reg |= BIT(28);
4873 reg |= BIT(24) | BIT(26) | BIT(30);
4874 ew32(TARC(1), reg);
4875
4876
4877 if (hw->mac.type == e1000_ich8lan) {
4878 reg = er32(STATUS);
4879 reg &= ~BIT(31);
4880 ew32(STATUS, reg);
4881 }
4882
4883
4884
4885
4886 reg = er32(RFCTL);
4887 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4888
4889
4890
4891
4892 if (hw->mac.type == e1000_ich8lan)
4893 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4894 ew32(RFCTL, reg);
4895
4896
4897 if ((hw->mac.type == e1000_pch_lpt) ||
4898 (hw->mac.type == e1000_pch_spt)) {
4899 reg = er32(PBECCSTS);
4900 reg |= E1000_PBECCSTS_ECC_ENABLE;
4901 ew32(PBECCSTS, reg);
4902
4903 reg = er32(CTRL);
4904 reg |= E1000_CTRL_MEHE;
4905 ew32(CTRL, reg);
4906 }
4907}
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4920{
4921 s32 ret_val;
4922
4923 if (hw->phy.ops.check_reset_block(hw))
4924 return 0;
4925
4926
4927
4928
4929
4930 if (hw->fc.requested_mode == e1000_fc_default) {
4931
4932 if (hw->mac.type == e1000_pchlan)
4933 hw->fc.requested_mode = e1000_fc_rx_pause;
4934 else
4935 hw->fc.requested_mode = e1000_fc_full;
4936 }
4937
4938
4939
4940
4941 hw->fc.current_mode = hw->fc.requested_mode;
4942
4943 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4944
4945
4946 ret_val = hw->mac.ops.setup_physical_interface(hw);
4947 if (ret_val)
4948 return ret_val;
4949
4950 ew32(FCTTV, hw->fc.pause_time);
4951 if ((hw->phy.type == e1000_phy_82578) ||
4952 (hw->phy.type == e1000_phy_82579) ||
4953 (hw->phy.type == e1000_phy_i217) ||
4954 (hw->phy.type == e1000_phy_82577)) {
4955 ew32(FCRTV_PCH, hw->fc.refresh_time);
4956
4957 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4958 hw->fc.pause_time);
4959 if (ret_val)
4960 return ret_val;
4961 }
4962
4963 return e1000e_set_fc_watermarks(hw);
4964}
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4975{
4976 u32 ctrl;
4977 s32 ret_val;
4978 u16 reg_data;
4979
4980 ctrl = er32(CTRL);
4981 ctrl |= E1000_CTRL_SLU;
4982 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4983 ew32(CTRL, ctrl);
4984
4985
4986
4987
4988
4989 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
4990 if (ret_val)
4991 return ret_val;
4992 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4993 ®_data);
4994 if (ret_val)
4995 return ret_val;
4996 reg_data |= 0x3F;
4997 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4998 reg_data);
4999 if (ret_val)
5000 return ret_val;
5001
5002 switch (hw->phy.type) {
5003 case e1000_phy_igp_3:
5004 ret_val = e1000e_copper_link_setup_igp(hw);
5005 if (ret_val)
5006 return ret_val;
5007 break;
5008 case e1000_phy_bm:
5009 case e1000_phy_82578:
5010 ret_val = e1000e_copper_link_setup_m88(hw);
5011 if (ret_val)
5012 return ret_val;
5013 break;
5014 case e1000_phy_82577:
5015 case e1000_phy_82579:
5016 ret_val = e1000_copper_link_setup_82577(hw);
5017 if (ret_val)
5018 return ret_val;
5019 break;
5020 case e1000_phy_ife:
5021 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
5022 if (ret_val)
5023 return ret_val;
5024
5025 reg_data &= ~IFE_PMC_AUTO_MDIX;
5026
5027 switch (hw->phy.mdix) {
5028 case 1:
5029 reg_data &= ~IFE_PMC_FORCE_MDIX;
5030 break;
5031 case 2:
5032 reg_data |= IFE_PMC_FORCE_MDIX;
5033 break;
5034 case 0:
5035 default:
5036 reg_data |= IFE_PMC_AUTO_MDIX;
5037 break;
5038 }
5039 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5040 if (ret_val)
5041 return ret_val;
5042 break;
5043 default:
5044 break;
5045 }
5046
5047 return e1000e_setup_copper_link(hw);
5048}
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5059{
5060 u32 ctrl;
5061 s32 ret_val;
5062
5063 ctrl = er32(CTRL);
5064 ctrl |= E1000_CTRL_SLU;
5065 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5066 ew32(CTRL, ctrl);
5067
5068 ret_val = e1000_copper_link_setup_82577(hw);
5069 if (ret_val)
5070 return ret_val;
5071
5072 return e1000e_setup_copper_link(hw);
5073}
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5086 u16 *duplex)
5087{
5088 s32 ret_val;
5089
5090 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5091 if (ret_val)
5092 return ret_val;
5093
5094 if ((hw->mac.type == e1000_ich8lan) &&
5095 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5096 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5097 }
5098
5099 return ret_val;
5100}
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5118{
5119 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5120 u32 phy_ctrl;
5121 s32 ret_val;
5122 u16 i, data;
5123 bool link;
5124
5125 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5126 return 0;
5127
5128
5129
5130
5131
5132 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5133 if (!link)
5134 return 0;
5135
5136 for (i = 0; i < 10; i++) {
5137
5138 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5139 if (ret_val)
5140 return ret_val;
5141
5142 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5143 if (ret_val)
5144 return ret_val;
5145
5146
5147 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5148 return 0;
5149
5150
5151 e1000_phy_hw_reset(hw);
5152 mdelay(5);
5153 }
5154
5155 phy_ctrl = er32(PHY_CTRL);
5156 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5157 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5158 ew32(PHY_CTRL, phy_ctrl);
5159
5160
5161
5162
5163 e1000e_gig_downshift_workaround_ich8lan(hw);
5164
5165
5166 return -E1000_ERR_PHY;
5167}
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5178 bool state)
5179{
5180 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5181
5182 if (hw->mac.type != e1000_ich8lan) {
5183 e_dbg("Workaround applies to ICH8 only.\n");
5184 return;
5185 }
5186
5187 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5188}
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5201{
5202 u32 reg;
5203 u16 data;
5204 u8 retry = 0;
5205
5206 if (hw->phy.type != e1000_phy_igp_3)
5207 return;
5208
5209
5210 do {
5211
5212 reg = er32(PHY_CTRL);
5213 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5214 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5215 ew32(PHY_CTRL, reg);
5216
5217
5218
5219
5220 if (hw->mac.type == e1000_ich8lan)
5221 e1000e_gig_downshift_workaround_ich8lan(hw);
5222
5223
5224 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5225 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5226 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5227
5228
5229 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5230 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5231 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5232 break;
5233
5234
5235 reg = er32(CTRL);
5236 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5237 retry++;
5238 } while (retry);
5239}
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5252{
5253 s32 ret_val;
5254 u16 reg_data;
5255
5256 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5257 return;
5258
5259 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5260 ®_data);
5261 if (ret_val)
5262 return;
5263 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5264 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5265 reg_data);
5266 if (ret_val)
5267 return;
5268 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5269 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5270}
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5287{
5288 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5289 u32 phy_ctrl;
5290 s32 ret_val;
5291
5292 phy_ctrl = er32(PHY_CTRL);
5293 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5294
5295 if (hw->phy.type == e1000_phy_i217) {
5296 u16 phy_reg, device_id = hw->adapter->pdev->device;
5297
5298 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5299 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5300 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5301 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5302 (hw->mac.type == e1000_pch_spt)) {
5303 u32 fextnvm6 = er32(FEXTNVM6);
5304
5305 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5306 }
5307
5308 ret_val = hw->phy.ops.acquire(hw);
5309 if (ret_val)
5310 goto out;
5311
5312 if (!dev_spec->eee_disable) {
5313 u16 eee_advert;
5314
5315 ret_val =
5316 e1000_read_emi_reg_locked(hw,
5317 I217_EEE_ADVERTISEMENT,
5318 &eee_advert);
5319 if (ret_val)
5320 goto release;
5321
5322
5323
5324
5325
5326
5327 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5328 (dev_spec->eee_lp_ability &
5329 I82579_EEE_100_SUPPORTED) &&
5330 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5331 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5332 E1000_PHY_CTRL_NOND0A_LPLU);
5333
5334
5335 e1e_rphy_locked(hw,
5336 I217_LPI_GPIO_CTRL, &phy_reg);
5337 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5338 e1e_wphy_locked(hw,
5339 I217_LPI_GPIO_CTRL, phy_reg);
5340 }
5341 }
5342
5343
5344
5345
5346
5347
5348
5349
5350 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5351
5352 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5353 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5354 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5355
5356
5357
5358
5359 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5360 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5361 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5362
5363
5364 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5365 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5366 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5367 }
5368
5369
5370
5371
5372 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5373 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5374 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5375
5376release:
5377 hw->phy.ops.release(hw);
5378 }
5379out:
5380 ew32(PHY_CTRL, phy_ctrl);
5381
5382 if (hw->mac.type == e1000_ich8lan)
5383 e1000e_gig_downshift_workaround_ich8lan(hw);
5384
5385 if (hw->mac.type >= e1000_pchlan) {
5386 e1000_oem_bits_config_ich8lan(hw, false);
5387
5388
5389 if (hw->mac.type == e1000_pchlan)
5390 e1000e_phy_hw_reset_generic(hw);
5391
5392 ret_val = hw->phy.ops.acquire(hw);
5393 if (ret_val)
5394 return;
5395 e1000_write_smbus_addr(hw);
5396 hw->phy.ops.release(hw);
5397 }
5398}
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5411{
5412 s32 ret_val;
5413
5414 if (hw->mac.type < e1000_pch2lan)
5415 return;
5416
5417 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5418 if (ret_val) {
5419 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5420 return;
5421 }
5422
5423
5424
5425
5426
5427
5428 if (hw->phy.type == e1000_phy_i217) {
5429 u16 phy_reg;
5430
5431 ret_val = hw->phy.ops.acquire(hw);
5432 if (ret_val) {
5433 e_dbg("Failed to setup iRST\n");
5434 return;
5435 }
5436
5437
5438 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5439 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5440 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5441
5442 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5443
5444
5445
5446 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5447 if (ret_val)
5448 goto release;
5449 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5450 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5451
5452
5453 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5454 }
5455
5456 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5457 if (ret_val)
5458 goto release;
5459 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5460 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5461release:
5462 if (ret_val)
5463 e_dbg("Error %d in resume workarounds\n", ret_val);
5464 hw->phy.ops.release(hw);
5465 }
5466}
5467
5468
5469
5470
5471
5472
5473
5474static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5475{
5476 if (hw->phy.type == e1000_phy_ife)
5477 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5478
5479 ew32(LEDCTL, hw->mac.ledctl_default);
5480 return 0;
5481}
5482
5483
5484
5485
5486
5487
5488
5489static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5490{
5491 if (hw->phy.type == e1000_phy_ife)
5492 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5493 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5494
5495 ew32(LEDCTL, hw->mac.ledctl_mode2);
5496 return 0;
5497}
5498
5499
5500
5501
5502
5503
5504
5505static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5506{
5507 if (hw->phy.type == e1000_phy_ife)
5508 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5509 (IFE_PSCL_PROBE_MODE |
5510 IFE_PSCL_PROBE_LEDS_OFF));
5511
5512 ew32(LEDCTL, hw->mac.ledctl_mode1);
5513 return 0;
5514}
5515
5516
5517
5518
5519
5520
5521
5522static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5523{
5524 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5525}
5526
5527
5528
5529
5530
5531
5532
5533static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5534{
5535 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5536}
5537
5538
5539
5540
5541
5542
5543
5544static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5545{
5546 u16 data = (u16)hw->mac.ledctl_mode2;
5547 u32 i, led;
5548
5549
5550
5551
5552 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5553 for (i = 0; i < 3; i++) {
5554 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5555 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5556 E1000_LEDCTL_MODE_LINK_UP)
5557 continue;
5558 if (led & E1000_PHY_LED0_IVRT)
5559 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5560 else
5561 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5562 }
5563 }
5564
5565 return e1e_wphy(hw, HV_LED_CONFIG, data);
5566}
5567
5568
5569
5570
5571
5572
5573
5574static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5575{
5576 u16 data = (u16)hw->mac.ledctl_mode1;
5577 u32 i, led;
5578
5579
5580
5581
5582 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5583 for (i = 0; i < 3; i++) {
5584 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5585 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5586 E1000_LEDCTL_MODE_LINK_UP)
5587 continue;
5588 if (led & E1000_PHY_LED0_IVRT)
5589 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5590 else
5591 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5592 }
5593 }
5594
5595 return e1e_wphy(hw, HV_LED_CONFIG, data);
5596}
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5611{
5612 s32 ret_val = 0;
5613 u32 bank = 0;
5614 u32 status;
5615
5616 e1000e_get_cfg_done_generic(hw);
5617
5618
5619 if (hw->mac.type >= e1000_ich10lan) {
5620 e1000_lan_init_done_ich8lan(hw);
5621 } else {
5622 ret_val = e1000e_get_auto_rd_done(hw);
5623 if (ret_val) {
5624
5625
5626
5627
5628 e_dbg("Auto Read Done did not complete\n");
5629 ret_val = 0;
5630 }
5631 }
5632
5633
5634 status = er32(STATUS);
5635 if (status & E1000_STATUS_PHYRA)
5636 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5637 else
5638 e_dbg("PHY Reset Asserted not set - needs delay\n");
5639
5640
5641 if (hw->mac.type <= e1000_ich9lan) {
5642 if (!(er32(EECD) & E1000_EECD_PRES) &&
5643 (hw->phy.type == e1000_phy_igp_3)) {
5644 e1000e_phy_init_script_igp3(hw);
5645 }
5646 } else {
5647 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5648
5649 e_dbg("EEPROM not present\n");
5650 ret_val = -E1000_ERR_CONFIG;
5651 }
5652 }
5653
5654 return ret_val;
5655}
5656
5657
5658
5659
5660
5661
5662
5663
5664static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5665{
5666
5667 if (!(hw->mac.ops.check_mng_mode(hw) ||
5668 hw->phy.ops.check_reset_block(hw)))
5669 e1000_power_down_phy_copper(hw);
5670}
5671
5672
5673
5674
5675
5676
5677
5678
5679static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5680{
5681 u16 phy_data;
5682 s32 ret_val;
5683
5684 e1000e_clear_hw_cntrs_base(hw);
5685
5686 er32(ALGNERRC);
5687 er32(RXERRC);
5688 er32(TNCRS);
5689 er32(CEXTERR);
5690 er32(TSCTC);
5691 er32(TSCTFC);
5692
5693 er32(MGTPRC);
5694 er32(MGTPDC);
5695 er32(MGTPTC);
5696
5697 er32(IAC);
5698 er32(ICRXOC);
5699
5700
5701 if ((hw->phy.type == e1000_phy_82578) ||
5702 (hw->phy.type == e1000_phy_82579) ||
5703 (hw->phy.type == e1000_phy_i217) ||
5704 (hw->phy.type == e1000_phy_82577)) {
5705 ret_val = hw->phy.ops.acquire(hw);
5706 if (ret_val)
5707 return;
5708 ret_val = hw->phy.ops.set_page(hw,
5709 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5710 if (ret_val)
5711 goto release;
5712 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5713 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5714 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5715 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5716 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5717 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5718 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5719 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5720 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5721 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5722 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5723 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5724 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5725 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5726release:
5727 hw->phy.ops.release(hw);
5728 }
5729}
5730
5731static const struct e1000_mac_operations ich8_mac_ops = {
5732
5733 .check_for_link = e1000_check_for_copper_link_ich8lan,
5734
5735 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5736 .get_bus_info = e1000_get_bus_info_ich8lan,
5737 .set_lan_id = e1000_set_lan_id_single_port,
5738 .get_link_up_info = e1000_get_link_up_info_ich8lan,
5739
5740
5741 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5742 .reset_hw = e1000_reset_hw_ich8lan,
5743 .init_hw = e1000_init_hw_ich8lan,
5744 .setup_link = e1000_setup_link_ich8lan,
5745 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5746
5747 .config_collision_dist = e1000e_config_collision_dist_generic,
5748 .rar_set = e1000e_rar_set_generic,
5749 .rar_get_count = e1000e_rar_get_count_generic,
5750};
5751
5752static const struct e1000_phy_operations ich8_phy_ops = {
5753 .acquire = e1000_acquire_swflag_ich8lan,
5754 .check_reset_block = e1000_check_reset_block_ich8lan,
5755 .commit = NULL,
5756 .get_cfg_done = e1000_get_cfg_done_ich8lan,
5757 .get_cable_length = e1000e_get_cable_length_igp_2,
5758 .read_reg = e1000e_read_phy_reg_igp,
5759 .release = e1000_release_swflag_ich8lan,
5760 .reset = e1000_phy_hw_reset_ich8lan,
5761 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5762 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5763 .write_reg = e1000e_write_phy_reg_igp,
5764};
5765
5766static const struct e1000_nvm_operations ich8_nvm_ops = {
5767 .acquire = e1000_acquire_nvm_ich8lan,
5768 .read = e1000_read_nvm_ich8lan,
5769 .release = e1000_release_nvm_ich8lan,
5770 .reload = e1000e_reload_nvm_generic,
5771 .update = e1000_update_nvm_checksum_ich8lan,
5772 .valid_led_default = e1000_valid_led_default_ich8lan,
5773 .validate = e1000_validate_nvm_checksum_ich8lan,
5774 .write = e1000_write_nvm_ich8lan,
5775};
5776
5777static const struct e1000_nvm_operations spt_nvm_ops = {
5778 .acquire = e1000_acquire_nvm_ich8lan,
5779 .release = e1000_release_nvm_ich8lan,
5780 .read = e1000_read_nvm_spt,
5781 .update = e1000_update_nvm_checksum_spt,
5782 .reload = e1000e_reload_nvm_generic,
5783 .valid_led_default = e1000_valid_led_default_ich8lan,
5784 .validate = e1000_validate_nvm_checksum_ich8lan,
5785 .write = e1000_write_nvm_ich8lan,
5786};
5787
5788const struct e1000_info e1000_ich8_info = {
5789 .mac = e1000_ich8lan,
5790 .flags = FLAG_HAS_WOL
5791 | FLAG_IS_ICH
5792 | FLAG_HAS_CTRLEXT_ON_LOAD
5793 | FLAG_HAS_AMT
5794 | FLAG_HAS_FLASH
5795 | FLAG_APME_IN_WUC,
5796 .pba = 8,
5797 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5798 .get_variants = e1000_get_variants_ich8lan,
5799 .mac_ops = &ich8_mac_ops,
5800 .phy_ops = &ich8_phy_ops,
5801 .nvm_ops = &ich8_nvm_ops,
5802};
5803
5804const struct e1000_info e1000_ich9_info = {
5805 .mac = e1000_ich9lan,
5806 .flags = FLAG_HAS_JUMBO_FRAMES
5807 | FLAG_IS_ICH
5808 | FLAG_HAS_WOL
5809 | FLAG_HAS_CTRLEXT_ON_LOAD
5810 | FLAG_HAS_AMT
5811 | FLAG_HAS_FLASH
5812 | FLAG_APME_IN_WUC,
5813 .pba = 18,
5814 .max_hw_frame_size = DEFAULT_JUMBO,
5815 .get_variants = e1000_get_variants_ich8lan,
5816 .mac_ops = &ich8_mac_ops,
5817 .phy_ops = &ich8_phy_ops,
5818 .nvm_ops = &ich8_nvm_ops,
5819};
5820
5821const struct e1000_info e1000_ich10_info = {
5822 .mac = e1000_ich10lan,
5823 .flags = FLAG_HAS_JUMBO_FRAMES
5824 | FLAG_IS_ICH
5825 | FLAG_HAS_WOL
5826 | FLAG_HAS_CTRLEXT_ON_LOAD
5827 | FLAG_HAS_AMT
5828 | FLAG_HAS_FLASH
5829 | FLAG_APME_IN_WUC,
5830 .pba = 18,
5831 .max_hw_frame_size = DEFAULT_JUMBO,
5832 .get_variants = e1000_get_variants_ich8lan,
5833 .mac_ops = &ich8_mac_ops,
5834 .phy_ops = &ich8_phy_ops,
5835 .nvm_ops = &ich8_nvm_ops,
5836};
5837
5838const struct e1000_info e1000_pch_info = {
5839 .mac = e1000_pchlan,
5840 .flags = FLAG_IS_ICH
5841 | FLAG_HAS_WOL
5842 | FLAG_HAS_CTRLEXT_ON_LOAD
5843 | FLAG_HAS_AMT
5844 | FLAG_HAS_FLASH
5845 | FLAG_HAS_JUMBO_FRAMES
5846 | FLAG_DISABLE_FC_PAUSE_TIME
5847 | FLAG_APME_IN_WUC,
5848 .flags2 = FLAG2_HAS_PHY_STATS,
5849 .pba = 26,
5850 .max_hw_frame_size = 4096,
5851 .get_variants = e1000_get_variants_ich8lan,
5852 .mac_ops = &ich8_mac_ops,
5853 .phy_ops = &ich8_phy_ops,
5854 .nvm_ops = &ich8_nvm_ops,
5855};
5856
5857const struct e1000_info e1000_pch2_info = {
5858 .mac = e1000_pch2lan,
5859 .flags = FLAG_IS_ICH
5860 | FLAG_HAS_WOL
5861 | FLAG_HAS_HW_TIMESTAMP
5862 | FLAG_HAS_CTRLEXT_ON_LOAD
5863 | FLAG_HAS_AMT
5864 | FLAG_HAS_FLASH
5865 | FLAG_HAS_JUMBO_FRAMES
5866 | FLAG_APME_IN_WUC,
5867 .flags2 = FLAG2_HAS_PHY_STATS
5868 | FLAG2_HAS_EEE,
5869 .pba = 26,
5870 .max_hw_frame_size = 9022,
5871 .get_variants = e1000_get_variants_ich8lan,
5872 .mac_ops = &ich8_mac_ops,
5873 .phy_ops = &ich8_phy_ops,
5874 .nvm_ops = &ich8_nvm_ops,
5875};
5876
5877const struct e1000_info e1000_pch_lpt_info = {
5878 .mac = e1000_pch_lpt,
5879 .flags = FLAG_IS_ICH
5880 | FLAG_HAS_WOL
5881 | FLAG_HAS_HW_TIMESTAMP
5882 | FLAG_HAS_CTRLEXT_ON_LOAD
5883 | FLAG_HAS_AMT
5884 | FLAG_HAS_FLASH
5885 | FLAG_HAS_JUMBO_FRAMES
5886 | FLAG_APME_IN_WUC,
5887 .flags2 = FLAG2_HAS_PHY_STATS
5888 | FLAG2_HAS_EEE,
5889 .pba = 26,
5890 .max_hw_frame_size = 9022,
5891 .get_variants = e1000_get_variants_ich8lan,
5892 .mac_ops = &ich8_mac_ops,
5893 .phy_ops = &ich8_phy_ops,
5894 .nvm_ops = &ich8_nvm_ops,
5895};
5896
5897const struct e1000_info e1000_pch_spt_info = {
5898 .mac = e1000_pch_spt,
5899 .flags = FLAG_IS_ICH
5900 | FLAG_HAS_WOL
5901 | FLAG_HAS_HW_TIMESTAMP
5902 | FLAG_HAS_CTRLEXT_ON_LOAD
5903 | FLAG_HAS_AMT
5904 | FLAG_HAS_FLASH
5905 | FLAG_HAS_JUMBO_FRAMES
5906 | FLAG_APME_IN_WUC,
5907 .flags2 = FLAG2_HAS_PHY_STATS
5908 | FLAG2_HAS_EEE,
5909 .pba = 26,
5910 .max_hw_frame_size = 9022,
5911 .get_variants = e1000_get_variants_ich8lan,
5912 .mac_ops = &ich8_mac_ops,
5913 .phy_ops = &ich8_phy_ops,
5914 .nvm_ops = &spt_nvm_ops,
5915};
5916