LXR linux/drivers/net/ethernet/rdc/r6040.c

   1/*
   2 * RDC R6040 Fast Ethernet MAC support
   3 *
   4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
   5 * Copyright (C) 2007
   6 *      Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
   7 * Copyright (C) 2007-2012 Florian Fainelli <florian@openwrt.org>
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License
  11 * as published by the Free Software Foundation; either version 2
  12 * of the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the
  21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  22 * Boston, MA  02110-1301, USA.
  23*/
  24
  25#include <linux/kernel.h>
  26#include <linux/module.h>
  27#include <linux/moduleparam.h>
  28#include <linux/string.h>
  29#include <linux/timer.h>
  30#include <linux/errno.h>
  31#include <linux/ioport.h>
  32#include <linux/interrupt.h>
  33#include <linux/pci.h>
  34#include <linux/netdevice.h>
  35#include <linux/etherdevice.h>
  36#include <linux/skbuff.h>
  37#include <linux/delay.h>
  38#include <linux/mii.h>
  39#include <linux/ethtool.h>
  40#include <linux/crc32.h>
  41#include <linux/spinlock.h>
  42#include <linux/bitops.h>
  43#include <linux/io.h>
  44#include <linux/irq.h>
  45#include <linux/uaccess.h>
  46#include <linux/phy.h>
  47
  48#include <asm/processor.h>
  49
  50#define DRV_NAME        "r6040"
  51#define DRV_VERSION     "0.28"
  52#define DRV_RELDATE     "07Oct2011"
  53
  54/* Time in jiffies before concluding the transmitter is hung. */
  55#define TX_TIMEOUT      (6000 * HZ / 1000)
  56
  57/* RDC MAC I/O Size */
  58#define R6040_IO_SIZE   256
  59
  60/* MAX RDC MAC */
  61#define MAX_MAC         2
  62
  63/* MAC registers */
  64#define MCR0            0x00    /* Control register 0 */
  65#define  MCR0_RCVEN     0x0002  /* Receive enable */
  66#define  MCR0_PROMISC   0x0020  /* Promiscuous mode */
  67#define  MCR0_HASH_EN   0x0100  /* Enable multicast hash table function */
  68#define  MCR0_XMTEN     0x1000  /* Transmission enable */
  69#define  MCR0_FD        0x8000  /* Full/Half duplex */
  70#define MCR1            0x04    /* Control register 1 */
  71#define  MAC_RST        0x0001  /* Reset the MAC */
  72#define MBCR            0x08    /* Bus control */
  73#define MT_ICR          0x0C    /* TX interrupt control */
  74#define MR_ICR          0x10    /* RX interrupt control */
  75#define MTPR            0x14    /* TX poll command register */
  76#define  TM2TX          0x0001  /* Trigger MAC to transmit */
  77#define MR_BSR          0x18    /* RX buffer size */
  78#define MR_DCR          0x1A    /* RX descriptor control */
  79#define MLSR            0x1C    /* Last status */
  80#define  TX_FIFO_UNDR   0x0200  /* TX FIFO under-run */
  81#define  TX_EXCEEDC     0x2000  /* Transmit exceed collision */
  82#define  TX_LATEC       0x4000  /* Transmit late collision */
  83#define MMDIO           0x20    /* MDIO control register */
  84#define  MDIO_WRITE     0x4000  /* MDIO write */
  85#define  MDIO_READ      0x2000  /* MDIO read */
  86#define MMRD            0x24    /* MDIO read data register */
  87#define MMWD            0x28    /* MDIO write data register */
  88#define MTD_SA0         0x2C    /* TX descriptor start address 0 */
  89#define MTD_SA1         0x30    /* TX descriptor start address 1 */
  90#define MRD_SA0         0x34    /* RX descriptor start address 0 */
  91#define MRD_SA1         0x38    /* RX descriptor start address 1 */
  92#define MISR            0x3C    /* Status register */
  93#define MIER            0x40    /* INT enable register */
  94#define  MSK_INT        0x0000  /* Mask off interrupts */
  95#define  RX_FINISH      0x0001  /* RX finished */
  96#define  RX_NO_DESC     0x0002  /* No RX descriptor available */
  97#define  RX_FIFO_FULL   0x0004  /* RX FIFO full */
  98#define  RX_EARLY       0x0008  /* RX early */
  99#define  TX_FINISH      0x0010  /* TX finished */
 100#define  TX_EARLY       0x0080  /* TX early */
 101#define  EVENT_OVRFL    0x0100  /* Event counter overflow */
 102#define  LINK_CHANGED   0x0200  /* PHY link changed */
 103#define ME_CISR         0x44    /* Event counter INT status */
 104#define ME_CIER         0x48    /* Event counter INT enable  */
 105#define MR_CNT          0x50    /* Successfully received packet counter */
 106#define ME_CNT0         0x52    /* Event counter 0 */
 107#define ME_CNT1         0x54    /* Event counter 1 */
 108#define ME_CNT2         0x56    /* Event counter 2 */
 109#define ME_CNT3         0x58    /* Event counter 3 */
 110#define MT_CNT          0x5A    /* Successfully transmit packet counter */
 111#define ME_CNT4         0x5C    /* Event counter 4 */
 112#define MP_CNT          0x5E    /* Pause frame counter register */
 113#define MAR0            0x60    /* Hash table 0 */
 114#define MAR1            0x62    /* Hash table 1 */
 115#define MAR2            0x64    /* Hash table 2 */
 116#define MAR3            0x66    /* Hash table 3 */
 117#define MID_0L          0x68    /* Multicast address MID0 Low */
 118#define MID_0M          0x6A    /* Multicast address MID0 Medium */
 119#define MID_0H          0x6C    /* Multicast address MID0 High */
 120#define MID_1L          0x70    /* MID1 Low */
 121#define MID_1M          0x72    /* MID1 Medium */
 122#define MID_1H          0x74    /* MID1 High */
 123#define MID_2L          0x78    /* MID2 Low */
 124#define MID_2M          0x7A    /* MID2 Medium */
 125#define MID_2H          0x7C    /* MID2 High */
 126#define MID_3L          0x80    /* MID3 Low */
 127#define MID_3M          0x82    /* MID3 Medium */
 128#define MID_3H          0x84    /* MID3 High */
 129#define PHY_CC          0x88    /* PHY status change configuration register */
 130#define  SCEN           0x8000  /* PHY status change enable */
 131#define  PHYAD_SHIFT    8       /* PHY address shift */
 132#define  TMRDIV_SHIFT   0       /* Timer divider shift */
 133#define PHY_ST          0x8A    /* PHY status register */
 134#define MAC_SM          0xAC    /* MAC status machine */
 135#define  MAC_SM_RST     0x0002  /* MAC status machine reset */
 136#define MAC_ID          0xBE    /* Identifier register */
 137
 138#define TX_DCNT         0x80    /* TX descriptor count */
 139#define RX_DCNT         0x80    /* RX descriptor count */
 140#define MAX_BUF_SIZE    0x600
 141#define RX_DESC_SIZE    (RX_DCNT * sizeof(struct r6040_descriptor))
 142#define TX_DESC_SIZE    (TX_DCNT * sizeof(struct r6040_descriptor))
 143#define MBCR_DEFAULT    0x012A  /* MAC Bus Control Register */
 144#define MCAST_MAX       3       /* Max number multicast addresses to filter */
 145
 146#define MAC_DEF_TIMEOUT 2048    /* Default MAC read/write operation timeout */
 147
 148/* Descriptor status */
 149#define DSC_OWNER_MAC   0x8000  /* MAC is the owner of this descriptor */
 150#define DSC_RX_OK       0x4000  /* RX was successful */
 151#define DSC_RX_ERR      0x0800  /* RX PHY error */
 152#define DSC_RX_ERR_DRI  0x0400  /* RX dribble packet */
 153#define DSC_RX_ERR_BUF  0x0200  /* RX length exceeds buffer size */
 154#define DSC_RX_ERR_LONG 0x0100  /* RX length > maximum packet length */
 155#define DSC_RX_ERR_RUNT 0x0080  /* RX packet length < 64 byte */
 156#define DSC_RX_ERR_CRC  0x0040  /* RX CRC error */
 157#define DSC_RX_BCAST    0x0020  /* RX broadcast (no error) */
 158#define DSC_RX_MCAST    0x0010  /* RX multicast (no error) */
 159#define DSC_RX_MCH_HIT  0x0008  /* RX multicast hit in hash table (no error) */
 160#define DSC_RX_MIDH_HIT 0x0004  /* RX MID table hit (no error) */
 161#define DSC_RX_IDX_MID_MASK 3   /* RX mask for the index of matched MIDx */
 162
 163MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
 164        "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
 165        "Florian Fainelli <florian@openwrt.org>");
 166MODULE_LICENSE("GPL");
 167MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
 168MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
 169
 170/* RX and TX interrupts that we handle */
 171#define RX_INTS                 (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
 172#define TX_INTS                 (TX_FINISH)
 173#define INT_MASK                (RX_INTS | TX_INTS)
 174
 175struct r6040_descriptor {
 176        u16     status, len;            /* 0-3 */
 177        __le32  buf;                    /* 4-7 */
 178        __le32  ndesc;                  /* 8-B */
 179        u32     rev1;                   /* C-F */
 180        char    *vbufp;                 /* 10-13 */
 181        struct r6040_descriptor *vndescp;       /* 14-17 */
 182        struct sk_buff *skb_ptr;        /* 18-1B */
 183        u32     rev2;                   /* 1C-1F */
 184} __aligned(32);
 185
 186struct r6040_private {
 187        spinlock_t lock;                /* driver lock */
 188        struct pci_dev *pdev;
 189        struct r6040_descriptor *rx_insert_ptr;
 190        struct r6040_descriptor *rx_remove_ptr;
 191        struct r6040_descriptor *tx_insert_ptr;
 192        struct r6040_descriptor *tx_remove_ptr;
 193        struct r6040_descriptor *rx_ring;
 194        struct r6040_descriptor *tx_ring;
 195        dma_addr_t rx_ring_dma;
 196        dma_addr_t tx_ring_dma;
 197        u16     tx_free_desc;
 198        u16     mcr0;
 199        struct net_device *dev;
 200        struct mii_bus *mii_bus;
 201        struct napi_struct napi;
 202        void __iomem *base;
 203        struct phy_device *phydev;
 204        int old_link;
 205        int old_duplex;
 206};
 207
 208static char version[] = DRV_NAME
 209        ": RDC R6040 NAPI net driver,"
 210        "version "DRV_VERSION " (" DRV_RELDATE ")";
 211
 212/* Read a word data from PHY Chip */
 213static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
 214{
 215        int limit = MAC_DEF_TIMEOUT;
 216        u16 cmd;
 217
 218        iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
 219        /* Wait for the read bit to be cleared */
 220        while (limit--) {
 221                cmd = ioread16(ioaddr + MMDIO);
 222                if (!(cmd & MDIO_READ))
 223                        break;
 224                udelay(1);
 225        }
 226
 227        if (limit < 0)
 228                return -ETIMEDOUT;
 229
 230        return ioread16(ioaddr + MMRD);
 231}
 232
 233/* Write a word data from PHY Chip */
 234static int r6040_phy_write(void __iomem *ioaddr,
 235                                        int phy_addr, int reg, u16 val)
 236{
 237        int limit = MAC_DEF_TIMEOUT;
 238        u16 cmd;
 239
 240        iowrite16(val, ioaddr + MMWD);
 241        /* Write the command to the MDIO bus */
 242        iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
 243        /* Wait for the write bit to be cleared */
 244        while (limit--) {
 245                cmd = ioread16(ioaddr + MMDIO);
 246                if (!(cmd & MDIO_WRITE))
 247                        break;
 248                udelay(1);
 249        }
 250
 251        return (limit < 0) ? -ETIMEDOUT : 0;
 252}
 253
 254static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
 255{
 256        struct net_device *dev = bus->priv;
 257        struct r6040_private *lp = netdev_priv(dev);
 258        void __iomem *ioaddr = lp->base;
 259
 260        return r6040_phy_read(ioaddr, phy_addr, reg);
 261}
 262
 263static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
 264                                                int reg, u16 value)
 265{
 266        struct net_device *dev = bus->priv;
 267        struct r6040_private *lp = netdev_priv(dev);
 268        void __iomem *ioaddr = lp->base;
 269
 270        return r6040_phy_write(ioaddr, phy_addr, reg, value);
 271}
 272
 273static void r6040_free_txbufs(struct net_device *dev)
 274{
 275        struct r6040_private *lp = netdev_priv(dev);
 276        int i;
 277
 278        for (i = 0; i < TX_DCNT; i++) {
 279                if (lp->tx_insert_ptr->skb_ptr) {
 280                        pci_unmap_single(lp->pdev,
 281                                le32_to_cpu(lp->tx_insert_ptr->buf),
 282                                MAX_BUF_SIZE, PCI_DMA_TODEVICE);
 283                        dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
 284                        lp->tx_insert_ptr->skb_ptr = NULL;
 285                }
 286                lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
 287        }
 288}
 289
 290static void r6040_free_rxbufs(struct net_device *dev)
 291{
 292        struct r6040_private *lp = netdev_priv(dev);
 293        int i;
 294
 295        for (i = 0; i < RX_DCNT; i++) {
 296                if (lp->rx_insert_ptr->skb_ptr) {
 297                        pci_unmap_single(lp->pdev,
 298                                le32_to_cpu(lp->rx_insert_ptr->buf),
 299                                MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
 300                        dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
 301                        lp->rx_insert_ptr->skb_ptr = NULL;
 302                }
 303                lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
 304        }
 305}
 306
 307static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
 308                                 dma_addr_t desc_dma, int size)
 309{
 310        struct r6040_descriptor *desc = desc_ring;
 311        dma_addr_t mapping = desc_dma;
 312
 313        while (size-- > 0) {
 314                mapping += sizeof(*desc);
 315                desc->ndesc = cpu_to_le32(mapping);
 316                desc->vndescp = desc + 1;
 317                desc++;
 318        }
 319        desc--;
 320        desc->ndesc = cpu_to_le32(desc_dma);
 321        desc->vndescp = desc_ring;
 322}
 323
 324static void r6040_init_txbufs(struct net_device *dev)
 325{
 326        struct r6040_private *lp = netdev_priv(dev);
 327
 328        lp->tx_free_desc = TX_DCNT;
 329
 330        lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
 331        r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
 332}
 333
 334static int r6040_alloc_rxbufs(struct net_device *dev)
 335{
 336        struct r6040_private *lp = netdev_priv(dev);
 337        struct r6040_descriptor *desc;
 338        struct sk_buff *skb;
 339        int rc;
 340
 341        lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
 342        r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
 343
 344        /* Allocate skbs for the rx descriptors */
 345        desc = lp->rx_ring;
 346        do {
 347                skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
 348                if (!skb) {
 349                        rc = -ENOMEM;
 350                        goto err_exit;
 351                }
 352                desc->skb_ptr = skb;
 353                desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
 354                                        desc->skb_ptr->data,
 355                                        MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
 356                desc->status = DSC_OWNER_MAC;
 357                desc = desc->vndescp;
 358        } while (desc != lp->rx_ring);
 359
 360        return 0;
 361
 362err_exit:
 363        /* Deallocate all previously allocated skbs */
 364        r6040_free_rxbufs(dev);
 365        return rc;
 366}
 367
 368static void r6040_reset_mac(struct r6040_private *lp)
 369{
 370        void __iomem *ioaddr = lp->base;
 371        int limit = MAC_DEF_TIMEOUT;
 372        u16 cmd;
 373
 374        iowrite16(MAC_RST, ioaddr + MCR1);
 375        while (limit--) {
 376                cmd = ioread16(ioaddr + MCR1);
 377                if (cmd & MAC_RST)
 378                        break;
 379        }
 380
 381        /* Reset internal state machine */
 382        iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
 383        iowrite16(0, ioaddr + MAC_SM);
 384        mdelay(5);
 385}
 386
 387static void r6040_init_mac_regs(struct net_device *dev)
 388{
 389        struct r6040_private *lp = netdev_priv(dev);
 390        void __iomem *ioaddr = lp->base;
 391
 392        /* Mask Off Interrupt */
 393        iowrite16(MSK_INT, ioaddr + MIER);
 394
 395        /* Reset RDC MAC */
 396        r6040_reset_mac(lp);
 397
 398        /* MAC Bus Control Register */
 399        iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
 400
 401        /* Buffer Size Register */
 402        iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
 403
 404        /* Write TX ring start address */
 405        iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
 406        iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
 407
 408        /* Write RX ring start address */
 409        iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
 410        iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
 411
 412        /* Set interrupt waiting time and packet numbers */
 413        iowrite16(0, ioaddr + MT_ICR);
 414        iowrite16(0, ioaddr + MR_ICR);
 415
 416        /* Enable interrupts */
 417        iowrite16(INT_MASK, ioaddr + MIER);
 418
 419        /* Enable TX and RX */
 420        iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr);
 421
 422        /* Let TX poll the descriptors
 423         * we may got called by r6040_tx_timeout which has left
 424         * some unsent tx buffers */
 425        iowrite16(TM2TX, ioaddr + MTPR);
 426}
 427
 428static void r6040_tx_timeout(struct net_device *dev)
 429{
 430        struct r6040_private *priv = netdev_priv(dev);
 431        void __iomem *ioaddr = priv->base;
 432
 433        netdev_warn(dev, "transmit timed out, int enable %4.4x "
 434                "status %4.4x\n",
 435                ioread16(ioaddr + MIER),
 436                ioread16(ioaddr + MISR));
 437
 438        dev->stats.tx_errors++;
 439
 440        /* Reset MAC and re-init all registers */
 441        r6040_init_mac_regs(dev);
 442}
 443
 444static struct net_device_stats *r6040_get_stats(struct net_device *dev)
 445{
 446        struct r6040_private *priv = netdev_priv(dev);
 447        void __iomem *ioaddr = priv->base;
 448        unsigned long flags;
 449
 450        spin_lock_irqsave(&priv->lock, flags);
 451        dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
 452        dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
 453        spin_unlock_irqrestore(&priv->lock, flags);
 454
 455        return &dev->stats;
 456}
 457
 458/* Stop RDC MAC and Free the allocated resource */
 459static void r6040_down(struct net_device *dev)
 460{
 461        struct r6040_private *lp = netdev_priv(dev);
 462        void __iomem *ioaddr = lp->base;
 463        u16 *adrp;
 464
 465        /* Stop MAC */
 466        iowrite16(MSK_INT, ioaddr + MIER);      /* Mask Off Interrupt */
 467
 468        /* Reset RDC MAC */
 469        r6040_reset_mac(lp);
 470
 471        /* Restore MAC Address to MIDx */
 472        adrp = (u16 *) dev->dev_addr;
 473        iowrite16(adrp[0], ioaddr + MID_0L);
 474        iowrite16(adrp[1], ioaddr + MID_0M);
 475        iowrite16(adrp[2], ioaddr + MID_0H);
 476
 477        phy_stop(lp->phydev);
 478}
 479
 480static int r6040_close(struct net_device *dev)
 481{
 482        struct r6040_private *lp = netdev_priv(dev);
 483        struct pci_dev *pdev = lp->pdev;
 484
 485        spin_lock_irq(&lp->lock);
 486        napi_disable(&lp->napi);
 487        netif_stop_queue(dev);
 488        r6040_down(dev);
 489
 490        free_irq(dev->irq, dev);
 491
 492        /* Free RX buffer */
 493        r6040_free_rxbufs(dev);
 494
 495        /* Free TX buffer */
 496        r6040_free_txbufs(dev);
 497
 498        spin_unlock_irq(&lp->lock);
 499
 500        /* Free Descriptor memory */
 501        if (lp->rx_ring) {
 502                pci_free_consistent(pdev,
 503                                RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
 504                lp->rx_ring = NULL;
 505        }
 506
 507        if (lp->tx_ring) {
 508                pci_free_consistent(pdev,
 509                                TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
 510                lp->tx_ring = NULL;
 511        }
 512
 513        return 0;
 514}
 515
 516static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 517{
 518        struct r6040_private *lp = netdev_priv(dev);
 519
 520        if (!lp->phydev)
 521                return -EINVAL;
 522
 523        return phy_mii_ioctl(lp->phydev, rq, cmd);
 524}
 525
 526static int r6040_rx(struct net_device *dev, int limit)
 527{
 528        struct r6040_private *priv = netdev_priv(dev);
 529        struct r6040_descriptor *descptr = priv->rx_remove_ptr;
 530        struct sk_buff *skb_ptr, *new_skb;
 531        int count = 0;
 532        u16 err;
 533
 534        /* Limit not reached and the descriptor belongs to the CPU */
 535        while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
 536                /* Read the descriptor status */
 537                err = descptr->status;
 538                /* Global error status set */
 539                if (err & DSC_RX_ERR) {
 540                        /* RX dribble */
 541                        if (err & DSC_RX_ERR_DRI)
 542                                dev->stats.rx_frame_errors++;
 543                        /* Buffer length exceeded */
 544                        if (err & DSC_RX_ERR_BUF)
 545                                dev->stats.rx_length_errors++;
 546                        /* Packet too long */
 547                        if (err & DSC_RX_ERR_LONG)
 548                                dev->stats.rx_length_errors++;
 549                        /* Packet < 64 bytes */
 550                        if (err & DSC_RX_ERR_RUNT)
 551                                dev->stats.rx_length_errors++;
 552                        /* CRC error */
 553                        if (err & DSC_RX_ERR_CRC) {
 554                                spin_lock(&priv->lock);
 555                                dev->stats.rx_crc_errors++;
 556                                spin_unlock(&priv->lock);
 557                        }
 558                        goto next_descr;
 559                }
 560
 561                /* Packet successfully received */
 562                new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
 563                if (!new_skb) {
 564                        dev->stats.rx_dropped++;
 565                        goto next_descr;
 566                }
 567                skb_ptr = descptr->skb_ptr;
 568                skb_ptr->dev = priv->dev;
 569
 570                /* Do not count the CRC */
 571                skb_put(skb_ptr, descptr->len - 4);
 572                pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
 573                                        MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
 574                skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
 575
 576                /* Send to upper layer */
 577                netif_receive_skb(skb_ptr);
 578                dev->stats.rx_packets++;
 579                dev->stats.rx_bytes += descptr->len - 4;
 580
 581                /* put new skb into descriptor */
 582                descptr->skb_ptr = new_skb;
 583                descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
 584                                                descptr->skb_ptr->data,
 585                                        MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
 586
 587next_descr:
 588                /* put the descriptor back to the MAC */
 589                descptr->status = DSC_OWNER_MAC;
 590                descptr = descptr->vndescp;
 591                count++;
 592        }
 593        priv->rx_remove_ptr = descptr;
 594
 595        return count;
 596}
 597
 598static void r6040_tx(struct net_device *dev)
 599{
 600        struct r6040_private *priv = netdev_priv(dev);
 601        struct r6040_descriptor *descptr;
 602        void __iomem *ioaddr = priv->base;
 603        struct sk_buff *skb_ptr;
 604        u16 err;
 605
 606        spin_lock(&priv->lock);
 607        descptr = priv->tx_remove_ptr;
 608        while (priv->tx_free_desc < TX_DCNT) {
 609                /* Check for errors */
 610                err = ioread16(ioaddr + MLSR);
 611
 612                if (err & TX_FIFO_UNDR)
 613                        dev->stats.tx_fifo_errors++;
 614                if (err & (TX_EXCEEDC | TX_LATEC))
 615                        dev->stats.tx_carrier_errors++;
 616
 617                if (descptr->status & DSC_OWNER_MAC)
 618                        break; /* Not complete */
 619                skb_ptr = descptr->skb_ptr;
 620                pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
 621                        skb_ptr->len, PCI_DMA_TODEVICE);
 622                /* Free buffer */
 623                dev_kfree_skb_irq(skb_ptr);
 624                descptr->skb_ptr = NULL;
 625                /* To next descriptor */
 626                descptr = descptr->vndescp;
 627                priv->tx_free_desc++;
 628        }
 629        priv->tx_remove_ptr = descptr;
 630
 631        if (priv->tx_free_desc)
 632                netif_wake_queue(dev);
 633        spin_unlock(&priv->lock);
 634}
 635
 636static int r6040_poll(struct napi_struct *napi, int budget)
 637{
 638        struct r6040_private *priv =
 639                container_of(napi, struct r6040_private, napi);
 640        struct net_device *dev = priv->dev;
 641        void __iomem *ioaddr = priv->base;
 642        int work_done;
 643
 644        work_done = r6040_rx(dev, budget);
 645
 646        if (work_done < budget) {
 647                napi_complete(napi);
 648                /* Enable RX interrupt */
 649                iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
 650        }
 651        return work_done;
 652}
 653
 654/* The RDC interrupt handler. */
 655static irqreturn_t r6040_interrupt(int irq, void *dev_id)
 656{
 657        struct net_device *dev = dev_id;
 658        struct r6040_private *lp = netdev_priv(dev);
 659        void __iomem *ioaddr = lp->base;
 660        u16 misr, status;
 661
 662        /* Save MIER */
 663        misr = ioread16(ioaddr + MIER);
 664        /* Mask off RDC MAC interrupt */
 665        iowrite16(MSK_INT, ioaddr + MIER);
 666        /* Read MISR status and clear */
 667        status = ioread16(ioaddr + MISR);
 668
 669        if (status == 0x0000 || status == 0xffff) {
 670                /* Restore RDC MAC interrupt */
 671                iowrite16(misr, ioaddr + MIER);
 672                return IRQ_NONE;
 673        }
 674
 675        /* RX interrupt request */
 676        if (status & RX_INTS) {
 677                if (status & RX_NO_DESC) {
 678                        /* RX descriptor unavailable */
 679                        dev->stats.rx_dropped++;
 680                        dev->stats.rx_missed_errors++;
 681                }
 682                if (status & RX_FIFO_FULL)
 683                        dev->stats.rx_fifo_errors++;
 684
 685                if (likely(napi_schedule_prep(&lp->napi))) {
 686                        /* Mask off RX interrupt */
 687                        misr &= ~RX_INTS;
 688                        __napi_schedule(&lp->napi);
 689                }
 690        }
 691
 692        /* TX interrupt request */
 693        if (status & TX_INTS)
 694                r6040_tx(dev);
 695
 696        /* Restore RDC MAC interrupt */
 697        iowrite16(misr, ioaddr + MIER);
 698
 699        return IRQ_HANDLED;
 700}
 701
 702#ifdef CONFIG_NET_POLL_CONTROLLER
 703static void r6040_poll_controller(struct net_device *dev)
 704{
 705        disable_irq(dev->irq);
 706        r6040_interrupt(dev->irq, dev);
 707        enable_irq(dev->irq);
 708}
 709#endif
 710
 711/* Init RDC MAC */
 712static int r6040_up(struct net_device *dev)
 713{
 714        struct r6040_private *lp = netdev_priv(dev);
 715        void __iomem *ioaddr = lp->base;
 716        int ret;
 717
 718        /* Initialise and alloc RX/TX buffers */
 719        r6040_init_txbufs(dev);
 720        ret = r6040_alloc_rxbufs(dev);
 721        if (ret)
 722                return ret;
 723
 724        /* improve performance (by RDC guys) */
 725        r6040_phy_write(ioaddr, 30, 17,
 726                        (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
 727        r6040_phy_write(ioaddr, 30, 17,
 728                        ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
 729        r6040_phy_write(ioaddr, 0, 19, 0x0000);
 730        r6040_phy_write(ioaddr, 0, 30, 0x01F0);
 731
 732        /* Initialize all MAC registers */
 733        r6040_init_mac_regs(dev);
 734
 735        phy_start(lp->phydev);
 736
 737        return 0;
 738}
 739
 740
 741/* Read/set MAC address routines */
 742static void r6040_mac_address(struct net_device *dev)
 743{
 744        struct r6040_private *lp = netdev_priv(dev);
 745        void __iomem *ioaddr = lp->base;
 746        u16 *adrp;
 747
 748        /* Reset MAC */
 749        r6040_reset_mac(lp);
 750
 751        /* Restore MAC Address */
 752        adrp = (u16 *) dev->dev_addr;
 753        iowrite16(adrp[0], ioaddr + MID_0L);
 754        iowrite16(adrp[1], ioaddr + MID_0M);
 755        iowrite16(adrp[2], ioaddr + MID_0H);
 756}
 757
 758static int r6040_open(struct net_device *dev)
 759{
 760        struct r6040_private *lp = netdev_priv(dev);
 761        int ret;
 762
 763        /* Request IRQ and Register interrupt handler */
 764        ret = request_irq(dev->irq, r6040_interrupt,
 765                IRQF_SHARED, dev->name, dev);
 766        if (ret)
 767                goto out;
 768
 769        /* Set MAC address */
 770        r6040_mac_address(dev);
 771
 772        /* Allocate Descriptor memory */
 773        lp->rx_ring =
 774                pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
 775        if (!lp->rx_ring) {
 776                ret = -ENOMEM;
 777                goto err_free_irq;
 778        }
 779
 780        lp->tx_ring =
 781                pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
 782        if (!lp->tx_ring) {
 783                ret = -ENOMEM;
 784                goto err_free_rx_ring;
 785        }
 786
 787        ret = r6040_up(dev);
 788        if (ret)
 789                goto err_free_tx_ring;
 790
 791        napi_enable(&lp->napi);
 792        netif_start_queue(dev);
 793
 794        return 0;
 795
 796err_free_tx_ring:
 797        pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
 798                        lp->tx_ring_dma);
 799err_free_rx_ring:
 800        pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
 801                        lp->rx_ring_dma);
 802err_free_irq:
 803        free_irq(dev->irq, dev);
 804out:
 805        return ret;
 806}
 807
 808static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
 809                                    struct net_device *dev)
 810{
 811        struct r6040_private *lp = netdev_priv(dev);
 812        struct r6040_descriptor *descptr;
 813        void __iomem *ioaddr = lp->base;
 814        unsigned long flags;
 815
 816        /* Critical Section */
 817        spin_lock_irqsave(&lp->lock, flags);
 818
 819        /* TX resource check */
 820        if (!lp->tx_free_desc) {
 821                spin_unlock_irqrestore(&lp->lock, flags);
 822                netif_stop_queue(dev);
 823                netdev_err(dev, ": no tx descriptor\n");
 824                return NETDEV_TX_BUSY;
 825        }
 826
 827        /* Statistic Counter */
 828        dev->stats.tx_packets++;
 829        dev->stats.tx_bytes += skb->len;
 830        /* Set TX descriptor & Transmit it */
 831        lp->tx_free_desc--;
 832        descptr = lp->tx_insert_ptr;
 833        if (skb->len < ETH_ZLEN)
 834                descptr->len = ETH_ZLEN;
 835        else
 836                descptr->len = skb->len;
 837
 838        descptr->skb_ptr = skb;
 839        descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
 840                skb->data, skb->len, PCI_DMA_TODEVICE));
 841        descptr->status = DSC_OWNER_MAC;
 842
 843        skb_tx_timestamp(skb);
 844
 845        /* Trigger the MAC to check the TX descriptor */
 846        iowrite16(TM2TX, ioaddr + MTPR);
 847        lp->tx_insert_ptr = descptr->vndescp;
 848
 849        /* If no tx resource, stop */
 850        if (!lp->tx_free_desc)
 851                netif_stop_queue(dev);
 852
 853        spin_unlock_irqrestore(&lp->lock, flags);
 854
 855        return NETDEV_TX_OK;
 856}
 857
 858static void r6040_multicast_list(struct net_device *dev)
 859{
 860        struct r6040_private *lp = netdev_priv(dev);
 861        void __iomem *ioaddr = lp->base;
 862        unsigned long flags;
 863        struct netdev_hw_addr *ha;
 864        int i;
 865        u16 *adrp;
 866        u16 hash_table[4] = { 0 };
 867
 868        spin_lock_irqsave(&lp->lock, flags);
 869
 870        /* Keep our MAC Address */
 871        adrp = (u16 *)dev->dev_addr;
 872        iowrite16(adrp[0], ioaddr + MID_0L);
 873        iowrite16(adrp[1], ioaddr + MID_0M);
 874        iowrite16(adrp[2], ioaddr + MID_0H);
 875
 876        /* Clear AMCP & PROM bits */
 877        lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
 878
 879        /* Promiscuous mode */
 880        if (dev->flags & IFF_PROMISC)
 881                lp->mcr0 |= MCR0_PROMISC;
 882
 883        /* Enable multicast hash table function to
 884         * receive all multicast packets. */
 885        else if (dev->flags & IFF_ALLMULTI) {
 886                lp->mcr0 |= MCR0_HASH_EN;
 887
 888                for (i = 0; i < MCAST_MAX ; i++) {
 889                        iowrite16(0, ioaddr + MID_1L + 8 * i);
 890                        iowrite16(0, ioaddr + MID_1M + 8 * i);
 891                        iowrite16(0, ioaddr + MID_1H + 8 * i);
 892                }
 893
 894                for (i = 0; i < 4; i++)
 895                        hash_table[i] = 0xffff;
 896        }
 897        /* Use internal multicast address registers if the number of
 898         * multicast addresses is not greater than MCAST_MAX. */
 899        else if (netdev_mc_count(dev) <= MCAST_MAX) {
 900                i = 0;
 901                netdev_for_each_mc_addr(ha, dev) {
 902                        u16 *adrp = (u16 *) ha->addr;
 903                        iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
 904                        iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
 905                        iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
 906                        i++;
 907                }
 908                while (i < MCAST_MAX) {
 909                        iowrite16(0, ioaddr + MID_1L + 8 * i);
 910                        iowrite16(0, ioaddr + MID_1M + 8 * i);
 911                        iowrite16(0, ioaddr + MID_1H + 8 * i);
 912                        i++;
 913                }
 914        }
 915        /* Otherwise, Enable multicast hash table function. */
 916        else {
 917                u32 crc;
 918
 919                lp->mcr0 |= MCR0_HASH_EN;
 920
 921                for (i = 0; i < MCAST_MAX ; i++) {
 922                        iowrite16(0, ioaddr + MID_1L + 8 * i);
 923                        iowrite16(0, ioaddr + MID_1M + 8 * i);
 924                        iowrite16(0, ioaddr + MID_1H + 8 * i);
 925                }
 926
 927                /* Build multicast hash table */
 928                netdev_for_each_mc_addr(ha, dev) {
 929                        u8 *addrs = ha->addr;
 930
 931                        crc = ether_crc(ETH_ALEN, addrs);
 932                        crc >>= 26;
 933                        hash_table[crc >> 4] |= 1 << (crc & 0xf);
 934                }
 935        }
 936
 937        iowrite16(lp->mcr0, ioaddr + MCR0);
 938
 939        /* Fill the MAC hash tables with their values */
 940        if (lp->mcr0 & MCR0_HASH_EN) {
 941                iowrite16(hash_table[0], ioaddr + MAR0);
 942                iowrite16(hash_table[1], ioaddr + MAR1);
 943                iowrite16(hash_table[2], ioaddr + MAR2);
 944                iowrite16(hash_table[3], ioaddr + MAR3);
 945        }
 946
 947        spin_unlock_irqrestore(&lp->lock, flags);
 948}
 949
 950static void netdev_get_drvinfo(struct net_device *dev,
 951                        struct ethtool_drvinfo *info)
 952{
 953        struct r6040_private *rp = netdev_priv(dev);
 954
 955        strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
 956        strlcpy(info->version, DRV_VERSION, sizeof(info->version));
 957        strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info));
 958}
 959
 960static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 961{
 962        struct r6040_private *rp = netdev_priv(dev);
 963
 964        return  phy_ethtool_gset(rp->phydev, cmd);
 965}
 966
 967static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 968{
 969        struct r6040_private *rp = netdev_priv(dev);
 970
 971        return phy_ethtool_sset(rp->phydev, cmd);
 972}
 973
 974static const struct ethtool_ops netdev_ethtool_ops = {
 975        .get_drvinfo            = netdev_get_drvinfo,
 976        .get_settings           = netdev_get_settings,
 977        .set_settings           = netdev_set_settings,
 978        .get_link               = ethtool_op_get_link,
 979        .get_ts_info            = ethtool_op_get_ts_info,
 980};
 981
 982static const struct net_device_ops r6040_netdev_ops = {
 983        .ndo_open               = r6040_open,
 984        .ndo_stop               = r6040_close,
 985        .ndo_start_xmit         = r6040_start_xmit,
 986        .ndo_get_stats          = r6040_get_stats,
 987        .ndo_set_rx_mode        = r6040_multicast_list,
 988        .ndo_change_mtu         = eth_change_mtu,
 989        .ndo_validate_addr      = eth_validate_addr,
 990        .ndo_set_mac_address    = eth_mac_addr,
 991        .ndo_do_ioctl           = r6040_ioctl,
 992        .ndo_tx_timeout         = r6040_tx_timeout,
 993#ifdef CONFIG_NET_POLL_CONTROLLER
 994        .ndo_poll_controller    = r6040_poll_controller,
 995#endif
 996};
 997
 998static void r6040_adjust_link(struct net_device *dev)
 999{
1000        struct r6040_private *lp = netdev_priv(dev);

1001        struct phy_device *phydev = lp->phydev;
1002        int status_changed = 0;
1003        void __iomem *ioaddr = lp->base;
1004
1005        BUG_ON(!phydev);
1006
1007        if (lp->old_link != phydev->link) {
1008                status_changed = 1;
1009                lp->old_link = phydev->link;
1010        }
1011
1012        /* reflect duplex change */
1013        if (phydev->link && (lp->old_duplex != phydev->duplex)) {
1014                lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);
1015                iowrite16(lp->mcr0, ioaddr);
1016
1017                status_changed = 1;
1018                lp->old_duplex = phydev->duplex;
1019        }
1020
1021        if (status_changed) {
1022                pr_info("%s: link %s", dev->name, phydev->link ?
1023                        "UP" : "DOWN");
1024                if (phydev->link)
1025                        pr_cont(" - %d/%s", phydev->speed,
1026                        DUPLEX_FULL == phydev->duplex ? "full" : "half");
1027                pr_cont("\n");
1028        }
1029}
1030
1031static int r6040_mii_probe(struct net_device *dev)
1032{
1033        struct r6040_private *lp = netdev_priv(dev);
1034        struct phy_device *phydev = NULL;
1035
1036        phydev = phy_find_first(lp->mii_bus);
1037        if (!phydev) {
1038                dev_err(&lp->pdev->dev, "no PHY found\n");
1039                return -ENODEV;
1040        }
1041
1042        phydev = phy_connect(dev, phydev_name(phydev), &r6040_adjust_link,
1043                             PHY_INTERFACE_MODE_MII);
1044
1045        if (IS_ERR(phydev)) {
1046                dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1047                return PTR_ERR(phydev);
1048        }
1049
1050        /* mask with MAC supported features */
1051        phydev->supported &= (SUPPORTED_10baseT_Half
1052                                | SUPPORTED_10baseT_Full
1053                                | SUPPORTED_100baseT_Half
1054                                | SUPPORTED_100baseT_Full
1055                                | SUPPORTED_Autoneg
1056                                | SUPPORTED_MII
1057                                | SUPPORTED_TP);
1058
1059        phydev->advertising = phydev->supported;
1060        lp->phydev = phydev;
1061        lp->old_link = 0;
1062        lp->old_duplex = -1;
1063
1064        phy_attached_info(phydev);
1065
1066        return 0;
1067}
1068
1069static int r6040_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1070{
1071        struct net_device *dev;
1072        struct r6040_private *lp;
1073        void __iomem *ioaddr;
1074        int err, io_size = R6040_IO_SIZE;
1075        static int card_idx = -1;
1076        int bar = 0;
1077        u16 *adrp;
1078
1079        pr_info("%s\n", version);
1080
1081        err = pci_enable_device(pdev);
1082        if (err)
1083                goto err_out;
1084
1085        /* this should always be supported */
1086        err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1087        if (err) {
1088                dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1089                                "not supported by the card\n");
1090                goto err_out_disable_dev;
1091        }
1092        err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1093        if (err) {
1094                dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1095                                "not supported by the card\n");
1096                goto err_out_disable_dev;
1097        }
1098
1099        /* IO Size check */
1100        if (pci_resource_len(pdev, bar) < io_size) {
1101                dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1102                err = -EIO;
1103                goto err_out_disable_dev;
1104        }
1105
1106        pci_set_master(pdev);
1107
1108        dev = alloc_etherdev(sizeof(struct r6040_private));
1109        if (!dev) {
1110                err = -ENOMEM;
1111                goto err_out_disable_dev;
1112        }
1113        SET_NETDEV_DEV(dev, &pdev->dev);
1114        lp = netdev_priv(dev);
1115
1116        err = pci_request_regions(pdev, DRV_NAME);
1117
1118        if (err) {
1119                dev_err(&pdev->dev, "Failed to request PCI regions\n");
1120                goto err_out_free_dev;
1121        }
1122
1123        ioaddr = pci_iomap(pdev, bar, io_size);
1124        if (!ioaddr) {
1125                dev_err(&pdev->dev, "ioremap failed for device\n");
1126                err = -EIO;
1127                goto err_out_free_res;
1128        }
1129
1130        /* If PHY status change register is still set to zero it means the
1131         * bootloader didn't initialize it, so we set it to:
1132         * - enable phy status change
1133         * - enable all phy addresses
1134         * - set to lowest timer divider */
1135        if (ioread16(ioaddr + PHY_CC) == 0)
1136                iowrite16(SCEN | PHY_MAX_ADDR << PHYAD_SHIFT |
1137                                7 << TMRDIV_SHIFT, ioaddr + PHY_CC);
1138
1139        /* Init system & device */
1140        lp->base = ioaddr;
1141        dev->irq = pdev->irq;
1142
1143        spin_lock_init(&lp->lock);
1144        pci_set_drvdata(pdev, dev);
1145
1146        /* Set MAC address */
1147        card_idx++;
1148
1149        adrp = (u16 *)dev->dev_addr;
1150        adrp[0] = ioread16(ioaddr + MID_0L);
1151        adrp[1] = ioread16(ioaddr + MID_0M);
1152        adrp[2] = ioread16(ioaddr + MID_0H);
1153
1154        /* Some bootloader/BIOSes do not initialize
1155         * MAC address, warn about that */
1156        if (!(adrp[0] || adrp[1] || adrp[2])) {
1157                netdev_warn(dev, "MAC address not initialized, "
1158                                        "generating random\n");
1159                eth_hw_addr_random(dev);
1160        }
1161
1162        /* Link new device into r6040_root_dev */
1163        lp->pdev = pdev;
1164        lp->dev = dev;
1165
1166        /* Init RDC private data */
1167        lp->mcr0 = MCR0_XMTEN | MCR0_RCVEN;
1168
1169        /* The RDC-specific entries in the device structure. */
1170        dev->netdev_ops = &r6040_netdev_ops;
1171        dev->ethtool_ops = &netdev_ethtool_ops;
1172        dev->watchdog_timeo = TX_TIMEOUT;
1173
1174        netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1175
1176        lp->mii_bus = mdiobus_alloc();
1177        if (!lp->mii_bus) {
1178                dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
1179                err = -ENOMEM;
1180                goto err_out_unmap;
1181        }
1182
1183        lp->mii_bus->priv = dev;
1184        lp->mii_bus->read = r6040_mdiobus_read;
1185        lp->mii_bus->write = r6040_mdiobus_write;
1186        lp->mii_bus->name = "r6040_eth_mii";
1187        snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1188                dev_name(&pdev->dev), card_idx);
1189
1190        err = mdiobus_register(lp->mii_bus);
1191        if (err) {
1192                dev_err(&pdev->dev, "failed to register MII bus\n");
1193                goto err_out_mdio;
1194        }
1195
1196        err = r6040_mii_probe(dev);
1197        if (err) {
1198                dev_err(&pdev->dev, "failed to probe MII bus\n");
1199                goto err_out_mdio_unregister;
1200        }
1201
1202        /* Register net device. After this dev->name assign */
1203        err = register_netdev(dev);
1204        if (err) {
1205                dev_err(&pdev->dev, "Failed to register net device\n");
1206                goto err_out_mdio_unregister;
1207        }
1208        return 0;
1209
1210err_out_mdio_unregister:
1211        mdiobus_unregister(lp->mii_bus);
1212err_out_mdio:
1213        mdiobus_free(lp->mii_bus);
1214err_out_unmap:
1215        netif_napi_del(&lp->napi);
1216        pci_iounmap(pdev, ioaddr);
1217err_out_free_res:
1218        pci_release_regions(pdev);
1219err_out_free_dev:
1220        free_netdev(dev);
1221err_out_disable_dev:
1222        pci_disable_device(pdev);
1223err_out:
1224        return err;
1225}
1226
1227static void r6040_remove_one(struct pci_dev *pdev)
1228{
1229        struct net_device *dev = pci_get_drvdata(pdev);
1230        struct r6040_private *lp = netdev_priv(dev);
1231
1232        unregister_netdev(dev);
1233        mdiobus_unregister(lp->mii_bus);
1234        mdiobus_free(lp->mii_bus);
1235        netif_napi_del(&lp->napi);
1236        pci_iounmap(pdev, lp->base);
1237        pci_release_regions(pdev);
1238        free_netdev(dev);
1239        pci_disable_device(pdev);
1240}
1241
1242
1243static const struct pci_device_id r6040_pci_tbl[] = {
1244        { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1245        { 0 }
1246};
1247MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1248
1249static struct pci_driver r6040_driver = {
1250        .name           = DRV_NAME,
1251        .id_table       = r6040_pci_tbl,
1252        .probe          = r6040_init_one,
1253        .remove         = r6040_remove_one,
1254};
1255
1256module_pci_driver(r6040_driver);
1257