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15#ifndef __RTL8188E_HAL_H__
16#define __RTL8188E_HAL_H__
17
18
19
20#include "rtl8188e_spec.h"
21#include "Hal8188EPhyReg.h"
22#include "Hal8188EPhyCfg.h"
23#include "rtl8188e_dm.h"
24#include "rtl8188e_recv.h"
25#include "rtl8188e_xmit.h"
26#include "rtl8188e_cmd.h"
27#include "pwrseq.h"
28#include "rtw_efuse.h"
29#include "rtw_sreset.h"
30#include "odm_precomp.h"
31
32
33#define Rtl8188E_FwImageArray Rtl8188EFwImgArray
34#define Rtl8188E_FWImgArrayLength Rtl8188EFWImgArrayLength
35
36#define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin"
37#define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt"
38#define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt"
39#define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt"
40#define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt"
41#define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt"
42#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt"
43#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt"
44
45
46#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow
47#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow
48#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow
49#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow
50#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow
51#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow
52#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow
53#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow
54#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow
55
56#define DRVINFO_SZ 4
57#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
58
59
60#define FW_8188E_SIZE 0x4000
61#define FW_8188E_START_ADDRESS 0x1000
62#define FW_8188E_END_ADDRESS 0x1FFF
63
64#define MAX_PAGE_SIZE 4096
65
66#define IS_FW_HEADER_EXIST(_pFwHdr) \
67 ((le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x92C0 || \
68 (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88C0 || \
69 (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x2300 || \
70 (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88E0)
71
72#define DRIVER_EARLY_INT_TIME 0x05
73#define BCN_DMA_ATIME_INT_TIME 0x02
74
75enum usb_rx_agg_mode {
76 USB_RX_AGG_DISABLE,
77 USB_RX_AGG_DMA,
78 USB_RX_AGG_USB,
79 USB_RX_AGG_MIX
80};
81
82#define MAX_RX_DMA_BUFFER_SIZE_88E \
83 0x2400
84
85
86#define MAX_TX_REPORT_BUFFER_SIZE 0x0400
87
88
89
90#define MAX_TX_QUEUE 9
91
92#define TX_SELE_HQ BIT(0)
93#define TX_SELE_LQ BIT(1)
94#define TX_SELE_NQ BIT(2)
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102
103#define TX_TOTAL_PAGE_NUMBER_88E 0xA9
104
105#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
106
107
108#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER \
109 TX_TOTAL_PAGE_NUMBER_88E
110#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E \
111 (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1)
112
113
114#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
115#define CHIP_BONDING_92C_1T2R 0x1
116#define CHIP_BONDING_88C_USB_MCARD 0x2
117#define CHIP_BONDING_88C_USB_HP 0x1
118#include "HalVerDef.h"
119#include "hal_com.h"
120
121
122enum ChannelPlan {
123 CHPL_FCC = 0,
124 CHPL_IC = 1,
125 CHPL_ETSI = 2,
126 CHPL_SPA = 3,
127 CHPL_FRANCE = 4,
128 CHPL_MKK = 5,
129 CHPL_MKK1 = 6,
130 CHPL_ISRAEL = 7,
131 CHPL_TELEC = 8,
132 CHPL_GLOBAL = 9,
133 CHPL_WORLD = 10,
134};
135
136struct txpowerinfo24g {
137 u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
138 u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
139
140 s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
141 s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
142 s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
143 s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
144};
145
146#define EFUSE_REAL_CONTENT_LEN 512
147#define EFUSE_MAX_SECTION 16
148#define EFUSE_IC_ID_OFFSET 506
149#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
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157
158#define EFUSE_OOB_PROTECT_BYTES 15
159
160#define HWSET_MAX_SIZE_88E 512
161
162#define EFUSE_REAL_CONTENT_LEN_88E 256
163#define EFUSE_MAP_LEN_88E 512
164#define EFUSE_MAP_LEN EFUSE_MAP_LEN_88E
165#define EFUSE_MAX_SECTION_88E 64
166#define EFUSE_MAX_WORD_UNIT_88E 4
167#define EFUSE_IC_ID_OFFSET_88E 506
168#define AVAILABLE_EFUSE_ADDR_88E(addr) \
169 (addr < EFUSE_REAL_CONTENT_LEN_88E)
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175
176#define EFUSE_OOB_PROTECT_BYTES_88E 18
177#define EFUSE_PROTECT_BYTES_BANK_88E 16
178
179
180#define EFUSE_BT_REAL_CONTENT_LEN 1536
181#define EFUSE_BT_MAP_LEN 1024
182#define EFUSE_BT_MAX_SECTION 128
183
184#define EFUSE_PROTECT_BYTES_BANK 16
185
186struct hal_data_8188e {
187 struct HAL_VERSION VersionID;
188 u16 CustomerID;
189 u16 FirmwareVersion;
190 u16 FirmwareVersionRev;
191 u16 FirmwareSubVersion;
192 u16 FirmwareSignature;
193 u8 PGMaxGroup;
194
195 u32 ReceiveConfig;
196 enum wireless_mode CurrentWirelessMode;
197 enum ht_channel_width CurrentChannelBW;
198 u8 CurrentChannel;
199 u8 nCur40MhzPrimeSC;
200
201 u16 BasicRateSet;
202
203
204 u8 rf_chip;
205 u8 rf_type;
206 u8 NumTotalRFPath;
207
208 u8 BoardType;
209
210
211 u16 EEPROMVID;
212 u16 EEPROMPID;
213 u16 EEPROMSVID;
214 u16 EEPROMSDID;
215 u8 EEPROMCustomerID;
216 u8 EEPROMSubCustomerID;
217 u8 EEPROMVersion;
218 u8 EEPROMRegulatory;
219
220 u8 bTXPowerDataReadFromEEPORM;
221 u8 EEPROMThermalMeter;
222 u8 bAPKThermalMeterIgnore;
223
224 bool EepromOrEfuse;
225
226 u8 EfuseMap[2][HWSET_MAX_SIZE_512];
227 u8 EfuseUsedPercentage;
228 struct efuse_hal EfuseHal;
229
230 u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
231 u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
232
233 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
234 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
235 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
236 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
237
238 u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
239
240 u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
241
242 u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
243
244 u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
245
246 u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
247
248 u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
249 u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
250
251 u8 LegacyHTTxPowerDiff;
252
253 u8 CurrentCckTxPwrIdx;
254 u8 CurrentOfdm24GTxPwrIdx;
255 u8 CurrentBW2024GTxPwrIdx;
256 u8 CurrentBW4024GTxPwrIdx;
257
258
259
260 u8 framesync;
261 u32 framesyncC34;
262 u8 framesyncMonitor;
263 u8 DefaultInitialGain[4];
264 u8 pwrGroupCnt;
265 u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
266 u32 CCKTxPowerLevelOriginalOffset;
267
268 u8 CrystalCap;
269 u32 AntennaTxPath;
270 u32 AntennaRxPath;
271 u8 BluetoothCoexist;
272 u8 ExternalPA;
273
274 u8 bLedOpenDrain;
275
276 u8 b1x1RecvCombine;
277
278 u32 AcParam_BE;
279
280 struct bb_reg_def PHYRegDef[4];
281
282 u32 RfRegChnlVal[2];
283
284
285 bool bRDGEnable;
286
287
288 u8 LastHMEBoxNum;
289
290 u8 RegTxPause;
291
292 u32 RegBcnCtrlVal;
293 u8 RegFwHwTxQCtrl;
294 u8 RegReg542;
295 u8 RegCR_1;
296
297 struct dm_priv dmpriv;
298 struct odm_dm_struct odmpriv;
299 struct sreset_priv srestpriv;
300
301 u8 CurAntenna;
302 u8 AntDivCfg;
303 u8 TRxAntDivType;
304
305
306 u8 bDumpRxPkt;
307 u8 bDumpTxPkt;
308 u8 FwRsvdPageStartOffset;
309
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312 bool pwrdown;
313
314
315 u32 interfaceIndex;
316
317 u8 OutEpQueueSel;
318 u8 OutEpNumber;
319
320
321 bool UsbRxHighSpeedMode;
322
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325
326 bool SlimComboDbg;
327
328 u16 EfuseUsedBytes;
329
330
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332 u8 bMacPwrCtrlOn;
333
334 u32 UsbBulkOutSize;
335
336
337 u32 IntArray[3];
338 u32 IntrMask[3];
339 u8 C2hArray[16];
340 u8 UsbTxAggMode;
341 u8 UsbTxAggDescNum;
342 u16 HwRxPageSize;
343 u32 MaxUsbRxAggBlock;
344
345 enum usb_rx_agg_mode UsbRxAggMode;
346 u8 UsbRxAggBlockCount;
347
348
349 u8 UsbRxAggBlockTimeout;
350 u8 UsbRxAggPageCount;
351 u8 UsbRxAggPageTimeout;
352};
353
354#define GET_HAL_DATA(__pAdapter) \
355 ((struct hal_data_8188e *)((__pAdapter)->HalData))
356#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
357
358
359void _8051Reset88E(struct adapter *padapter);
360void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
361
362
363s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
364
365
366void Hal_InitPGData88E(struct adapter *padapter);
367void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
368void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
369 bool AutoLoadFail);
370
371void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo,
372 bool AutoLoadFail);
373void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
374 bool AutoLoadFail);
375void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo,
376 bool AutoLoadFail);
377void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent,
378 bool AutoLoadFail);
379void Hal_ReadThermalMeter_88E(struct adapter *dapter, u8 *PROMContent,
380 bool AutoloadFail);
381void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
382 bool AutoLoadFail);
383void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo,
384 bool AutoLoadFail);
385void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
386 bool AutoLoadFail);
387
388void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc);
389
390
391
392void rtl8188e_start_thread(struct adapter *padapter);
393void rtl8188e_stop_thread(struct adapter *padapter);
394
395s32 iol_execute(struct adapter *padapter, u8 control);
396void iol_mode_enable(struct adapter *padapter, u8 enable);
397s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
398void rtw_cancel_all_timer(struct adapter *padapter);
399
400#endif
401