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20#ifndef R8192_HW
21#define R8192_HW
22
23typedef enum _VERSION_819xU{
24 VERSION_819xU_A,
25 VERSION_819xU_B,
26 VERSION_819xU_C,
27} VERSION_819xU, *PVERSION_819xU;
28
29typedef enum _RT_RF_TYPE_DEF
30{
31 RF_1T2R = 0,
32 RF_2T4R,
33
34 RF_819X_MAX_TYPE
35}RT_RF_TYPE_DEF;
36
37
38typedef enum _BaseBand_Config_Type{
39 BaseBand_Config_PHY_REG = 0,
40 BaseBand_Config_AGC_TAB = 1,
41}BaseBand_Config_Type, *PBaseBand_Config_Type;
42#define RTL8187_REQT_READ 0xc0
43#define RTL8187_REQT_WRITE 0x40
44#define RTL8187_REQ_GET_REGS 0x05
45#define RTL8187_REQ_SET_REGS 0x05
46
47#define MAX_TX_URB 5
48#define MAX_RX_URB 16
49
50#define R8180_MAX_RETRY 255
51
52
53#define RX_URB_SIZE 9100
54
55#define BB_ANTATTEN_CHAN14 0x0c
56#define BB_ANTENNA_B 0x40
57
58#define BB_HOST_BANG BIT(30)
59#define BB_HOST_BANG_EN BIT(2)
60#define BB_HOST_BANG_CLK BIT(1)
61#define BB_HOST_BANG_RW BIT(3)
62#define BB_HOST_BANG_DATA 1
63
64
65#define AFR 0x010
66#define AFR_CardBEn BIT(0)
67#define AFR_CLKRUN_SEL BIT(1)
68#define AFR_FuncRegEn BIT(2)
69#define RTL8190_EEPROM_ID 0x8129
70#define EEPROM_VID 0x02
71#define EEPROM_PID 0x04
72#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
73
74#define EEPROM_TxPowerDiff 0x1F
75#define EEPROM_ThermalMeter 0x20
76#define EEPROM_PwDiff 0x21
77#define EEPROM_CrystalCap 0x22
78
79#define EEPROM_TxPwIndex_CCK 0x23
80#define EEPROM_TxPwIndex_OFDM_24G 0x24
81#define EEPROM_TxPwIndex_CCK_V1 0x29
82#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C
83#define EEPROM_TxPwIndex_Ver 0x27
84
85#define EEPROM_Default_TxPowerDiff 0x0
86#define EEPROM_Default_ThermalMeter 0x7
87#define EEPROM_Default_PwDiff 0x4
88#define EEPROM_Default_CrystalCap 0x5
89#define EEPROM_Default_TxPower 0x1010
90#define EEPROM_Customer_ID 0x7B
91#define EEPROM_ChannelPlan 0x16
92#define EEPROM_IC_VER 0x7d
93#define EEPROM_CRC 0x7e
94
95#define EEPROM_CID_DEFAULT 0x0
96#define EEPROM_CID_CAMEO 0x1
97#define EEPROM_CID_RUNTOP 0x2
98#define EEPROM_CID_Senao 0x3
99#define EEPROM_CID_TOSHIBA 0x4
100#define EEPROM_CID_NetCore 0x5
101#define EEPROM_CID_Nettronix 0x6
102#define EEPROM_CID_Pronet 0x7
103#define EEPROM_CID_DLINK 0x8
104
105#define AC_PARAM_TXOP_LIMIT_OFFSET 16
106#define AC_PARAM_ECW_MAX_OFFSET 12
107#define AC_PARAM_ECW_MIN_OFFSET 8
108#define AC_PARAM_AIFS_OFFSET 0
109
110
111enum _RTL8192Usb_HW {
112
113 PCIF = 0x009,
114#define BB_GLOBAL_RESET_BIT 0x1
115 BB_GLOBAL_RESET = 0x020,
116 BSSIDR = 0x02E,
117 CMDR = 0x037,
118#define CR_RST 0x10
119#define CR_RE 0x08
120#define CR_TE 0x04
121#define CR_MulRW 0x01
122 SIFS = 0x03E,
123 TCR = 0x040,
124
125#define TCR_MXDMA_2048 7
126#define TCR_LRL_OFFSET 0
127#define TCR_SRL_OFFSET 8
128#define TCR_MXDMA_OFFSET 21
129#define TCR_SAT BIT(24)
130 RCR = 0x044,
131#define MAC_FILTER_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(5) | \
132 BIT(12) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | \
133 BIT(22) | BIT(23))
134#define RX_FIFO_THRESHOLD_MASK (BIT(13) | BIT(14) | BIT(15))
135#define RX_FIFO_THRESHOLD_SHIFT 13
136#define RX_FIFO_THRESHOLD_128 3
137#define RX_FIFO_THRESHOLD_256 4
138#define RX_FIFO_THRESHOLD_512 5
139#define RX_FIFO_THRESHOLD_1024 6
140#define RX_FIFO_THRESHOLD_NONE 7
141#define MAX_RX_DMA_MASK (BIT(8) | BIT(9) | BIT(10))
142#define RCR_MXDMA_OFFSET 8
143#define RCR_FIFO_OFFSET 13
144#define RCR_ONLYERLPKT BIT(31)
145#define RCR_ENCS2 BIT(30)
146#define RCR_ENCS1 BIT(29)
147#define RCR_ENMBID BIT(27)
148#define RCR_ACKTXBW (BIT(24) | BIT(25))
149#define RCR_CBSSID BIT(23)
150#define RCR_APWRMGT BIT(22)
151#define RCR_ADD3 BIT(21)
152#define RCR_AMF BIT(20)
153#define RCR_ACF BIT(19)
154#define RCR_ADF BIT(18)
155#define RCR_RXFTH BIT(13)
156#define RCR_AICV BIT(12)
157#define RCR_ACRC32 BIT(5)
158#define RCR_AB BIT(3)
159#define RCR_AM BIT(2)
160#define RCR_APM BIT(1)
161#define RCR_AAP BIT(0)
162 SLOT_TIME = 0x049,
163 ACK_TIMEOUT = 0x04c,
164 PIFS_TIME = 0x04d,
165 USTIME = 0x04e,
166 EDCAPARA_BE = 0x050,
167 EDCAPARA_BK = 0x054,
168 EDCAPARA_VO = 0x058,
169 EDCAPARA_VI = 0x05C,
170 RFPC = 0x05F,
171 CWRR = 0x060,
172 BCN_TCFG = 0x062,
173#define BCN_TCFG_CW_SHIFT 8
174#define BCN_TCFG_IFS 0
175 BCN_INTERVAL = 0x070,
176 ATIMWND = 0x072,
177 BCN_DRV_EARLY_INT = 0x074,
178 BCN_DMATIME = 0x076,
179 BCN_ERR_THRESH = 0x078,
180 RWCAM = 0x0A0,
181 WCAMI = 0x0A4,
182 RCAMO = 0x0A8,
183 SECR = 0x0B0,
184#define SCR_TxUseDK BIT(0)
185#define SCR_RxUseDK BIT(1)
186#define SCR_TxEncEnable BIT(2)
187#define SCR_RxDecEnable BIT(3)
188#define SCR_SKByA2 BIT(4)
189#define SCR_NoSKMC BIT(5)
190#define SCR_UseDK 0x01
191#define SCR_TxSecEnable 0x02
192#define SCR_RxSecEnable 0x04
193 TPPoll = 0x0fd,
194 PSR = 0x0ff,
195#define CPU_CCK_LOOPBACK 0x00030000
196#define CPU_GEN_SYSTEM_RESET 0x00000001
197#define CPU_GEN_FIRMWARE_RESET 0x00000008
198#define CPU_GEN_BOOT_RDY 0x00000010
199#define CPU_GEN_FIRM_RDY 0x00000020
200#define CPU_GEN_PUT_CODE_OK 0x00000080
201#define CPU_GEN_BB_RST 0x00000100
202#define CPU_GEN_PWR_STB_CPU 0x00000004
203#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF
204#define CPU_GEN_NO_LOOPBACK_SET 0x00080000
205
206
207
208
209#define CPU_CCK_LOOPBACK 0x00030000
210#define CPU_GEN_SYSTEM_RESET 0x00000001
211#define CPU_GEN_FIRMWARE_RESET 0x00000008
212#define CPU_GEN_BOOT_RDY 0x00000010
213#define CPU_GEN_FIRM_RDY 0x00000020
214#define CPU_GEN_PUT_CODE_OK 0x00000080
215#define CPU_GEN_BB_RST 0x00000100
216#define CPU_GEN_PWR_STB_CPU 0x00000004
217#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF
218#define CPU_GEN_NO_LOOPBACK_SET 0x00080000
219 CPU_GEN = 0x100,
220 LED1Cfg = 0x154,
221 LED0Cfg = 0x155,
222
223 AcmAvg = 0x170,
224 AcmHwCtrl = 0x171,
225
226
227
228
229
230#define AcmHw_HwEn BIT(0)
231#define AcmHw_BeqEn BIT(1)
232#define AcmHw_ViqEn BIT(2)
233#define AcmHw_VoqEn BIT(3)
234#define AcmHw_BeqStatus BIT(4)
235#define AcmHw_ViqStatus BIT(5)
236#define AcmHw_VoqStatus BIT(6)
237
238 AcmFwCtrl = 0x172,
239 AES_11N_FIX = 0x173,
240 VOAdmTime = 0x174,
241 VIAdmTime = 0x178,
242 BEAdmTime = 0x17C,
243 RQPN1 = 0x180,
244 RQPN2 = 0x184,
245 RQPN3 = 0x188,
246
247 QPNR = 0x1D0,
248 BQDA = 0x200,
249 HQDA = 0x204,
250 CQDA = 0x208,
251 MQDA = 0x20C,
252 HCCAQDA = 0x210,
253 VOQDA = 0x214,
254 VIQDA = 0x218,
255 BEQDA = 0x21C,
256 BKQDA = 0x220,
257 RCQDA = 0x224,
258 RDQDA = 0x228,
259
260 MAR0 = 0x240,
261 MAR4 = 0x244,
262
263 CCX_PERIOD = 0x250,
264 CLM_RESULT = 0x251,
265 NHM_PERIOD = 0x252,
266
267 NHM_THRESHOLD0 = 0x253,
268 NHM_THRESHOLD1 = 0x254,
269 NHM_THRESHOLD2 = 0x255,
270 NHM_THRESHOLD3 = 0x256,
271 NHM_THRESHOLD4 = 0x257,
272 NHM_THRESHOLD5 = 0x258,
273 NHM_THRESHOLD6 = 0x259,
274
275 MCTRL = 0x25A,
276
277 NHM_RPI_COUNTER0 = 0x264,
278 NHM_RPI_COUNTER1 = 0x265,
279 NHM_RPI_COUNTER2 = 0x266,
280 NHM_RPI_COUNTER3 = 0x267,
281 NHM_RPI_COUNTER4 = 0x268,
282 NHM_RPI_COUNTER5 = 0x269,
283 NHM_RPI_COUNTER6 = 0x26A,
284 NHM_RPI_COUNTER7 = 0x26B,
285#define BW_OPMODE_11J BIT(0)
286#define BW_OPMODE_5G BIT(1)
287#define BW_OPMODE_20MHZ BIT(2)
288 BW_OPMODE = 0x300,
289 MSR = 0x303,
290#define MSR_LINK_MASK (BIT(0)|BIT(1))
291#define MSR_LINK_MANAGED 2
292#define MSR_LINK_NONE 0
293#define MSR_LINK_SHIFT 0
294#define MSR_LINK_ADHOC 1
295#define MSR_LINK_MASTER 3
296#define MSR_LINK_ENEDCA BIT(4)
297 RETRY_LIMIT = 0x304,
298#define RETRY_LIMIT_SHORT_SHIFT 8
299#define RETRY_LIMIT_LONG_SHIFT 0
300 TSFR = 0x308,
301 RRSR = 0x310,
302#define RRSR_RSC_OFFSET 21
303#define RRSR_SHORT_OFFSET 23
304#define RRSR_RSC_DUPLICATE 0x600000
305#define RRSR_RSC_LOWSUBCHNL 0x400000
306#define RRSR_RSC_UPSUBCHANL 0x200000
307#define RRSR_SHORT 0x800000
308#define RRSR_1M BIT(0)
309#define RRSR_2M BIT(1)
310#define RRSR_5_5M BIT(2)
311#define RRSR_11M BIT(3)
312#define RRSR_6M BIT(4)
313#define RRSR_9M BIT(5)
314#define RRSR_12M BIT(6)
315#define RRSR_18M BIT(7)
316#define RRSR_24M BIT(8)
317#define RRSR_36M BIT(9)
318#define RRSR_48M BIT(10)
319#define RRSR_54M BIT(11)
320#define RRSR_MCS0 BIT(12)
321#define RRSR_MCS1 BIT(13)
322#define RRSR_MCS2 BIT(14)
323#define RRSR_MCS3 BIT(15)
324#define RRSR_MCS4 BIT(16)
325#define RRSR_MCS5 BIT(17)
326#define RRSR_MCS6 BIT(18)
327#define RRSR_MCS7 BIT(19)
328#define BRSR_AckShortPmb BIT(23)
329 RATR0 = 0x320,
330 UFWP = 0x318,
331 DRIVER_RSSI = 0x32c,
332
333
334
335
336#define RATR_1M 0x00000001
337#define RATR_2M 0x00000002
338#define RATR_55M 0x00000004
339#define RATR_11M 0x00000008
340
341#define RATR_6M 0x00000010
342#define RATR_9M 0x00000020
343#define RATR_12M 0x00000040
344#define RATR_18M 0x00000080
345#define RATR_24M 0x00000100
346#define RATR_36M 0x00000200
347#define RATR_48M 0x00000400
348#define RATR_54M 0x00000800
349
350#define RATR_MCS0 0x00001000
351#define RATR_MCS1 0x00002000
352#define RATR_MCS2 0x00004000
353#define RATR_MCS3 0x00008000
354#define RATR_MCS4 0x00010000
355#define RATR_MCS5 0x00020000
356#define RATR_MCS6 0x00040000
357#define RATR_MCS7 0x00080000
358
359#define RATR_MCS8 0x00100000
360#define RATR_MCS9 0x00200000
361#define RATR_MCS10 0x00400000
362#define RATR_MCS11 0x00800000
363#define RATR_MCS12 0x01000000
364#define RATR_MCS13 0x02000000
365#define RATR_MCS14 0x04000000
366#define RATR_MCS15 0x08000000
367
368#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
369#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\
370 |RATR_36M|RATR_48M|RATR_54M
371#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \
372 RATR_MCS4|RATR_MCS5|RATR_MCS6|RATR_MCS7
373#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \
374 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
375
376 MCS_TXAGC = 0x340,
377 CCK_TXAGC = 0x348,
378
379
380
381 MacBlkCtrl = 0x403,
382
383 EPROM_CMD = 0xfe58,
384#define Cmd9346CR_9356SEL BIT(4)
385#define EPROM_CMD_RESERVED_MASK BIT(5)
386#define EPROM_CMD_OPERATING_MODE_SHIFT 6
387#define EPROM_CMD_OPERATING_MODE_MASK (BIT(7) | BIT(6))
388#define EPROM_CMD_CONFIG 0x3
389#define EPROM_CMD_NORMAL 0
390#define EPROM_CMD_LOAD 1
391#define EPROM_CMD_PROGRAM 2
392#define EPROM_CS_BIT BIT(3)
393#define EPROM_CK_BIT BIT(2)
394#define EPROM_W_BIT BIT(1)
395#define EPROM_R_BIT BIT(0)
396
397 MAC0 = 0x000,
398 MAC1 = 0x001,
399 MAC2 = 0x002,
400 MAC3 = 0x003,
401 MAC4 = 0x004,
402 MAC5 = 0x005,
403
404};
405
406
407
408
409
410#define GPI 0x108
411#define GPO 0x109
412#define GPE 0x10a
413#endif
414