linux/drivers/staging/rtl8723au/include/rtl8723a_hal.h
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   1/******************************************************************************
   2 *
   3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12 * more details.
  13 *
  14 ******************************************************************************/
  15#ifndef __RTL8723A_HAL_H__
  16#define __RTL8723A_HAL_H__
  17
  18#include "rtl8723a_spec.h"
  19#include "rtl8723a_pg.h"
  20#include "Hal8723APhyReg.h"
  21#include "Hal8723APhyCfg.h"
  22#include "rtl8723a_rf.h"
  23#include "rtl8723a_bt_intf.h"
  24#ifdef CONFIG_8723AU_BT_COEXIST
  25#include "rtl8723a_bt-coexist.h"
  26#endif
  27#include "rtl8723a_dm.h"
  28#include "rtl8723a_recv.h"
  29#include "rtl8723a_xmit.h"
  30#include "rtl8723a_cmd.h"
  31#include "rtl8723a_sreset.h"
  32#include "rtw_efuse.h"
  33#include "rtw_eeprom.h"
  34
  35#include "odm_precomp.h"
  36#include "odm.h"
  37
  38
  39/* 2TODO: We should define 8192S firmware related macro settings here!! */
  40#define RTL819X_DEFAULT_RF_TYPE                 RF_1T2R
  41#define RTL819X_TOTAL_RF_PATH                           2
  42
  43/*  */
  44/*              RTL8723S From header */
  45/*  */
  46
  47/*  Fw Array */
  48#define Rtl8723_FwImageArray                            Rtl8723UFwImgArray
  49#define Rtl8723_FwUMCBCutImageArrayWithBT               Rtl8723UFwUMCBCutImgArrayWithBT
  50#define Rtl8723_FwUMCBCutImageArrayWithoutBT    Rtl8723UFwUMCBCutImgArrayWithoutBT
  51
  52#define Rtl8723_ImgArrayLength                          Rtl8723UImgArrayLength
  53#define Rtl8723_UMCBCutImgArrayWithBTLength             Rtl8723UUMCBCutImgArrayWithBTLength
  54#define Rtl8723_UMCBCutImgArrayWithoutBTLength  Rtl8723UUMCBCutImgArrayWithoutBTLength
  55
  56#define Rtl8723_PHY_REG_Array_PG                        Rtl8723UPHY_REG_Array_PG
  57#define Rtl8723_PHY_REG_Array_PGLength          Rtl8723UPHY_REG_Array_PGLength
  58
  59#define Rtl8723_FwUMCBCutMPImageArray           Rtl8723SFwUMCBCutMPImgAr
  60#define Rtl8723_UMCBCutMPImgArrayLength         Rtl8723SUMCBCutMPImgArrayLength
  61
  62#define DRVINFO_SZ                              4 /*  unit is 8bytes */
  63#define PageNum_128(_Len)               (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
  64
  65#define FW_8723A_SIZE                   0x8000
  66#define FW_8723A_START_ADDRESS  0x1000
  67#define FW_8723A_END_ADDRESS            0x1FFF /* 0x5FFF */
  68
  69#define MAX_PAGE_SIZE                   4096    /*  @ page : 4k bytes */
  70
  71#define IS_FW_HEADER_EXIST(_pFwHdr)     ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
  72                                                                        (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
  73                                                                        (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
  74
  75/*  */
  76/*  This structure must be cared byte-ordering */
  77/*  */
  78/*  Added by tynli. 2009.12.04. */
  79struct rt_8723a_firmware_hdr {
  80        /*  8-byte alinment required */
  81
  82        /*  LONG WORD 0 ---- */
  83        __le16          Signature;  /*
  84                                     * 92C0: test chip; 92C, 88C0: test chip;
  85                                     * 88C1: MP A-cut; 92C1: MP A-cut
  86                                     */
  87        u8              Category;       /*  AP/NIC and USB/PCI */
  88        u8              Function;       /*  Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
  89        __le16          Version;                /*  FW Version */
  90        u8              Subversion;     /*  FW Subversion, default 0x00 */
  91        u8              Rsvd1;
  92
  93
  94        /*  LONG WORD 1 ---- */
  95        u8              Month;  /*  Release time Month field */
  96        u8              Date;   /*  Release time Date field */
  97        u8              Hour;   /*  Release time Hour field */
  98        u8              Minute; /*  Release time Minute field */
  99        __le16          RamCodeSize;    /*  The size of RAM code */
 100        __le16          Rsvd2;
 101
 102        /*  LONG WORD 2 ---- */
 103        __le32          SvnIdx; /*  The SVN entry index */
 104        __le32          Rsvd3;
 105
 106        /*  LONG WORD 3 ---- */
 107        __le32          Rsvd4;
 108        __le32          Rsvd5;
 109};
 110
 111#define DRIVER_EARLY_INT_TIME           0x05
 112#define BCN_DMA_ATIME_INT_TIME          0x02
 113
 114
 115/*  BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
 116#define MAX_TX_QUEUE            9
 117
 118#define TX_SELE_HQ                      BIT(0)          /*  High Queue */
 119#define TX_SELE_LQ                      BIT(1)          /*  Low Queue */
 120#define TX_SELE_NQ                      BIT(2)          /*  Normal Queue */
 121
 122/*  Note: We will divide number of page equally for each queue other than public queue! */
 123#define TX_TOTAL_PAGE_NUMBER    0xF8
 124#define TX_PAGE_BOUNDARY                (TX_TOTAL_PAGE_NUMBER + 1)
 125
 126/*  For Normal Chip Setting */
 127/*  (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
 128#define NORMAL_PAGE_NUM_PUBQ    0xE7
 129#define NORMAL_PAGE_NUM_HPQ             0x0C
 130#define NORMAL_PAGE_NUM_LPQ             0x02
 131#define NORMAL_PAGE_NUM_NPQ             0x02
 132
 133/*  For Test Chip Setting */
 134/*  (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
 135#define TEST_PAGE_NUM_PUBQ              0x7E
 136
 137/*  For Test Chip Setting */
 138#define WMM_TEST_TX_TOTAL_PAGE_NUMBER   0xF5
 139#define WMM_TEST_TX_PAGE_BOUNDARY               (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */
 140
 141#define WMM_TEST_PAGE_NUM_PUBQ          0xA3
 142#define WMM_TEST_PAGE_NUM_HPQ           0x29
 143#define WMM_TEST_PAGE_NUM_LPQ           0x29
 144
 145/*  Note: For Normal Chip Setting, modify later */
 146#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
 147#define WMM_NORMAL_TX_PAGE_BOUNDARY             (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */
 148
 149#define WMM_NORMAL_PAGE_NUM_PUBQ        0xB0
 150#define WMM_NORMAL_PAGE_NUM_HPQ         0x29
 151#define WMM_NORMAL_PAGE_NUM_LPQ         0x1C
 152#define WMM_NORMAL_PAGE_NUM_NPQ         0x1C
 153
 154
 155/*  */
 156/*      Chip specific */
 157/*  */
 158#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 159#define CHIP_BONDING_92C_1T2R                   0x1
 160#define CHIP_BONDING_88C_USB_MCARD              0x2
 161#define CHIP_BONDING_88C_USB_HP                 0x1
 162
 163#include "HalVerDef.h"
 164#include "hal_com.h"
 165
 166/*  */
 167/*      Channel Plan */
 168/*  */
 169enum ChannelPlan
 170{
 171        CHPL_FCC        = 0,
 172        CHPL_IC         = 1,
 173        CHPL_ETSI       = 2,
 174        CHPL_SPAIN      = 3,
 175        CHPL_FRANCE     = 4,
 176        CHPL_MKK        = 5,
 177        CHPL_MKK1       = 6,
 178        CHPL_ISRAEL     = 7,
 179        CHPL_TELEC      = 8,
 180        CHPL_GLOBAL     = 9,
 181        CHPL_WORLD      = 10,
 182};
 183
 184#define EFUSE_REAL_CONTENT_LEN          512
 185#define EFUSE_MAP_LEN                           128
 186#define EFUSE_MAX_SECTION                       16
 187#define EFUSE_IC_ID_OFFSET                      506     /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
 188#define AVAILABLE_EFUSE_ADDR(addr)      (addr < EFUSE_REAL_CONTENT_LEN)
 189/*  */
 190/*  <Roger_Notes> */
 191/*  To prevent out of boundary programming case, */
 192/*  leave 1byte and program full section */
 193/*  9bytes + 1byt + 5bytes and pre 1byte. */
 194/*  For worst case: */
 195/*  | 1byte|----8bytes----|1byte|--5bytes--| */
 196/*  |         |            Reserved(14bytes)          | */
 197/*  */
 198
 199/*  PG data exclude header, dummy 6 bytes from CP test and reserved 1byte. */
 200#define EFUSE_OOB_PROTECT_BYTES                 15
 201
 202#define EFUSE_REAL_CONTENT_LEN_8723A    512
 203#define EFUSE_MAP_LEN_8723A                             256
 204#define EFUSE_MAX_SECTION_8723A                 32
 205
 206/*  */
 207/*                      EFUSE for BT definition */
 208/*  */
 209#define EFUSE_BT_REAL_BANK_CONTENT_LEN  512
 210#define EFUSE_BT_REAL_CONTENT_LEN               1536    /*  512*3 */
 211#define EFUSE_BT_MAP_LEN                                1024    /*  1k bytes */
 212#define EFUSE_BT_MAX_SECTION                    128             /*  1024/8 */
 213
 214#define EFUSE_PROTECT_BYTES_BANK                16
 215
 216/*  */
 217/*  <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. */
 218/*  */
 219enum RT_MULTI_FUNC {
 220        RT_MULTI_FUNC_NONE = 0x00,
 221        RT_MULTI_FUNC_WIFI = 0x01,
 222        RT_MULTI_FUNC_BT = 0x02,
 223        RT_MULTI_FUNC_GPS = 0x04,
 224};
 225
 226/*  */
 227/*  <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. */
 228/*  */
 229enum RT_POLARITY_CTL {
 230        RT_POLARITY_LOW_ACT = 0,
 231        RT_POLARITY_HIGH_ACT = 1,
 232};
 233
 234/*  For RTL8723 regulator mode. by tynli. 2011.01.14. */
 235enum RT_REGULATOR_MODE {
 236        RT_SWITCHING_REGULATOR = 0,
 237        RT_LDO_REGULATOR = 1,
 238};
 239
 240/*  Description: Determine the types of C2H events that are the same in driver and Fw. */
 241/*  Fisrt constructed by tynli. 2009.10.09. */
 242enum {
 243        C2H_DBG = 0,
 244        C2H_TSF = 1,
 245        C2H_AP_RPT_RSP = 2,
 246        C2H_CCX_TX_RPT = 3,     /*  The FW notify the report of the specific tx packet. */
 247        C2H_BT_RSSI = 4,
 248        C2H_BT_OP_MODE = 5,
 249        C2H_EXT_RA_RPT = 6,
 250        C2H_HW_INFO_EXCH = 10,
 251        C2H_C2H_H2C_TEST = 11,
 252        C2H_BT_INFO = 12,
 253        C2H_BT_MP_INFO = 15,
 254        MAX_C2HEVENT
 255};
 256
 257struct hal_data_8723a {
 258        struct hal_version              VersionID;
 259        enum rt_customer_id CustomerID;
 260
 261        u16     FirmwareVersion;
 262        u16     FirmwareVersionRev;
 263        u16     FirmwareSubVersion;
 264        u16     FirmwareSignature;
 265
 266        /* current WIFI_PHY values */
 267        u32     ReceiveConfig;
 268        enum WIRELESS_MODE              CurrentWirelessMode;
 269        enum ht_channel_width   CurrentChannelBW;
 270        u8      CurrentChannel;
 271        u8      nCur40MhzPrimeSC;/*  Control channel sub-carrier */
 272
 273        u16     BasicRateSet;
 274
 275        /* rf_ctrl */
 276        u8      rf_type;
 277        u8      NumTotalRFPath;
 278
 279        u8      BoardType;
 280        u8      CrystalCap;
 281        /*  */
 282        /*  EEPROM setting. */
 283        /*  */
 284        u8      EEPROMVersion;
 285        u8      EEPROMCustomerID;
 286        u8      EEPROMSubCustomerID;
 287        u8      EEPROMRegulatory;
 288        u8      EEPROMThermalMeter;
 289        u8      EEPROMBluetoothCoexist;
 290        u8      EEPROMBluetoothType;
 291        u8      EEPROMBluetoothAntNum;
 292        u8      EEPROMBluetoothAntIsolation;
 293        u8      EEPROMBluetoothRadioShared;
 294
 295        u8      bTXPowerDataReadFromEEPORM;
 296        u8      bAPKThermalMeterIgnore;
 297
 298        u8      bIQKInitialized;
 299        u8      bAntennaDetected;
 300
 301        u8      TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 302        u8      TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];     /*  For HT 40MHZ pwr */
 303        u8      TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];     /*  For HT 40MHZ pwr */
 304        u8      TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/*  HT 20<->40 Pwr diff */
 305        u8      TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/*  For HT<->legacy pwr diff */
 306        /*  For power group */
 307        u8      PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 308        u8      PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 309
 310        u8      LegacyHTTxPowerDiff;/*  Legacy to HT rate power diff */
 311
 312        /*  Read/write are allow for following hardware information variables */
 313        u8      framesync;
 314        u32     framesyncC34;
 315        u8      framesyncMonitor;
 316        u8      pwrGroupCnt;
 317        u32     MCSTxPowerLevelOriginalOffset[7][16];
 318        u32     CCKTxPowerLevelOriginalOffset;
 319
 320        u32     AntennaTxPath;                                  /*  Antenna path Tx */
 321        u32     AntennaRxPath;                                  /*  Antenna path Rx */
 322        u8      ExternalPA;
 323
 324        u8      bLedOpenDrain; /*  Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
 325
 326        u8      b1x1RecvCombine;        /*  for 1T1R receive combining */
 327
 328        /*  For EDCA Turbo mode */
 329
 330        u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
 331
 332        /* vivi, for tx power tracking, 20080407 */
 333        /* u16  TSSI_13dBm; */
 334        /* u32  Pwr_Track; */
 335        /*  The current Tx Power Level */
 336        u8      CurrentCckTxPwrIdx;
 337        u8      CurrentOfdm24GTxPwrIdx;
 338
 339        struct bb_reg_define    PHYRegDef[4];   /* Radio A/B/C/D */
 340
 341        bool            bRFPathRxEnable[4];     /*  We support 4 RF path now. */
 342
 343        u32     RfRegChnlVal[2];
 344
 345        u8      bCckHighPower;
 346
 347        /* RDG enable */
 348        bool     bRDGEnable;
 349
 350        /* for host message to fw */
 351        u8      LastHMEBoxNum;
 352
 353        u8      RegTxPause;
 354        /*  Beacon function related global variable. */
 355        u8      RegFwHwTxQCtrl;
 356        u8      RegReg542;
 357
 358        struct dm_priv  dmpriv;
 359        struct dm_odm_t         odmpriv;
 360        struct sreset_priv srestpriv;
 361
 362#ifdef CONFIG_8723AU_BT_COEXIST
 363        u8                              bBTMode;
 364        /*  BT only. */
 365        struct bt_30info                BtInfo;
 366        /*  For bluetooth co-existance */
 367        struct bt_coexist_str   bt_coexist;
 368#endif
 369
 370        u8      bDumpRxPkt;/* for debug */
 371        u8      FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. */
 372
 373        /*  2010/08/09 MH Add CU power down mode. */
 374        u8      pwrdown;
 375
 376        u8      OutEpQueueSel;
 377        u8      OutEpNumber;
 378
 379        /*  */
 380        /*  Add For EEPROM Efuse switch and  Efuse Shadow map Setting */
 381        /*  */
 382        u8                      EepromOrEfuse;
 383        u16                     EfuseUsedBytes;
 384        u16                     BTEfuseUsedBytes;
 385
 386        /*  Interrupt relatd register information. */
 387        u32                     SysIntrStatus;
 388        u32                     SysIntrMask;
 389
 390        /*  */
 391        /*  2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an */
 392        /*  independent file in the future. */
 393        /*  */
 394        /* 8723-----------------------------------------*/
 395        enum RT_MULTI_FUNC      MultiFunc; /*  For multi-function consideration. */
 396        enum RT_POLARITY_CTL    PolarityCtl; /*  For Wifi PDn Polarity control. */
 397        enum RT_REGULATOR_MODE  RegulatorMode; /*  switching regulator or LDO */
 398        /* 8723-----------------------------------------
 399         *  2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an */
 400        /*  independent file in the future. */
 401
 402        /*  Interrupt related register information. */
 403        u32     IntArray[2];
 404        u32     IntrMask[2];
 405};
 406
 407#define GET_HAL_DATA(__pAdapter)        ((struct hal_data_8723a *)((__pAdapter)->HalData))
 408#define GET_RF_TYPE(priv)                       (GET_HAL_DATA(priv)->rf_type)
 409
 410#define INCLUDE_MULTI_FUNC_BT(_Adapter)         (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
 411#define INCLUDE_MULTI_FUNC_GPS(_Adapter)        (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
 412
 413struct rxreport_8723a {
 414        u32 pktlen:14;
 415        u32 crc32:1;
 416        u32 icverr:1;
 417        u32 drvinfosize:4;
 418        u32 security:3;
 419        u32 qos:1;
 420        u32 shift:2;
 421        u32 physt:1;
 422        u32 swdec:1;
 423        u32 ls:1;
 424        u32 fs:1;
 425        u32 eor:1;
 426        u32 own:1;
 427
 428        u32 macid:5;
 429        u32 tid:4;
 430        u32 hwrsvd:4;
 431        u32 amsdu:1;
 432        u32 paggr:1;
 433        u32 faggr:1;
 434        u32 a1fit:4;
 435        u32 a2fit:4;
 436        u32 pam:1;
 437        u32 pwr:1;
 438        u32 md:1;
 439        u32 mf:1;
 440        u32 type:2;
 441        u32 mc:1;
 442        u32 bc:1;
 443
 444        u32 seq:12;
 445        u32 frag:4;
 446        u32 nextpktlen:14;
 447        u32 nextind:1;
 448        u32 rsvd0831:1;
 449
 450        u32 rxmcs:6;
 451        u32 rxht:1;
 452        u32 gf:1;
 453        u32 splcp:1;
 454        u32 bw:1;
 455        u32 htc:1;
 456        u32 eosp:1;
 457        u32 bssidfit:2;
 458        u32 rsvd1214:16;
 459        u32 unicastwake:1;
 460        u32 magicwake:1;
 461
 462        u32 pattern0match:1;
 463        u32 pattern1match:1;
 464        u32 pattern2match:1;
 465        u32 pattern3match:1;
 466        u32 pattern4match:1;
 467        u32 pattern5match:1;
 468        u32 pattern6match:1;
 469        u32 pattern7match:1;
 470        u32 pattern8match:1;
 471        u32 pattern9match:1;
 472        u32 patternamatch:1;
 473        u32 patternbmatch:1;
 474        u32 patterncmatch:1;
 475        u32 rsvd1613:19;
 476
 477        u32 tsfl;
 478
 479        u32 bassn:12;
 480        u32 bavld:1;
 481        u32 rsvd2413:19;
 482};
 483
 484/*  rtl8723a_hal_init.c */
 485s32 rtl8723a_FirmwareDownload(struct rtw_adapter *padapter);
 486void rtl8723a_FirmwareSelfReset(struct rtw_adapter *padapter);
 487void rtl8723a_InitializeFirmwareVars(struct rtw_adapter *padapter);
 488
 489void rtl8723a_InitAntenna_Selection(struct rtw_adapter *padapter);
 490void rtl8723a_DeinitAntenna_Selection(struct rtw_adapter *padapter);
 491void rtl8723a_CheckAntenna_Selection(struct rtw_adapter *padapter);
 492void rtl8723a_init_default_value(struct rtw_adapter *padapter);
 493
 494s32 InitLLTTable23a(struct rtw_adapter *padapter, u32 boundary);
 495
 496s32 CardDisableHWSM(struct rtw_adapter *padapter, u8 resetMCU);
 497s32 CardDisableWithoutHWSM(struct rtw_adapter *padapter);
 498
 499/*  EFuse */
 500u8 GetEEPROMSize8723A(struct rtw_adapter *padapter);
 501void Hal_InitPGData(struct rtw_adapter *padapter, u8 *PROMContent);
 502void Hal_EfuseParseIDCode(struct rtw_adapter *padapter, u8 *hwinfo);
 503void Hal_EfuseParsetxpowerinfo_8723A(struct rtw_adapter *padapter, u8 *PROMContent, bool AutoLoadFail);
 504void Hal_EfuseParseBTCoexistInfo_8723A(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 505void Hal_EfuseParseEEPROMVer(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 506void rtl8723a_EfuseParseChnlPlan(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 507void Hal_EfuseParseCustomerID(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 508void Hal_EfuseParseAntennaDiversity(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 509void Hal_EfuseParseRateIndicationOption(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 510void Hal_EfuseParseXtal_8723A(struct rtw_adapter *pAdapter, u8 *hwinfo, u8 AutoLoadFail);
 511void Hal_EfuseParseThermalMeter_8723A(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 512
 513/*  register */
 514void SetBcnCtrlReg23a(struct rtw_adapter *padapter, u8 SetBits, u8 ClearBits);
 515void rtl8723a_InitBeaconParameters(struct rtw_adapter *padapter);
 516
 517void rtl8723a_start_thread(struct rtw_adapter *padapter);
 518void rtl8723a_stop_thread(struct rtw_adapter *padapter);
 519
 520bool c2h_id_filter_ccx_8723a(u8 id);
 521int c2h_handler_8723a(struct rtw_adapter *padapter, struct c2h_evt_hdr *c2h_evt);
 522
 523void rtl8723a_read_adapter_info(struct rtw_adapter *Adapter);
 524void rtl8723a_read_chip_version(struct rtw_adapter *padapter);
 525void rtl8723a_notch_filter(struct rtw_adapter *adapter, bool enable);
 526void rtl8723a_SetBeaconRelatedRegisters(struct rtw_adapter *padapter);
 527void rtl8723a_SetHalODMVar(struct rtw_adapter *Adapter,
 528                           enum hal_odm_variable eVariable,
 529                           void *pValue1, bool bSet);
 530void
 531rtl8723a_readefuse(struct rtw_adapter *padapter,
 532                   u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf);
 533u16 rtl8723a_EfuseGetCurrentSize_WiFi(struct rtw_adapter *padapter);
 534u16 rtl8723a_EfuseGetCurrentSize_BT(struct rtw_adapter *padapter);
 535void rtl8723a_update_ramask(struct rtw_adapter *padapter,
 536                            u32 mac_id, u8 rssi_level);
 537
 538#endif
 539
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