1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 7 */ 8#ifndef __LINUX_IRQCHIP_MIPS_GIC_H 9#define __LINUX_IRQCHIP_MIPS_GIC_H 10 11#include <linux/clocksource.h> 12#include <linux/ioport.h> 13 14#define GIC_MAX_INTRS 256 15 16/* Constants */ 17#define GIC_POL_POS 1 18#define GIC_POL_NEG 0 19#define GIC_TRIG_EDGE 1 20#define GIC_TRIG_LEVEL 0 21#define GIC_TRIG_DUAL_ENABLE 1 22#define GIC_TRIG_DUAL_DISABLE 0 23 24#define MSK(n) ((1 << (n)) - 1) 25 26/* Accessors */ 27#define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS) 28 29/* GIC Address Space */ 30#define SHARED_SECTION_OFS 0x0000 31#define SHARED_SECTION_SIZE 0x8000 32#define VPE_LOCAL_SECTION_OFS 0x8000 33#define VPE_LOCAL_SECTION_SIZE 0x4000 34#define VPE_OTHER_SECTION_OFS 0xc000 35#define VPE_OTHER_SECTION_SIZE 0x4000 36#define USM_VISIBLE_SECTION_OFS 0x10000 37#define USM_VISIBLE_SECTION_SIZE 0x10000 38 39/* Register Map for Shared Section */ 40 41#define GIC_SH_CONFIG_OFS 0x0000 42 43/* Shared Global Counter */ 44#define GIC_SH_COUNTER_31_00_OFS 0x0010 45/* 64-bit counter register for CM3 */ 46#define GIC_SH_COUNTER_OFS GIC_SH_COUNTER_31_00_OFS 47#define GIC_SH_COUNTER_63_32_OFS 0x0014 48#define GIC_SH_REVISIONID_OFS 0x0020 49 50/* Convert an interrupt number to a byte offset/bit for multi-word registers */ 51#define GIC_INTR_OFS(intr) ({ \ 52 unsigned bits = mips_cm_is64 ? 64 : 32; \ 53 unsigned reg_idx = (intr) / bits; \ 54 unsigned reg_width = bits / 8; \ 55 \ 56 reg_idx * reg_width; \ 57}) 58#define GIC_INTR_BIT(intr) ((intr) % (mips_cm_is64 ? 64 : 32)) 59 60/* Polarity : Reset Value is always 0 */ 61#define GIC_SH_SET_POLARITY_OFS 0x0100 62 63/* Triggering : Reset Value is always 0 */ 64#define GIC_SH_SET_TRIGGER_OFS 0x0180 65 66/* Dual edge triggering : Reset Value is always 0 */ 67#define GIC_SH_SET_DUAL_OFS 0x0200 68 69/* Set/Clear corresponding bit in Edge Detect Register */ 70#define GIC_SH_WEDGE_OFS 0x0280 71 72/* Mask manipulation */ 73#define GIC_SH_RMASK_OFS 0x0300 74#define GIC_SH_SMASK_OFS 0x0380 75 76/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ 77#define GIC_SH_MASK_OFS 0x0400 78 79/* Pending Global Interrupts (RO) */ 80#define GIC_SH_PEND_OFS 0x0480 81 82/* Maps Interrupt X to a Pin */ 83#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 84#define GIC_SH_MAP_TO_PIN(intr) (4 * (intr)) 85 86/* Maps Interrupt X to a VPE */ 87#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000 88#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ 89 ((32 * (intr)) + (((vpe) / 32) * 4)) 90#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) 91 92/* Register Map for Local Section */ 93#define GIC_VPE_CTL_OFS 0x0000 94#define GIC_VPE_PEND_OFS 0x0004 95#define GIC_VPE_MASK_OFS 0x0008 96#define GIC_VPE_RMASK_OFS 0x000c 97#define GIC_VPE_SMASK_OFS 0x0010 98#define GIC_VPE_WD_MAP_OFS 0x0040 99#define GIC_VPE_COMPARE_MAP_OFS 0x0044 100#define GIC_VPE_TIMER_MAP_OFS 0x0048 101#define GIC_VPE_FDC_MAP_OFS 0x004c 102#define GIC_VPE_PERFCTR_MAP_OFS 0x0050 103#define GIC_VPE_SWINT0_MAP_OFS 0x0054 104#define GIC_VPE_SWINT1_MAP_OFS 0x0058 105#define GIC_VPE_OTHER_ADDR_OFS 0x0080 106#define GIC_VP_IDENT_OFS 0x0088 107#define GIC_VPE_WD_CONFIG0_OFS 0x0090 108#define GIC_VPE_WD_COUNT0_OFS 0x0094 109#define GIC_VPE_WD_INITIAL0_OFS 0x0098 110#define GIC_VPE_COMPARE_LO_OFS 0x00a0 111/* 64-bit Compare register on CM3 */ 112#define GIC_VPE_COMPARE_OFS GIC_VPE_COMPARE_LO_OFS 113#define GIC_VPE_COMPARE_HI_OFS 0x00a4 114 115#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS 0x0100 116#define GIC_VPE_EIC_SS(intr) (4 * (intr)) 117 118#define GIC_VPE_EIC_VEC_BASE_OFS 0x0800 119#define GIC_VPE_EIC_VEC(intr) (4 * (intr)) 120 121#define GIC_VPE_TENABLE_NMI_OFS 0x1000 122#define GIC_VPE_TENABLE_YQ_OFS 0x1004 123#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080 124#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084 125 126/* User Mode Visible Section Register Map */ 127#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 128#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 129 130/* Masks */ 131#define GIC_SH_CONFIG_COUNTSTOP_SHF 28 132#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) 133 134#define GIC_SH_CONFIG_COUNTBITS_SHF 24 135#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF) 136 137#define GIC_SH_CONFIG_NUMINTRS_SHF 16 138#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF) 139 140#define GIC_SH_CONFIG_NUMVPES_SHF 0 141#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF) 142 143#define GIC_SH_WEDGE_SET(intr) ((intr) | (0x1 << 31)) 144#define GIC_SH_WEDGE_CLR(intr) ((intr) & ~(0x1 << 31)) 145 146#define GIC_MAP_TO_PIN_SHF 31 147#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF) 148#define GIC_MAP_TO_NMI_SHF 30 149#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF) 150#define GIC_MAP_TO_YQ_SHF 29 151#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF) 152#define GIC_MAP_SHF 0 153#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) 154 155/* GIC_VPE_CTL Masks */ 156#define GIC_VPE_CTL_FDC_RTBL_SHF 4 157#define GIC_VPE_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF) 158#define GIC_VPE_CTL_SWINT_RTBL_SHF 3 159#define GIC_VPE_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF) 160#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2 161#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF) 162#define GIC_VPE_CTL_TIMER_RTBL_SHF 1 163#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF) 164#define GIC_VPE_CTL_EIC_MODE_SHF 0 165#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF) 166 167/* GIC_VPE_PEND Masks */ 168#define GIC_VPE_PEND_WD_SHF 0 169#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF) 170#define GIC_VPE_PEND_CMP_SHF 1 171#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF) 172#define GIC_VPE_PEND_TIMER_SHF 2 173#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF) 174#define GIC_VPE_PEND_PERFCOUNT_SHF 3 175#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF) 176#define GIC_VPE_PEND_SWINT0_SHF 4 177#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF) 178#define GIC_VPE_PEND_SWINT1_SHF 5 179#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF) 180#define GIC_VPE_PEND_FDC_SHF 6 181#define GIC_VPE_PEND_FDC_MSK (MSK(1) << GIC_VPE_PEND_FDC_SHF) 182 183/* GIC_VPE_RMASK Masks */ 184#define GIC_VPE_RMASK_WD_SHF 0 185#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF) 186#define GIC_VPE_RMASK_CMP_SHF 1 187#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF) 188#define GIC_VPE_RMASK_TIMER_SHF 2 189#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF) 190#define GIC_VPE_RMASK_PERFCNT_SHF 3 191#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF) 192#define GIC_VPE_RMASK_SWINT0_SHF 4 193#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF) 194#define GIC_VPE_RMASK_SWINT1_SHF 5 195#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF) 196#define GIC_VPE_RMASK_FDC_SHF 6 197#define GIC_VPE_RMASK_FDC_MSK (MSK(1) << GIC_VPE_RMASK_FDC_SHF) 198 199/* GIC_VPE_SMASK Masks */ 200#define GIC_VPE_SMASK_WD_SHF 0 201#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF) 202#define GIC_VPE_SMASK_CMP_SHF 1 203#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF) 204#define GIC_VPE_SMASK_TIMER_SHF 2 205#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF) 206#define GIC_VPE_SMASK_PERFCNT_SHF 3 207#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF) 208#define GIC_VPE_SMASK_SWINT0_SHF 4 209#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF) 210#define GIC_VPE_SMASK_SWINT1_SHF 5 211#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF) 212#define GIC_VPE_SMASK_FDC_SHF 6 213#define GIC_VPE_SMASK_FDC_MSK (MSK(1) << GIC_VPE_SMASK_FDC_SHF) 214 215/* GIC_VP_IDENT fields */ 216#define GIC_VP_IDENT_VCNUM_SHF 0 217#define GIC_VP_IDENT_VCNUM_MSK (MSK(6) << GIC_VP_IDENT_VCNUM_SHF) 218 219/* GIC nomenclature for Core Interrupt Pins. */ 220#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ 221#define GIC_CPU_INT1 1 /* . */ 222#define GIC_CPU_INT2 2 /* . */ 223#define GIC_CPU_INT3 3 /* . */ 224#define GIC_CPU_INT4 4 /* . */ 225#define GIC_CPU_INT5 5 /* Core Interrupt 7 */ 226 227/* Add 2 to convert GIC CPU pin to core interrupt */ 228#define GIC_CPU_PIN_OFFSET 2 229 230/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */ 231#define GIC_CPU_TO_VEC_OFFSET 2 232 233/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ 234#define GIC_PIN_TO_VEC_OFFSET 1 235 236/* Local GIC interrupts. */ 237#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */ 238#define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */ 239#define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */ 240#define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */ 241#define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */ 242#define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */ 243#define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */ 244#define GIC_NUM_LOCAL_INTRS 7 245 246/* Convert between local/shared IRQ number and GIC HW IRQ number. */ 247#define GIC_LOCAL_HWIRQ_BASE 0 248#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x)) 249#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE) 250#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS 251#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x)) 252#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE) 253 254#ifdef CONFIG_MIPS_GIC 255 256extern unsigned int gic_present; 257 258extern void gic_init(unsigned long gic_base_addr, 259 unsigned long gic_addrspace_size, unsigned int cpu_vec, 260 unsigned int irqbase); 261extern void gic_clocksource_init(unsigned int); 262extern cycle_t gic_read_count(void); 263extern unsigned int gic_get_count_width(void); 264extern cycle_t gic_read_compare(void); 265extern void gic_write_compare(cycle_t cnt); 266extern void gic_write_cpu_compare(cycle_t cnt, int cpu); 267extern void gic_start_count(void); 268extern void gic_stop_count(void); 269extern int gic_get_c0_compare_int(void); 270extern int gic_get_c0_perfcount_int(void); 271extern int gic_get_c0_fdc_int(void); 272extern int gic_get_usm_range(struct resource *gic_usm_res); 273 274#else /* CONFIG_MIPS_GIC */ 275 276#define gic_present 0 277 278static inline int gic_get_usm_range(struct resource *gic_usm_res) 279{ 280 /* Shouldn't be called. */ 281 return -1; 282} 283 284#endif /* CONFIG_MIPS_GIC */ 285 286/** 287 * gic_read_local_vp_id() - read the local VPs VCNUM 288 * 289 * Read the VCNUM of the local VP from the GIC_VP_IDENT register and 290 * return it to the caller. This ID should be used to refer to the VP 291 * via the GICs VP-other region, or when calculating an offset to a 292 * bit representing the VP in interrupt masks. 293 * 294 * Return: The VCNUM value for the local VP. 295 */ 296extern unsigned gic_read_local_vp_id(void); 297 298#endif /* __LINUX_IRQCHIP_MIPS_GIC_H */ 299