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16#ifndef LINUX_PCI_H
17#define LINUX_PCI_H
18
19
20#include <linux/mod_devicetable.h>
21
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/ioport.h>
25#include <linux/list.h>
26#include <linux/compiler.h>
27#include <linux/errno.h>
28#include <linux/kobject.h>
29#include <linux/atomic.h>
30#include <linux/device.h>
31#include <linux/io.h>
32#include <linux/resource_ext.h>
33#include <uapi/linux/pci.h>
34
35#include <linux/pci_ids.h>
36
37
38
39
40
41
42
43
44
45
46
47
48
49#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50
51#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
52
53
54struct pci_slot {
55 struct pci_bus *bus;
56 struct list_head list;
57 struct hotplug_slot *hotplug;
58 unsigned char number;
59 struct kobject kobj;
60};
61
62static inline const char *pci_slot_name(const struct pci_slot *slot)
63{
64 return kobject_name(&slot->kobj);
65}
66
67
68enum pci_mmap_state {
69 pci_mmap_io,
70 pci_mmap_mem
71};
72
73
74
75
76enum {
77
78 PCI_STD_RESOURCES,
79 PCI_STD_RESOURCE_END = 5,
80
81
82 PCI_ROM_RESOURCE,
83
84
85#ifdef CONFIG_PCI_IOV
86 PCI_IOV_RESOURCES,
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
88#endif
89
90
91#define PCI_BRIDGE_RESOURCE_NUM 4
92
93 PCI_BRIDGE_RESOURCES,
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
96
97
98 PCI_NUM_RESOURCES,
99
100
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
102};
103
104typedef int __bitwise pci_power_t;
105
106#define PCI_D0 ((pci_power_t __force) 0)
107#define PCI_D1 ((pci_power_t __force) 1)
108#define PCI_D2 ((pci_power_t __force) 2)
109#define PCI_D3hot ((pci_power_t __force) 3)
110#define PCI_D3cold ((pci_power_t __force) 4)
111#define PCI_UNKNOWN ((pci_power_t __force) 5)
112#define PCI_POWER_ERROR ((pci_power_t __force) -1)
113
114
115extern const char *pci_power_names[];
116
117static inline const char *pci_power_name(pci_power_t state)
118{
119 return pci_power_names[1 + (int) state];
120}
121
122#define PCI_PM_D2_DELAY 200
123#define PCI_PM_D3_WAIT 10
124#define PCI_PM_D3COLD_WAIT 100
125#define PCI_PM_BUS_WAIT 50
126
127
128
129
130
131typedef unsigned int __bitwise pci_channel_state_t;
132
133enum pci_channel_state {
134
135 pci_channel_io_normal = (__force pci_channel_state_t) 1,
136
137
138 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
139
140
141 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
142};
143
144typedef unsigned int __bitwise pcie_reset_state_t;
145
146enum pcie_reset_state {
147
148 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
149
150
151 pcie_warm_reset = (__force pcie_reset_state_t) 2,
152
153
154 pcie_hot_reset = (__force pcie_reset_state_t) 3
155};
156
157typedef unsigned short __bitwise pci_dev_flags_t;
158enum pci_dev_flags {
159
160
161
162 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
163
164 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
165
166 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
167
168 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
169
170 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
171
172 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
173
174 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
175
176 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
177};
178
179enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182};
183
184typedef unsigned short __bitwise pci_bus_flags_t;
185enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188};
189
190
191enum pcie_link_width {
192 PCIE_LNK_WIDTH_RESRV = 0x00,
193 PCIE_LNK_X1 = 0x01,
194 PCIE_LNK_X2 = 0x02,
195 PCIE_LNK_X4 = 0x04,
196 PCIE_LNK_X8 = 0x08,
197 PCIE_LNK_X12 = 0x0C,
198 PCIE_LNK_X16 = 0x10,
199 PCIE_LNK_X32 = 0x20,
200 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
201};
202
203
204enum pci_bus_speed {
205 PCI_SPEED_33MHz = 0x00,
206 PCI_SPEED_66MHz = 0x01,
207 PCI_SPEED_66MHz_PCIX = 0x02,
208 PCI_SPEED_100MHz_PCIX = 0x03,
209 PCI_SPEED_133MHz_PCIX = 0x04,
210 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
211 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
212 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
213 PCI_SPEED_66MHz_PCIX_266 = 0x09,
214 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
215 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
216 AGP_UNKNOWN = 0x0c,
217 AGP_1X = 0x0d,
218 AGP_2X = 0x0e,
219 AGP_4X = 0x0f,
220 AGP_8X = 0x10,
221 PCI_SPEED_66MHz_PCIX_533 = 0x11,
222 PCI_SPEED_100MHz_PCIX_533 = 0x12,
223 PCI_SPEED_133MHz_PCIX_533 = 0x13,
224 PCIE_SPEED_2_5GT = 0x14,
225 PCIE_SPEED_5_0GT = 0x15,
226 PCIE_SPEED_8_0GT = 0x16,
227 PCI_SPEED_UNKNOWN = 0xff,
228};
229
230struct pci_cap_saved_data {
231 u16 cap_nr;
232 bool cap_extended;
233 unsigned int size;
234 u32 data[0];
235};
236
237struct pci_cap_saved_state {
238 struct hlist_node next;
239 struct pci_cap_saved_data cap;
240};
241
242struct pcie_link_state;
243struct pci_vpd;
244struct pci_sriov;
245struct pci_ats;
246
247
248
249
250struct pci_dev {
251 struct list_head bus_list;
252 struct pci_bus *bus;
253 struct pci_bus *subordinate;
254
255 void *sysdata;
256 struct proc_dir_entry *procent;
257 struct pci_slot *slot;
258
259 unsigned int devfn;
260 unsigned short vendor;
261 unsigned short device;
262 unsigned short subsystem_vendor;
263 unsigned short subsystem_device;
264 unsigned int class;
265 u8 revision;
266 u8 hdr_type;
267 u8 pcie_cap;
268 u8 msi_cap;
269 u8 msix_cap;
270 u8 pcie_mpss:3;
271 u8 rom_base_reg;
272 u8 pin;
273 u16 pcie_flags_reg;
274 unsigned long *dma_alias_mask;
275
276 struct pci_driver *driver;
277 u64 dma_mask;
278
279
280
281
282
283 struct device_dma_parameters dma_parms;
284
285 pci_power_t current_state;
286
287
288 u8 pm_cap;
289 unsigned int pme_support:5;
290
291 unsigned int pme_interrupt:1;
292 unsigned int pme_poll:1;
293 unsigned int d1_support:1;
294 unsigned int d2_support:1;
295 unsigned int no_d1d2:1;
296 unsigned int no_d3cold:1;
297 unsigned int d3cold_allowed:1;
298 unsigned int mmio_always_on:1;
299
300 unsigned int wakeup_prepared:1;
301 unsigned int runtime_d3cold:1;
302
303
304
305 unsigned int ignore_hotplug:1;
306 unsigned int d3_delay;
307 unsigned int d3cold_delay;
308
309#ifdef CONFIG_PCIEASPM
310 struct pcie_link_state *link_state;
311#endif
312
313 pci_channel_state_t error_state;
314 struct device dev;
315
316 int cfg_size;
317
318
319
320
321
322 unsigned int irq;
323 struct resource resource[DEVICE_COUNT_RESOURCE];
324
325 bool match_driver;
326
327 unsigned int transparent:1;
328 unsigned int multifunction:1;
329
330 unsigned int is_added:1;
331 unsigned int is_busmaster:1;
332 unsigned int no_msi:1;
333 unsigned int no_64bit_msi:1;
334 unsigned int block_cfg_access:1;
335 unsigned int broken_parity_status:1;
336 unsigned int irq_reroute_variant:2;
337 unsigned int msi_enabled:1;
338 unsigned int msix_enabled:1;
339 unsigned int ari_enabled:1;
340 unsigned int ats_enabled:1;
341 unsigned int is_managed:1;
342 unsigned int needs_freset:1;
343 unsigned int state_saved:1;
344 unsigned int is_physfn:1;
345 unsigned int is_virtfn:1;
346 unsigned int reset_fn:1;
347 unsigned int is_hotplug_bridge:1;
348 unsigned int __aer_firmware_first_valid:1;
349 unsigned int __aer_firmware_first:1;
350 unsigned int broken_intx_masking:1;
351 unsigned int io_window_1k:1;
352 unsigned int irq_managed:1;
353 unsigned int has_secondary_link:1;
354 unsigned int non_compliant_bars:1;
355 pci_dev_flags_t dev_flags;
356 atomic_t enable_cnt;
357
358 u32 saved_config_space[16];
359 struct hlist_head saved_cap_space;
360 struct bin_attribute *rom_attr;
361 int rom_attr_enabled;
362 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
363 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
364#ifdef CONFIG_PCI_MSI
365 const struct attribute_group **msi_irq_groups;
366#endif
367 struct pci_vpd *vpd;
368#ifdef CONFIG_PCI_ATS
369 union {
370 struct pci_sriov *sriov;
371 struct pci_dev *physfn;
372 };
373 u16 ats_cap;
374 u8 ats_stu;
375 atomic_t ats_ref_cnt;
376#endif
377 phys_addr_t rom;
378 size_t romlen;
379 char *driver_override;
380};
381
382static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
383{
384#ifdef CONFIG_PCI_IOV
385 if (dev->is_virtfn)
386 dev = dev->physfn;
387#endif
388 return dev;
389}
390
391struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
392
393#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
394#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
395
396static inline int pci_channel_offline(struct pci_dev *pdev)
397{
398 return (pdev->error_state != pci_channel_io_normal);
399}
400
401struct pci_host_bridge {
402 struct device dev;
403 struct pci_bus *bus;
404 struct list_head windows;
405 void (*release_fn)(struct pci_host_bridge *);
406 void *release_data;
407 unsigned int ignore_reset_delay:1;
408
409 resource_size_t (*align_resource)(struct pci_dev *dev,
410 const struct resource *res,
411 resource_size_t start,
412 resource_size_t size,
413 resource_size_t align);
414};
415
416#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
417
418struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
419
420void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
421 void (*release_fn)(struct pci_host_bridge *),
422 void *release_data);
423
424int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
425
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436
437
438
439#define PCI_SUBTRACTIVE_DECODE 0x1
440
441struct pci_bus_resource {
442 struct list_head list;
443 struct resource *res;
444 unsigned int flags;
445};
446
447#define PCI_REGION_FLAG_MASK 0x0fU
448
449struct pci_bus {
450 struct list_head node;
451 struct pci_bus *parent;
452 struct list_head children;
453 struct list_head devices;
454 struct pci_dev *self;
455 struct list_head slots;
456
457 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
458 struct list_head resources;
459 struct resource busn_res;
460
461 struct pci_ops *ops;
462 struct msi_controller *msi;
463 void *sysdata;
464 struct proc_dir_entry *procdir;
465
466 unsigned char number;
467 unsigned char primary;
468 unsigned char max_bus_speed;
469 unsigned char cur_bus_speed;
470#ifdef CONFIG_PCI_DOMAINS_GENERIC
471 int domain_nr;
472#endif
473
474 char name[48];
475
476 unsigned short bridge_ctl;
477 pci_bus_flags_t bus_flags;
478 struct device *bridge;
479 struct device dev;
480 struct bin_attribute *legacy_io;
481 struct bin_attribute *legacy_mem;
482 unsigned int is_added:1;
483};
484
485#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
486
487
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493
494
495static inline bool pci_is_root_bus(struct pci_bus *pbus)
496{
497 return !(pbus->parent);
498}
499
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505
506
507static inline bool pci_is_bridge(struct pci_dev *dev)
508{
509 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
510 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
511}
512
513static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
514{
515 dev = pci_physfn(dev);
516 if (pci_is_root_bus(dev->bus))
517 return NULL;
518
519 return dev->bus->self;
520}
521
522struct device *pci_get_host_bridge_device(struct pci_dev *dev);
523void pci_put_host_bridge_device(struct device *dev);
524
525#ifdef CONFIG_PCI_MSI
526static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
527{
528 return pci_dev->msi_enabled || pci_dev->msix_enabled;
529}
530#else
531static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
532#endif
533
534
535
536
537#define PCIBIOS_SUCCESSFUL 0x00
538#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
539#define PCIBIOS_BAD_VENDOR_ID 0x83
540#define PCIBIOS_DEVICE_NOT_FOUND 0x86
541#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
542#define PCIBIOS_SET_FAILED 0x88
543#define PCIBIOS_BUFFER_TOO_SMALL 0x89
544
545
546
547
548static inline int pcibios_err_to_errno(int err)
549{
550 if (err <= PCIBIOS_SUCCESSFUL)
551 return err;
552
553 switch (err) {
554 case PCIBIOS_FUNC_NOT_SUPPORTED:
555 return -ENOENT;
556 case PCIBIOS_BAD_VENDOR_ID:
557 return -ENOTTY;
558 case PCIBIOS_DEVICE_NOT_FOUND:
559 return -ENODEV;
560 case PCIBIOS_BAD_REGISTER_NUMBER:
561 return -EFAULT;
562 case PCIBIOS_SET_FAILED:
563 return -EIO;
564 case PCIBIOS_BUFFER_TOO_SMALL:
565 return -ENOSPC;
566 }
567
568 return -ERANGE;
569}
570
571
572
573struct pci_ops {
574 int (*add_bus)(struct pci_bus *bus);
575 void (*remove_bus)(struct pci_bus *bus);
576 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
577 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
578 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
579};
580
581
582
583
584
585int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
586 int reg, int len, u32 *val);
587int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
588 int reg, int len, u32 val);
589
590#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
591typedef u64 pci_bus_addr_t;
592#else
593typedef u32 pci_bus_addr_t;
594#endif
595
596struct pci_bus_region {
597 pci_bus_addr_t start;
598 pci_bus_addr_t end;
599};
600
601struct pci_dynids {
602 spinlock_t lock;
603 struct list_head list;
604};
605
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611
612
613
614typedef unsigned int __bitwise pci_ers_result_t;
615
616enum pci_ers_result {
617
618 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
619
620
621 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
622
623
624 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
625
626
627 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
628
629
630 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
631
632
633 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
634};
635
636
637struct pci_error_handlers {
638
639 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
640 enum pci_channel_state error);
641
642
643 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
644
645
646 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
647
648
649 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
650
651
652 void (*reset_notify)(struct pci_dev *dev, bool prepare);
653
654
655 void (*resume)(struct pci_dev *dev);
656};
657
658
659struct module;
660struct pci_driver {
661 struct list_head node;
662 const char *name;
663 const struct pci_device_id *id_table;
664 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id);
665 void (*remove) (struct pci_dev *dev);
666 int (*suspend) (struct pci_dev *dev, pm_message_t state);
667 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
668 int (*resume_early) (struct pci_dev *dev);
669 int (*resume) (struct pci_dev *dev);
670 void (*shutdown) (struct pci_dev *dev);
671 int (*sriov_configure) (struct pci_dev *dev, int num_vfs);
672 const struct pci_error_handlers *err_handler;
673 struct device_driver driver;
674 struct pci_dynids dynids;
675};
676
677#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
678
679
680
681
682
683
684
685#define DEFINE_PCI_DEVICE_TABLE(_table) \
686 const struct pci_device_id _table[]
687
688
689
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693
694
695
696
697#define PCI_DEVICE(vend,dev) \
698 .vendor = (vend), .device = (dev), \
699 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
700
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710
711#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
712 .vendor = (vend), .device = (dev), \
713 .subvendor = (subvend), .subdevice = (subdev)
714
715
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717
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719
720
721
722
723
724#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
725 .class = (dev_class), .class_mask = (dev_class_mask), \
726 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
727 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
728
729
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738
739
740#define PCI_VDEVICE(vend, dev) \
741 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
742 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
743
744enum {
745 PCI_REASSIGN_ALL_RSRC = 0x00000001,
746 PCI_REASSIGN_ALL_BUS = 0x00000002,
747 PCI_PROBE_ONLY = 0x00000004,
748 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
749 PCI_ENABLE_PROC_DOMAINS = 0x00000010,
750 PCI_COMPAT_DOMAIN_0 = 0x00000020,
751 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
752};
753
754
755#ifdef CONFIG_PCI
756
757extern unsigned int pci_flags;
758
759static inline void pci_set_flags(int flags) { pci_flags = flags; }
760static inline void pci_add_flags(int flags) { pci_flags |= flags; }
761static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
762static inline int pci_has_flag(int flag) { return pci_flags & flag; }
763
764void pcie_bus_configure_settings(struct pci_bus *bus);
765
766enum pcie_bus_config_types {
767 PCIE_BUS_TUNE_OFF,
768 PCIE_BUS_DEFAULT,
769 PCIE_BUS_SAFE,
770 PCIE_BUS_PERFORMANCE,
771 PCIE_BUS_PEER2PEER,
772};
773
774extern enum pcie_bus_config_types pcie_bus_config;
775
776extern struct bus_type pci_bus_type;
777
778
779
780extern struct list_head pci_root_buses;
781
782int no_pci_devices(void);
783
784void pcibios_resource_survey_bus(struct pci_bus *bus);
785void pcibios_bus_add_device(struct pci_dev *pdev);
786void pcibios_add_bus(struct pci_bus *bus);
787void pcibios_remove_bus(struct pci_bus *bus);
788void pcibios_fixup_bus(struct pci_bus *);
789int __must_check pcibios_enable_device(struct pci_dev *, int mask);
790
791char *pcibios_setup(char *str);
792
793
794resource_size_t pcibios_align_resource(void *, const struct resource *,
795 resource_size_t,
796 resource_size_t);
797void pcibios_update_irq(struct pci_dev *, int irq);
798
799
800void pci_fixup_cardbus(struct pci_bus *);
801
802
803
804void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
805 struct resource *res);
806void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
807 struct pci_bus_region *region);
808void pcibios_scan_specific_bus(int busn);
809struct pci_bus *pci_find_bus(int domain, int busnr);
810void pci_bus_add_devices(const struct pci_bus *bus);
811struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
812struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
813 struct pci_ops *ops, void *sysdata,
814 struct list_head *resources);
815int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
816int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
817void pci_bus_release_busn_res(struct pci_bus *b);
818struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
819 struct pci_ops *ops, void *sysdata,
820 struct list_head *resources,
821 struct msi_controller *msi);
822struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
823 struct pci_ops *ops, void *sysdata,
824 struct list_head *resources);
825struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
826 int busnr);
827void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
828struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
829 const char *name,
830 struct hotplug_slot *hotplug);
831void pci_destroy_slot(struct pci_slot *slot);
832#ifdef CONFIG_SYSFS
833void pci_dev_assign_slot(struct pci_dev *dev);
834#else
835static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
836#endif
837int pci_scan_slot(struct pci_bus *bus, int devfn);
838struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
839void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
840unsigned int pci_scan_child_bus(struct pci_bus *bus);
841void pci_bus_add_device(struct pci_dev *dev);
842void pci_read_bridge_bases(struct pci_bus *child);
843struct resource *pci_find_parent_resource(const struct pci_dev *dev,
844 struct resource *res);
845struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
846u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
847int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
848u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
849struct pci_dev *pci_dev_get(struct pci_dev *dev);
850void pci_dev_put(struct pci_dev *dev);
851void pci_remove_bus(struct pci_bus *b);
852void pci_stop_and_remove_bus_device(struct pci_dev *dev);
853void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
854void pci_stop_root_bus(struct pci_bus *bus);
855void pci_remove_root_bus(struct pci_bus *bus);
856void pci_setup_cardbus(struct pci_bus *bus);
857void pci_sort_breadthfirst(void);
858#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
859#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
860#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
861
862
863
864enum pci_lost_interrupt_reason {
865 PCI_LOST_IRQ_NO_INFORMATION = 0,
866 PCI_LOST_IRQ_DISABLE_MSI,
867 PCI_LOST_IRQ_DISABLE_MSIX,
868 PCI_LOST_IRQ_DISABLE_ACPI,
869};
870enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
871int pci_find_capability(struct pci_dev *dev, int cap);
872int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
873int pci_find_ext_capability(struct pci_dev *dev, int cap);
874int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
875int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
876int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
877struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
878
879struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
880 struct pci_dev *from);
881struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
882 unsigned int ss_vendor, unsigned int ss_device,
883 struct pci_dev *from);
884struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
885struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
886 unsigned int devfn);
887static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
888 unsigned int devfn)
889{
890 return pci_get_domain_bus_and_slot(0, bus, devfn);
891}
892struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
893int pci_dev_present(const struct pci_device_id *ids);
894
895int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
896 int where, u8 *val);
897int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
898 int where, u16 *val);
899int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
900 int where, u32 *val);
901int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
902 int where, u8 val);
903int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
904 int where, u16 val);
905int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
906 int where, u32 val);
907
908int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
909 int where, int size, u32 *val);
910int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
911 int where, int size, u32 val);
912int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
913 int where, int size, u32 *val);
914int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
915 int where, int size, u32 val);
916
917struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
918
919static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
920{
921 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
922}
923static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
924{
925 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
926}
927static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
928 u32 *val)
929{
930 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
931}
932static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
933{
934 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
935}
936static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
937{
938 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
939}
940static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
941 u32 val)
942{
943 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
944}
945
946int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
947int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
948int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
949int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
950int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
951 u16 clear, u16 set);
952int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
953 u32 clear, u32 set);
954
955static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
956 u16 set)
957{
958 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
959}
960
961static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
962 u32 set)
963{
964 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
965}
966
967static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
968 u16 clear)
969{
970 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
971}
972
973static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
974 u32 clear)
975{
976 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
977}
978
979
980int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
981int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
982int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
983int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
984int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
985int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
986
987int __must_check pci_enable_device(struct pci_dev *dev);
988int __must_check pci_enable_device_io(struct pci_dev *dev);
989int __must_check pci_enable_device_mem(struct pci_dev *dev);
990int __must_check pci_reenable_device(struct pci_dev *);
991int __must_check pcim_enable_device(struct pci_dev *pdev);
992void pcim_pin_device(struct pci_dev *pdev);
993
994static inline int pci_is_enabled(struct pci_dev *pdev)
995{
996 return (atomic_read(&pdev->enable_cnt) > 0);
997}
998
999static inline int pci_is_managed(struct pci_dev *pdev)
1000{
1001 return pdev->is_managed;
1002}
1003
1004void pci_disable_device(struct pci_dev *dev);
1005
1006extern unsigned int pcibios_max_latency;
1007void pci_set_master(struct pci_dev *dev);
1008void pci_clear_master(struct pci_dev *dev);
1009
1010int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1011int pci_set_cacheline_size(struct pci_dev *dev);
1012#define HAVE_PCI_SET_MWI
1013int __must_check pci_set_mwi(struct pci_dev *dev);
1014int pci_try_set_mwi(struct pci_dev *dev);
1015void pci_clear_mwi(struct pci_dev *dev);
1016void pci_intx(struct pci_dev *dev, int enable);
1017bool pci_intx_mask_supported(struct pci_dev *dev);
1018bool pci_check_and_mask_intx(struct pci_dev *dev);
1019bool pci_check_and_unmask_intx(struct pci_dev *dev);
1020int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1021int pci_wait_for_pending_transaction(struct pci_dev *dev);
1022int pcix_get_max_mmrbc(struct pci_dev *dev);
1023int pcix_get_mmrbc(struct pci_dev *dev);
1024int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1025int pcie_get_readrq(struct pci_dev *dev);
1026int pcie_set_readrq(struct pci_dev *dev, int rq);
1027int pcie_get_mps(struct pci_dev *dev);
1028int pcie_set_mps(struct pci_dev *dev, int mps);
1029int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1030 enum pcie_link_width *width);
1031int __pci_reset_function(struct pci_dev *dev);
1032int __pci_reset_function_locked(struct pci_dev *dev);
1033int pci_reset_function(struct pci_dev *dev);
1034int pci_try_reset_function(struct pci_dev *dev);
1035int pci_probe_reset_slot(struct pci_slot *slot);
1036int pci_reset_slot(struct pci_slot *slot);
1037int pci_try_reset_slot(struct pci_slot *slot);
1038int pci_probe_reset_bus(struct pci_bus *bus);
1039int pci_reset_bus(struct pci_bus *bus);
1040int pci_try_reset_bus(struct pci_bus *bus);
1041void pci_reset_secondary_bus(struct pci_dev *dev);
1042void pcibios_reset_secondary_bus(struct pci_dev *dev);
1043void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1044void pci_update_resource(struct pci_dev *dev, int resno);
1045int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1046int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1047int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1048bool pci_device_is_present(struct pci_dev *pdev);
1049void pci_ignore_hotplug(struct pci_dev *dev);
1050
1051
1052int pci_enable_rom(struct pci_dev *pdev);
1053void pci_disable_rom(struct pci_dev *pdev);
1054void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1055void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1056size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1057void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1058
1059
1060int pci_save_state(struct pci_dev *dev);
1061void pci_restore_state(struct pci_dev *dev);
1062struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1063int pci_load_saved_state(struct pci_dev *dev,
1064 struct pci_saved_state *state);
1065int pci_load_and_free_saved_state(struct pci_dev *dev,
1066 struct pci_saved_state **state);
1067struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1068struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1069 u16 cap);
1070int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1071int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1072 u16 cap, unsigned int size);
1073int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1074int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1075pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1076bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1077void pci_pme_active(struct pci_dev *dev, bool enable);
1078int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1079 bool runtime, bool enable);
1080int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1081int pci_prepare_to_sleep(struct pci_dev *dev);
1082int pci_back_from_sleep(struct pci_dev *dev);
1083bool pci_dev_run_wake(struct pci_dev *dev);
1084bool pci_check_pme_status(struct pci_dev *dev);
1085void pci_pme_wakeup_bus(struct pci_bus *bus);
1086
1087static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1088 bool enable)
1089{
1090 return __pci_enable_wake(dev, state, false, enable);
1091}
1092
1093
1094int pci_save_vc_state(struct pci_dev *dev);
1095void pci_restore_vc_state(struct pci_dev *dev);
1096void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1097
1098
1099void set_pcie_port_type(struct pci_dev *pdev);
1100void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1101
1102
1103int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1104unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1105unsigned int pci_rescan_bus(struct pci_bus *bus);
1106void pci_lock_rescan_remove(void);
1107void pci_unlock_rescan_remove(void);
1108
1109
1110ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1111ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1112int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1113
1114
1115resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1116void pci_bus_assign_resources(const struct pci_bus *bus);
1117void pci_bus_size_bridges(struct pci_bus *bus);
1118int pci_claim_resource(struct pci_dev *, int);
1119int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1120void pci_assign_unassigned_resources(void);
1121void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1122void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1123void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1124void pdev_enable_device(struct pci_dev *);
1125int pci_enable_resources(struct pci_dev *, int mask);
1126void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1127 int (*)(const struct pci_dev *, u8, u8));
1128#define HAVE_PCI_REQ_REGIONS 2
1129int __must_check pci_request_regions(struct pci_dev *, const char *);
1130int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1131void pci_release_regions(struct pci_dev *);
1132int __must_check pci_request_region(struct pci_dev *, int, const char *);
1133int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1134void pci_release_region(struct pci_dev *, int);
1135int pci_request_selected_regions(struct pci_dev *, int, const char *);
1136int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1137void pci_release_selected_regions(struct pci_dev *, int);
1138
1139
1140struct pci_bus *pci_bus_get(struct pci_bus *bus);
1141void pci_bus_put(struct pci_bus *bus);
1142void pci_add_resource(struct list_head *resources, struct resource *res);
1143void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1144 resource_size_t offset);
1145void pci_free_resource_list(struct list_head *resources);
1146void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1147struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1148void pci_bus_remove_resources(struct pci_bus *bus);
1149
1150#define pci_bus_for_each_resource(bus, res, i) \
1151 for (i = 0; \
1152 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1153 i++)
1154
1155int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1156 struct resource *res, resource_size_t size,
1157 resource_size_t align, resource_size_t min,
1158 unsigned long type_mask,
1159 resource_size_t (*alignf)(void *,
1160 const struct resource *,
1161 resource_size_t,
1162 resource_size_t),
1163 void *alignf_data);
1164
1165
1166int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1167unsigned long pci_address_to_pio(phys_addr_t addr);
1168phys_addr_t pci_pio_to_address(unsigned long pio);
1169int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1170
1171static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1172{
1173 struct pci_bus_region region;
1174
1175 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1176 return region.start;
1177}
1178
1179
1180int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1181 const char *mod_name);
1182
1183
1184
1185
1186#define pci_register_driver(driver) \
1187 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1188
1189void pci_unregister_driver(struct pci_driver *dev);
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199#define module_pci_driver(__pci_driver) \
1200 module_driver(__pci_driver, pci_register_driver, \
1201 pci_unregister_driver)
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211#define builtin_pci_driver(__pci_driver) \
1212 builtin_driver(__pci_driver, pci_register_driver)
1213
1214struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1215int pci_add_dynid(struct pci_driver *drv,
1216 unsigned int vendor, unsigned int device,
1217 unsigned int subvendor, unsigned int subdevice,
1218 unsigned int class, unsigned int class_mask,
1219 unsigned long driver_data);
1220const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1221 struct pci_dev *dev);
1222int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1223 int pass);
1224
1225void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1226 void *userdata);
1227int pci_cfg_space_size(struct pci_dev *dev);
1228unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1229void pci_setup_bridge(struct pci_bus *bus);
1230resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1231 unsigned long type);
1232resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1233
1234#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1235#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1236
1237int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1238 unsigned int command_bits, u32 flags);
1239
1240
1241
1242#include <linux/pci-dma.h>
1243#include <linux/dmapool.h>
1244
1245#define pci_pool dma_pool
1246#define pci_pool_create(name, pdev, size, align, allocation) \
1247 dma_pool_create(name, &pdev->dev, size, align, allocation)
1248#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1249#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1250#define pci_pool_zalloc(pool, flags, handle) \
1251 dma_pool_zalloc(pool, flags, handle)
1252#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1253
1254struct msix_entry {
1255 u32 vector;
1256 u16 entry;
1257};
1258
1259#ifdef CONFIG_PCI_MSI
1260int pci_msi_vec_count(struct pci_dev *dev);
1261void pci_msi_shutdown(struct pci_dev *dev);
1262void pci_disable_msi(struct pci_dev *dev);
1263int pci_msix_vec_count(struct pci_dev *dev);
1264int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1265void pci_msix_shutdown(struct pci_dev *dev);
1266void pci_disable_msix(struct pci_dev *dev);
1267void pci_restore_msi_state(struct pci_dev *dev);
1268int pci_msi_enabled(void);
1269int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1270static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1271{
1272 int rc = pci_enable_msi_range(dev, nvec, nvec);
1273 if (rc < 0)
1274 return rc;
1275 return 0;
1276}
1277int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1278 int minvec, int maxvec);
1279static inline int pci_enable_msix_exact(struct pci_dev *dev,
1280 struct msix_entry *entries, int nvec)
1281{
1282 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1283 if (rc < 0)
1284 return rc;
1285 return 0;
1286}
1287#else
1288static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1289static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1290static inline void pci_disable_msi(struct pci_dev *dev) { }
1291static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1292static inline int pci_enable_msix(struct pci_dev *dev,
1293 struct msix_entry *entries, int nvec)
1294{ return -ENOSYS; }
1295static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1296static inline void pci_disable_msix(struct pci_dev *dev) { }
1297static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1298static inline int pci_msi_enabled(void) { return 0; }
1299static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1300 int maxvec)
1301{ return -ENOSYS; }
1302static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1303{ return -ENOSYS; }
1304static inline int pci_enable_msix_range(struct pci_dev *dev,
1305 struct msix_entry *entries, int minvec, int maxvec)
1306{ return -ENOSYS; }
1307static inline int pci_enable_msix_exact(struct pci_dev *dev,
1308 struct msix_entry *entries, int nvec)
1309{ return -ENOSYS; }
1310#endif
1311
1312#ifdef CONFIG_PCIEPORTBUS
1313extern bool pcie_ports_disabled;
1314extern bool pcie_ports_auto;
1315#else
1316#define pcie_ports_disabled true
1317#define pcie_ports_auto false
1318#endif
1319
1320#ifdef CONFIG_PCIEASPM
1321bool pcie_aspm_support_enabled(void);
1322#else
1323static inline bool pcie_aspm_support_enabled(void) { return false; }
1324#endif
1325
1326#ifdef CONFIG_PCIEAER
1327void pci_no_aer(void);
1328bool pci_aer_available(void);
1329#else
1330static inline void pci_no_aer(void) { }
1331static inline bool pci_aer_available(void) { return false; }
1332#endif
1333
1334#ifdef CONFIG_PCIE_ECRC
1335void pcie_set_ecrc_checking(struct pci_dev *dev);
1336void pcie_ecrc_get_policy(char *str);
1337#else
1338static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1339static inline void pcie_ecrc_get_policy(char *str) { }
1340#endif
1341
1342#define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1343
1344#ifdef CONFIG_HT_IRQ
1345
1346int ht_create_irq(struct pci_dev *dev, int idx);
1347void ht_destroy_irq(unsigned int irq);
1348#endif
1349
1350#ifdef CONFIG_PCI_ATS
1351
1352void pci_ats_init(struct pci_dev *dev);
1353int pci_enable_ats(struct pci_dev *dev, int ps);
1354void pci_disable_ats(struct pci_dev *dev);
1355int pci_ats_queue_depth(struct pci_dev *dev);
1356#else
1357static inline void pci_ats_init(struct pci_dev *d) { }
1358static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1359static inline void pci_disable_ats(struct pci_dev *d) { }
1360static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1361#endif
1362
1363void pci_cfg_access_lock(struct pci_dev *dev);
1364bool pci_cfg_access_trylock(struct pci_dev *dev);
1365void pci_cfg_access_unlock(struct pci_dev *dev);
1366
1367
1368
1369
1370
1371
1372#ifdef CONFIG_PCI_DOMAINS
1373extern int pci_domains_supported;
1374int pci_get_new_domain_nr(void);
1375#else
1376enum { pci_domains_supported = 0 };
1377static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1378static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1379static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1380#endif
1381
1382
1383
1384
1385
1386
1387#ifdef CONFIG_PCI_DOMAINS_GENERIC
1388static inline int pci_domain_nr(struct pci_bus *bus)
1389{
1390 return bus->domain_nr;
1391}
1392void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent);
1393#else
1394static inline void pci_bus_assign_domain_nr(struct pci_bus *bus,
1395 struct device *parent)
1396{
1397}
1398#endif
1399
1400
1401typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1402 unsigned int command_bits, u32 flags);
1403void pci_register_set_vga_state(arch_set_vga_state_t func);
1404
1405#else
1406
1407static inline void pci_set_flags(int flags) { }
1408static inline void pci_add_flags(int flags) { }
1409static inline void pci_clear_flags(int flags) { }
1410static inline int pci_has_flag(int flag) { return 0; }
1411
1412
1413
1414
1415
1416
1417#define _PCI_NOP(o, s, t) \
1418 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1419 int where, t val) \
1420 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1421
1422#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1423 _PCI_NOP(o, word, u16 x) \
1424 _PCI_NOP(o, dword, u32 x)
1425_PCI_NOP_ALL(read, *)
1426_PCI_NOP_ALL(write,)
1427
1428static inline struct pci_dev *pci_get_device(unsigned int vendor,
1429 unsigned int device,
1430 struct pci_dev *from)
1431{ return NULL; }
1432
1433static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1434 unsigned int device,
1435 unsigned int ss_vendor,
1436 unsigned int ss_device,
1437 struct pci_dev *from)
1438{ return NULL; }
1439
1440static inline struct pci_dev *pci_get_class(unsigned int class,
1441 struct pci_dev *from)
1442{ return NULL; }
1443
1444#define pci_dev_present(ids) (0)
1445#define no_pci_devices() (1)
1446#define pci_dev_put(dev) do { } while (0)
1447
1448static inline void pci_set_master(struct pci_dev *dev) { }
1449static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1450static inline void pci_disable_device(struct pci_dev *dev) { }
1451static inline int pci_assign_resource(struct pci_dev *dev, int i)
1452{ return -EBUSY; }
1453static inline int __pci_register_driver(struct pci_driver *drv,
1454 struct module *owner)
1455{ return 0; }
1456static inline int pci_register_driver(struct pci_driver *drv)
1457{ return 0; }
1458static inline void pci_unregister_driver(struct pci_driver *drv) { }
1459static inline int pci_find_capability(struct pci_dev *dev, int cap)
1460{ return 0; }
1461static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1462 int cap)
1463{ return 0; }
1464static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1465{ return 0; }
1466
1467
1468static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1469static inline void pci_restore_state(struct pci_dev *dev) { }
1470static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1471{ return 0; }
1472static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1473{ return 0; }
1474static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1475 pm_message_t state)
1476{ return PCI_D0; }
1477static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1478 int enable)
1479{ return 0; }
1480
1481static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1482{ return -EIO; }
1483static inline void pci_release_regions(struct pci_dev *dev) { }
1484
1485static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1486
1487static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1488static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1489{ return 0; }
1490static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1491
1492static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1493{ return NULL; }
1494static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1495 unsigned int devfn)
1496{ return NULL; }
1497static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1498 unsigned int devfn)
1499{ return NULL; }
1500
1501static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1502static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1503static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1504
1505#define dev_is_pci(d) (false)
1506#define dev_is_pf(d) (false)
1507#define dev_num_vf(d) (0)
1508#endif
1509
1510
1511
1512#include <asm/pci.h>
1513
1514#ifndef pci_root_bus_fwnode
1515#define pci_root_bus_fwnode(bus) NULL
1516#endif
1517
1518
1519
1520#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1521#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1522#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1523#define pci_resource_len(dev,bar) \
1524 ((pci_resource_start((dev), (bar)) == 0 && \
1525 pci_resource_end((dev), (bar)) == \
1526 pci_resource_start((dev), (bar))) ? 0 : \
1527 \
1528 (pci_resource_end((dev), (bar)) - \
1529 pci_resource_start((dev), (bar)) + 1))
1530
1531
1532
1533
1534
1535static inline void *pci_get_drvdata(struct pci_dev *pdev)
1536{
1537 return dev_get_drvdata(&pdev->dev);
1538}
1539
1540static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1541{
1542 dev_set_drvdata(&pdev->dev, data);
1543}
1544
1545
1546
1547
1548static inline const char *pci_name(const struct pci_dev *pdev)
1549{
1550 return dev_name(&pdev->dev);
1551}
1552
1553
1554
1555
1556
1557#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1558static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1559 const struct resource *rsrc, resource_size_t *start,
1560 resource_size_t *end)
1561{
1562 *start = rsrc->start;
1563 *end = rsrc->end;
1564}
1565#endif
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575struct pci_fixup {
1576 u16 vendor;
1577 u16 device;
1578 u32 class;
1579 unsigned int class_shift;
1580 void (*hook)(struct pci_dev *dev);
1581};
1582
1583enum pci_fixup_pass {
1584 pci_fixup_early,
1585 pci_fixup_header,
1586 pci_fixup_final,
1587 pci_fixup_enable,
1588 pci_fixup_resume,
1589 pci_fixup_suspend,
1590 pci_fixup_resume_early,
1591 pci_fixup_suspend_late,
1592};
1593
1594
1595#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1596 class_shift, hook) \
1597 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1598 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1599 = { vendor, device, class, class_shift, hook };
1600
1601#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1602 class_shift, hook) \
1603 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1604 hook, vendor, device, class, class_shift, hook)
1605#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1606 class_shift, hook) \
1607 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1608 hook, vendor, device, class, class_shift, hook)
1609#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1610 class_shift, hook) \
1611 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1612 hook, vendor, device, class, class_shift, hook)
1613#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1614 class_shift, hook) \
1615 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1616 hook, vendor, device, class, class_shift, hook)
1617#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1618 class_shift, hook) \
1619 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1620 resume##hook, vendor, device, class, \
1621 class_shift, hook)
1622#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1623 class_shift, hook) \
1624 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1625 resume_early##hook, vendor, device, \
1626 class, class_shift, hook)
1627#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1628 class_shift, hook) \
1629 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1630 suspend##hook, vendor, device, class, \
1631 class_shift, hook)
1632#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1633 class_shift, hook) \
1634 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1635 suspend_late##hook, vendor, device, \
1636 class, class_shift, hook)
1637
1638#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1639 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1640 hook, vendor, device, PCI_ANY_ID, 0, hook)
1641#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1642 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1643 hook, vendor, device, PCI_ANY_ID, 0, hook)
1644#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1645 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1646 hook, vendor, device, PCI_ANY_ID, 0, hook)
1647#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1648 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1649 hook, vendor, device, PCI_ANY_ID, 0, hook)
1650#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1651 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1652 resume##hook, vendor, device, \
1653 PCI_ANY_ID, 0, hook)
1654#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1655 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1656 resume_early##hook, vendor, device, \
1657 PCI_ANY_ID, 0, hook)
1658#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1659 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1660 suspend##hook, vendor, device, \
1661 PCI_ANY_ID, 0, hook)
1662#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1663 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1664 suspend_late##hook, vendor, device, \
1665 PCI_ANY_ID, 0, hook)
1666
1667#ifdef CONFIG_PCI_QUIRKS
1668void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1669int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1670int pci_dev_specific_enable_acs(struct pci_dev *dev);
1671#else
1672static inline void pci_fixup_device(enum pci_fixup_pass pass,
1673 struct pci_dev *dev) { }
1674static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1675 u16 acs_flags)
1676{
1677 return -ENOTTY;
1678}
1679static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1680{
1681 return -ENOTTY;
1682}
1683#endif
1684
1685void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1686void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1687void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1688int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1689int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1690 const char *name);
1691void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1692
1693extern int pci_pci_problems;
1694#define PCIPCI_FAIL 1
1695#define PCIPCI_TRITON 2
1696#define PCIPCI_NATOMA 4
1697#define PCIPCI_VIAETBF 8
1698#define PCIPCI_VSFX 16
1699#define PCIPCI_ALIMAGIK 32
1700#define PCIAGP_FAIL 64
1701
1702extern unsigned long pci_cardbus_io_size;
1703extern unsigned long pci_cardbus_mem_size;
1704extern u8 pci_dfl_cache_line_size;
1705extern u8 pci_cache_line_size;
1706
1707extern unsigned long pci_hotplug_io_size;
1708extern unsigned long pci_hotplug_mem_size;
1709
1710
1711void pcibios_disable_device(struct pci_dev *dev);
1712void pcibios_set_master(struct pci_dev *dev);
1713int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1714 enum pcie_reset_state state);
1715int pcibios_add_device(struct pci_dev *dev);
1716void pcibios_release_device(struct pci_dev *dev);
1717void pcibios_penalize_isa_irq(int irq, int active);
1718int pcibios_alloc_irq(struct pci_dev *dev);
1719void pcibios_free_irq(struct pci_dev *dev);
1720
1721#ifdef CONFIG_HIBERNATE_CALLBACKS
1722extern struct dev_pm_ops pcibios_pm_ops;
1723#endif
1724
1725#ifdef CONFIG_PCI_MMCONFIG
1726void __init pci_mmcfg_early_init(void);
1727void __init pci_mmcfg_late_init(void);
1728#else
1729static inline void pci_mmcfg_early_init(void) { }
1730static inline void pci_mmcfg_late_init(void) { }
1731#endif
1732
1733int pci_ext_cfg_avail(void);
1734
1735void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1736void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1737
1738#ifdef CONFIG_PCI_IOV
1739int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1740int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1741
1742int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1743void pci_disable_sriov(struct pci_dev *dev);
1744int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1745void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1746int pci_num_vf(struct pci_dev *dev);
1747int pci_vfs_assigned(struct pci_dev *dev);
1748int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1749int pci_sriov_get_totalvfs(struct pci_dev *dev);
1750resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1751#else
1752static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1753{
1754 return -ENOSYS;
1755}
1756static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1757{
1758 return -ENOSYS;
1759}
1760static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1761{ return -ENODEV; }
1762static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1763{
1764 return -ENOSYS;
1765}
1766static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1767 int id, int reset) { }
1768static inline void pci_disable_sriov(struct pci_dev *dev) { }
1769static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1770static inline int pci_vfs_assigned(struct pci_dev *dev)
1771{ return 0; }
1772static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1773{ return 0; }
1774static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1775{ return 0; }
1776static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1777{ return 0; }
1778#endif
1779
1780#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1781void pci_hp_create_module_link(struct pci_slot *pci_slot);
1782void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1783#endif
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796static inline int pci_pcie_cap(struct pci_dev *dev)
1797{
1798 return dev->pcie_cap;
1799}
1800
1801
1802
1803
1804
1805
1806
1807static inline bool pci_is_pcie(struct pci_dev *dev)
1808{
1809 return pci_pcie_cap(dev);
1810}
1811
1812
1813
1814
1815
1816static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1817{
1818 return dev->pcie_flags_reg;
1819}
1820
1821
1822
1823
1824
1825static inline int pci_pcie_type(const struct pci_dev *dev)
1826{
1827 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1828}
1829
1830void pci_request_acs(void);
1831bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1832bool pci_acs_path_enabled(struct pci_dev *start,
1833 struct pci_dev *end, u16 acs_flags);
1834
1835#define PCI_VPD_LRDT 0x80
1836#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1837
1838
1839#define PCI_VPD_LTIN_ID_STRING 0x02
1840#define PCI_VPD_LTIN_RO_DATA 0x10
1841#define PCI_VPD_LTIN_RW_DATA 0x11
1842
1843#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1844#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1845#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1846
1847
1848#define PCI_VPD_STIN_END 0x0f
1849
1850#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
1851
1852#define PCI_VPD_SRDT_TIN_MASK 0x78
1853#define PCI_VPD_SRDT_LEN_MASK 0x07
1854#define PCI_VPD_LRDT_TIN_MASK 0x7f
1855
1856#define PCI_VPD_LRDT_TAG_SIZE 3
1857#define PCI_VPD_SRDT_TAG_SIZE 1
1858
1859#define PCI_VPD_INFO_FLD_HDR_SIZE 3
1860
1861#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1862#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1863#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1864#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1865
1866
1867
1868
1869
1870
1871
1872static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1873{
1874 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1875}
1876
1877
1878
1879
1880
1881
1882
1883static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
1884{
1885 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
1886}
1887
1888
1889
1890
1891
1892
1893
1894static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1895{
1896 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1897}
1898
1899
1900
1901
1902
1903
1904
1905static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
1906{
1907 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
1908}
1909
1910
1911
1912
1913
1914
1915
1916static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1917{
1918 return info_field[2];
1919}
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1932
1933
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1941
1942
1943int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1944 unsigned int len, const char *kw);
1945
1946
1947#ifdef CONFIG_OF
1948struct device_node;
1949struct irq_domain;
1950void pci_set_of_node(struct pci_dev *dev);
1951void pci_release_of_node(struct pci_dev *dev);
1952void pci_set_bus_of_node(struct pci_bus *bus);
1953void pci_release_bus_of_node(struct pci_bus *bus);
1954struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
1955
1956
1957struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1958
1959static inline struct device_node *
1960pci_device_to_OF_node(const struct pci_dev *pdev)
1961{
1962 return pdev ? pdev->dev.of_node : NULL;
1963}
1964
1965static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1966{
1967 return bus ? bus->dev.of_node : NULL;
1968}
1969
1970#else
1971static inline void pci_set_of_node(struct pci_dev *dev) { }
1972static inline void pci_release_of_node(struct pci_dev *dev) { }
1973static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1974static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1975static inline struct device_node *
1976pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
1977static inline struct irq_domain *
1978pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
1979#endif
1980
1981#ifdef CONFIG_ACPI
1982struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
1983
1984void
1985pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
1986#else
1987static inline struct irq_domain *
1988pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
1989#endif
1990
1991#ifdef CONFIG_EEH
1992static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1993{
1994 return pdev->dev.archdata.edev;
1995}
1996#endif
1997
1998void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
1999bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2000int pci_for_each_dma_alias(struct pci_dev *pdev,
2001 int (*fn)(struct pci_dev *pdev,
2002 u16 alias, void *data), void *data);
2003
2004
2005static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2006{
2007 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2008}
2009static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2010{
2011 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2012}
2013static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2014{
2015 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2016}
2017
2018
2019
2020
2021
2022
2023
2024static inline bool pci_ari_enabled(struct pci_bus *bus)
2025{
2026 return bus->self && bus->self->ari_enabled;
2027}
2028
2029
2030#include <linux/pci-dma-compat.h>
2031
2032#endif
2033