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23#ifndef _UAPI__SOUND_ASOUND_H
24#define _UAPI__SOUND_ASOUND_H
25
26#if defined(__KERNEL__) || defined(__linux__)
27#include <linux/types.h>
28#else
29#include <sys/ioctl.h>
30#endif
31
32#ifndef __KERNEL__
33#include <stdlib.h>
34#endif
35
36
37
38
39
40#define SNDRV_PROTOCOL_VERSION(major, minor, subminor) (((major)<<16)|((minor)<<8)|(subminor))
41#define SNDRV_PROTOCOL_MAJOR(version) (((version)>>16)&0xffff)
42#define SNDRV_PROTOCOL_MINOR(version) (((version)>>8)&0xff)
43#define SNDRV_PROTOCOL_MICRO(version) ((version)&0xff)
44#define SNDRV_PROTOCOL_INCOMPATIBLE(kversion, uversion) \
45 (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || \
46 (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && \
47 SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion)))
48
49
50
51
52
53
54
55struct snd_aes_iec958 {
56 unsigned char status[24];
57 unsigned char subcode[147];
58 unsigned char pad;
59 unsigned char dig_subframe[4];
60};
61
62
63
64
65
66
67
68struct snd_cea_861_aud_if {
69 unsigned char db1_ct_cc;
70 unsigned char db2_sf_ss;
71 unsigned char db3;
72 unsigned char db4_ca;
73 unsigned char db5_dminh_lsv;
74};
75
76
77
78
79
80
81
82#define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
83
84enum {
85 SNDRV_HWDEP_IFACE_OPL2 = 0,
86 SNDRV_HWDEP_IFACE_OPL3,
87 SNDRV_HWDEP_IFACE_OPL4,
88 SNDRV_HWDEP_IFACE_SB16CSP,
89 SNDRV_HWDEP_IFACE_EMU10K1,
90 SNDRV_HWDEP_IFACE_YSS225,
91 SNDRV_HWDEP_IFACE_ICS2115,
92 SNDRV_HWDEP_IFACE_SSCAPE,
93 SNDRV_HWDEP_IFACE_VX,
94 SNDRV_HWDEP_IFACE_MIXART,
95 SNDRV_HWDEP_IFACE_USX2Y,
96 SNDRV_HWDEP_IFACE_EMUX_WAVETABLE,
97 SNDRV_HWDEP_IFACE_BLUETOOTH,
98 SNDRV_HWDEP_IFACE_USX2Y_PCM,
99 SNDRV_HWDEP_IFACE_PCXHR,
100 SNDRV_HWDEP_IFACE_SB_RC,
101 SNDRV_HWDEP_IFACE_HDA,
102 SNDRV_HWDEP_IFACE_USB_STREAM,
103 SNDRV_HWDEP_IFACE_FW_DICE,
104 SNDRV_HWDEP_IFACE_FW_FIREWORKS,
105 SNDRV_HWDEP_IFACE_FW_BEBOB,
106 SNDRV_HWDEP_IFACE_FW_OXFW,
107 SNDRV_HWDEP_IFACE_FW_DIGI00X,
108 SNDRV_HWDEP_IFACE_FW_TASCAM,
109
110
111 SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_FW_TASCAM
112};
113
114struct snd_hwdep_info {
115 unsigned int device;
116 int card;
117 unsigned char id[64];
118 unsigned char name[80];
119 int iface;
120 unsigned char reserved[64];
121};
122
123
124struct snd_hwdep_dsp_status {
125 unsigned int version;
126 unsigned char id[32];
127 unsigned int num_dsps;
128 unsigned int dsp_loaded;
129 unsigned int chip_ready;
130 unsigned char reserved[16];
131};
132
133struct snd_hwdep_dsp_image {
134 unsigned int index;
135 unsigned char name[64];
136 unsigned char __user *image;
137 size_t length;
138 unsigned long driver_data;
139};
140
141#define SNDRV_HWDEP_IOCTL_PVERSION _IOR ('H', 0x00, int)
142#define SNDRV_HWDEP_IOCTL_INFO _IOR ('H', 0x01, struct snd_hwdep_info)
143#define SNDRV_HWDEP_IOCTL_DSP_STATUS _IOR('H', 0x02, struct snd_hwdep_dsp_status)
144#define SNDRV_HWDEP_IOCTL_DSP_LOAD _IOW('H', 0x03, struct snd_hwdep_dsp_image)
145
146
147
148
149
150
151
152#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 13)
153
154typedef unsigned long snd_pcm_uframes_t;
155typedef signed long snd_pcm_sframes_t;
156
157enum {
158 SNDRV_PCM_CLASS_GENERIC = 0,
159 SNDRV_PCM_CLASS_MULTI,
160 SNDRV_PCM_CLASS_MODEM,
161 SNDRV_PCM_CLASS_DIGITIZER,
162
163 SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER,
164};
165
166enum {
167 SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0,
168 SNDRV_PCM_SUBCLASS_MULTI_MIX,
169
170 SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX,
171};
172
173enum {
174 SNDRV_PCM_STREAM_PLAYBACK = 0,
175 SNDRV_PCM_STREAM_CAPTURE,
176 SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE,
177};
178
179typedef int __bitwise snd_pcm_access_t;
180#define SNDRV_PCM_ACCESS_MMAP_INTERLEAVED ((__force snd_pcm_access_t) 0)
181#define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED ((__force snd_pcm_access_t) 1)
182#define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((__force snd_pcm_access_t) 2)
183#define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((__force snd_pcm_access_t) 3)
184#define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED ((__force snd_pcm_access_t) 4)
185#define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED
186
187typedef int __bitwise snd_pcm_format_t;
188#define SNDRV_PCM_FORMAT_S8 ((__force snd_pcm_format_t) 0)
189#define SNDRV_PCM_FORMAT_U8 ((__force snd_pcm_format_t) 1)
190#define SNDRV_PCM_FORMAT_S16_LE ((__force snd_pcm_format_t) 2)
191#define SNDRV_PCM_FORMAT_S16_BE ((__force snd_pcm_format_t) 3)
192#define SNDRV_PCM_FORMAT_U16_LE ((__force snd_pcm_format_t) 4)
193#define SNDRV_PCM_FORMAT_U16_BE ((__force snd_pcm_format_t) 5)
194#define SNDRV_PCM_FORMAT_S24_LE ((__force snd_pcm_format_t) 6)
195#define SNDRV_PCM_FORMAT_S24_BE ((__force snd_pcm_format_t) 7)
196#define SNDRV_PCM_FORMAT_U24_LE ((__force snd_pcm_format_t) 8)
197#define SNDRV_PCM_FORMAT_U24_BE ((__force snd_pcm_format_t) 9)
198#define SNDRV_PCM_FORMAT_S32_LE ((__force snd_pcm_format_t) 10)
199#define SNDRV_PCM_FORMAT_S32_BE ((__force snd_pcm_format_t) 11)
200#define SNDRV_PCM_FORMAT_U32_LE ((__force snd_pcm_format_t) 12)
201#define SNDRV_PCM_FORMAT_U32_BE ((__force snd_pcm_format_t) 13)
202#define SNDRV_PCM_FORMAT_FLOAT_LE ((__force snd_pcm_format_t) 14)
203#define SNDRV_PCM_FORMAT_FLOAT_BE ((__force snd_pcm_format_t) 15)
204#define SNDRV_PCM_FORMAT_FLOAT64_LE ((__force snd_pcm_format_t) 16)
205#define SNDRV_PCM_FORMAT_FLOAT64_BE ((__force snd_pcm_format_t) 17)
206#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE ((__force snd_pcm_format_t) 18)
207#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE ((__force snd_pcm_format_t) 19)
208#define SNDRV_PCM_FORMAT_MU_LAW ((__force snd_pcm_format_t) 20)
209#define SNDRV_PCM_FORMAT_A_LAW ((__force snd_pcm_format_t) 21)
210#define SNDRV_PCM_FORMAT_IMA_ADPCM ((__force snd_pcm_format_t) 22)
211#define SNDRV_PCM_FORMAT_MPEG ((__force snd_pcm_format_t) 23)
212#define SNDRV_PCM_FORMAT_GSM ((__force snd_pcm_format_t) 24)
213#define SNDRV_PCM_FORMAT_SPECIAL ((__force snd_pcm_format_t) 31)
214#define SNDRV_PCM_FORMAT_S24_3LE ((__force snd_pcm_format_t) 32)
215#define SNDRV_PCM_FORMAT_S24_3BE ((__force snd_pcm_format_t) 33)
216#define SNDRV_PCM_FORMAT_U24_3LE ((__force snd_pcm_format_t) 34)
217#define SNDRV_PCM_FORMAT_U24_3BE ((__force snd_pcm_format_t) 35)
218#define SNDRV_PCM_FORMAT_S20_3LE ((__force snd_pcm_format_t) 36)
219#define SNDRV_PCM_FORMAT_S20_3BE ((__force snd_pcm_format_t) 37)
220#define SNDRV_PCM_FORMAT_U20_3LE ((__force snd_pcm_format_t) 38)
221#define SNDRV_PCM_FORMAT_U20_3BE ((__force snd_pcm_format_t) 39)
222#define SNDRV_PCM_FORMAT_S18_3LE ((__force snd_pcm_format_t) 40)
223#define SNDRV_PCM_FORMAT_S18_3BE ((__force snd_pcm_format_t) 41)
224#define SNDRV_PCM_FORMAT_U18_3LE ((__force snd_pcm_format_t) 42)
225#define SNDRV_PCM_FORMAT_U18_3BE ((__force snd_pcm_format_t) 43)
226#define SNDRV_PCM_FORMAT_G723_24 ((__force snd_pcm_format_t) 44)
227#define SNDRV_PCM_FORMAT_G723_24_1B ((__force snd_pcm_format_t) 45)
228#define SNDRV_PCM_FORMAT_G723_40 ((__force snd_pcm_format_t) 46)
229#define SNDRV_PCM_FORMAT_G723_40_1B ((__force snd_pcm_format_t) 47)
230#define SNDRV_PCM_FORMAT_DSD_U8 ((__force snd_pcm_format_t) 48)
231#define SNDRV_PCM_FORMAT_DSD_U16_LE ((__force snd_pcm_format_t) 49)
232#define SNDRV_PCM_FORMAT_DSD_U32_LE ((__force snd_pcm_format_t) 50)
233#define SNDRV_PCM_FORMAT_DSD_U16_BE ((__force snd_pcm_format_t) 51)
234#define SNDRV_PCM_FORMAT_DSD_U32_BE ((__force snd_pcm_format_t) 52)
235#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_DSD_U32_BE
236
237#ifdef SNDRV_LITTLE_ENDIAN
238#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE
239#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_LE
240#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_LE
241#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_LE
242#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_LE
243#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_LE
244#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE
245#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE
246#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE
247#endif
248#ifdef SNDRV_BIG_ENDIAN
249#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE
250#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_BE
251#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_BE
252#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_BE
253#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_BE
254#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_BE
255#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE
256#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE
257#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE
258#endif
259
260typedef int __bitwise snd_pcm_subformat_t;
261#define SNDRV_PCM_SUBFORMAT_STD ((__force snd_pcm_subformat_t) 0)
262#define SNDRV_PCM_SUBFORMAT_LAST SNDRV_PCM_SUBFORMAT_STD
263
264#define SNDRV_PCM_INFO_MMAP 0x00000001
265#define SNDRV_PCM_INFO_MMAP_VALID 0x00000002
266#define SNDRV_PCM_INFO_DOUBLE 0x00000004
267#define SNDRV_PCM_INFO_BATCH 0x00000010
268#define SNDRV_PCM_INFO_INTERLEAVED 0x00000100
269#define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200
270#define SNDRV_PCM_INFO_COMPLEX 0x00000400
271#define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000
272#define SNDRV_PCM_INFO_OVERRANGE 0x00020000
273#define SNDRV_PCM_INFO_RESUME 0x00040000
274#define SNDRV_PCM_INFO_PAUSE 0x00080000
275#define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000
276#define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000
277#define SNDRV_PCM_INFO_SYNC_START 0x00400000
278#define SNDRV_PCM_INFO_NO_PERIOD_WAKEUP 0x00800000
279#define SNDRV_PCM_INFO_HAS_WALL_CLOCK 0x01000000
280#define SNDRV_PCM_INFO_HAS_LINK_ATIME 0x01000000
281#define SNDRV_PCM_INFO_HAS_LINK_ABSOLUTE_ATIME 0x02000000
282#define SNDRV_PCM_INFO_HAS_LINK_ESTIMATED_ATIME 0x04000000
283#define SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 0x08000000
284
285#define SNDRV_PCM_INFO_DRAIN_TRIGGER 0x40000000
286#define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000
287
288
289
290typedef int __bitwise snd_pcm_state_t;
291#define SNDRV_PCM_STATE_OPEN ((__force snd_pcm_state_t) 0)
292#define SNDRV_PCM_STATE_SETUP ((__force snd_pcm_state_t) 1)
293#define SNDRV_PCM_STATE_PREPARED ((__force snd_pcm_state_t) 2)
294#define SNDRV_PCM_STATE_RUNNING ((__force snd_pcm_state_t) 3)
295#define SNDRV_PCM_STATE_XRUN ((__force snd_pcm_state_t) 4)
296#define SNDRV_PCM_STATE_DRAINING ((__force snd_pcm_state_t) 5)
297#define SNDRV_PCM_STATE_PAUSED ((__force snd_pcm_state_t) 6)
298#define SNDRV_PCM_STATE_SUSPENDED ((__force snd_pcm_state_t) 7)
299#define SNDRV_PCM_STATE_DISCONNECTED ((__force snd_pcm_state_t) 8)
300#define SNDRV_PCM_STATE_LAST SNDRV_PCM_STATE_DISCONNECTED
301
302enum {
303 SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000,
304 SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000,
305 SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000,
306};
307
308union snd_pcm_sync_id {
309 unsigned char id[16];
310 unsigned short id16[8];
311 unsigned int id32[4];
312};
313
314struct snd_pcm_info {
315 unsigned int device;
316 unsigned int subdevice;
317 int stream;
318 int card;
319 unsigned char id[64];
320 unsigned char name[80];
321 unsigned char subname[32];
322 int dev_class;
323 int dev_subclass;
324 unsigned int subdevices_count;
325 unsigned int subdevices_avail;
326 union snd_pcm_sync_id sync;
327 unsigned char reserved[64];
328};
329
330typedef int snd_pcm_hw_param_t;
331#define SNDRV_PCM_HW_PARAM_ACCESS 0
332#define SNDRV_PCM_HW_PARAM_FORMAT 1
333#define SNDRV_PCM_HW_PARAM_SUBFORMAT 2
334#define SNDRV_PCM_HW_PARAM_FIRST_MASK SNDRV_PCM_HW_PARAM_ACCESS
335#define SNDRV_PCM_HW_PARAM_LAST_MASK SNDRV_PCM_HW_PARAM_SUBFORMAT
336
337#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS 8
338#define SNDRV_PCM_HW_PARAM_FRAME_BITS 9
339#define SNDRV_PCM_HW_PARAM_CHANNELS 10
340#define SNDRV_PCM_HW_PARAM_RATE 11
341#define SNDRV_PCM_HW_PARAM_PERIOD_TIME 12
342
343
344#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE 13
345
346
347#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES 14
348
349
350#define SNDRV_PCM_HW_PARAM_PERIODS 15
351
352
353#define SNDRV_PCM_HW_PARAM_BUFFER_TIME 16
354
355
356#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE 17
357#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES 18
358#define SNDRV_PCM_HW_PARAM_TICK_TIME 19
359#define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL SNDRV_PCM_HW_PARAM_SAMPLE_BITS
360#define SNDRV_PCM_HW_PARAM_LAST_INTERVAL SNDRV_PCM_HW_PARAM_TICK_TIME
361
362#define SNDRV_PCM_HW_PARAMS_NORESAMPLE (1<<0)
363#define SNDRV_PCM_HW_PARAMS_EXPORT_BUFFER (1<<1)
364#define SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP (1<<2)
365
366struct snd_interval {
367 unsigned int min, max;
368 unsigned int openmin:1,
369 openmax:1,
370 integer:1,
371 empty:1;
372};
373
374#define SNDRV_MASK_MAX 256
375
376struct snd_mask {
377 __u32 bits[(SNDRV_MASK_MAX+31)/32];
378};
379
380struct snd_pcm_hw_params {
381 unsigned int flags;
382 struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK -
383 SNDRV_PCM_HW_PARAM_FIRST_MASK + 1];
384 struct snd_mask mres[5];
385 struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL -
386 SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1];
387 struct snd_interval ires[9];
388 unsigned int rmask;
389 unsigned int cmask;
390 unsigned int info;
391 unsigned int msbits;
392 unsigned int rate_num;
393 unsigned int rate_den;
394 snd_pcm_uframes_t fifo_size;
395 unsigned char reserved[64];
396};
397
398enum {
399 SNDRV_PCM_TSTAMP_NONE = 0,
400 SNDRV_PCM_TSTAMP_ENABLE,
401 SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_ENABLE,
402};
403
404struct snd_pcm_sw_params {
405 int tstamp_mode;
406 unsigned int period_step;
407 unsigned int sleep_min;
408 snd_pcm_uframes_t avail_min;
409 snd_pcm_uframes_t xfer_align;
410 snd_pcm_uframes_t start_threshold;
411 snd_pcm_uframes_t stop_threshold;
412 snd_pcm_uframes_t silence_threshold;
413 snd_pcm_uframes_t silence_size;
414 snd_pcm_uframes_t boundary;
415 unsigned int proto;
416 unsigned int tstamp_type;
417 unsigned char reserved[56];
418};
419
420struct snd_pcm_channel_info {
421 unsigned int channel;
422 __kernel_off_t offset;
423 unsigned int first;
424 unsigned int step;
425};
426
427enum {
428
429
430
431
432 SNDRV_PCM_AUDIO_TSTAMP_TYPE_COMPAT = 0,
433
434
435 SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT = 1,
436 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK = 2,
437 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ABSOLUTE = 3,
438 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ESTIMATED = 4,
439 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED = 5,
440 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED
441};
442
443struct snd_pcm_status {
444 snd_pcm_state_t state;
445 struct timespec trigger_tstamp;
446 struct timespec tstamp;
447 snd_pcm_uframes_t appl_ptr;
448 snd_pcm_uframes_t hw_ptr;
449 snd_pcm_sframes_t delay;
450 snd_pcm_uframes_t avail;
451 snd_pcm_uframes_t avail_max;
452 snd_pcm_uframes_t overrange;
453 snd_pcm_state_t suspended_state;
454 __u32 audio_tstamp_data;
455 struct timespec audio_tstamp;
456 struct timespec driver_tstamp;
457 __u32 audio_tstamp_accuracy;
458 unsigned char reserved[52-2*sizeof(struct timespec)];
459};
460
461struct snd_pcm_mmap_status {
462 snd_pcm_state_t state;
463 int pad1;
464 snd_pcm_uframes_t hw_ptr;
465 struct timespec tstamp;
466 snd_pcm_state_t suspended_state;
467 struct timespec audio_tstamp;
468};
469
470struct snd_pcm_mmap_control {
471 snd_pcm_uframes_t appl_ptr;
472 snd_pcm_uframes_t avail_min;
473};
474
475#define SNDRV_PCM_SYNC_PTR_HWSYNC (1<<0)
476#define SNDRV_PCM_SYNC_PTR_APPL (1<<1)
477#define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2)
478
479struct snd_pcm_sync_ptr {
480 unsigned int flags;
481 union {
482 struct snd_pcm_mmap_status status;
483 unsigned char reserved[64];
484 } s;
485 union {
486 struct snd_pcm_mmap_control control;
487 unsigned char reserved[64];
488 } c;
489};
490
491struct snd_xferi {
492 snd_pcm_sframes_t result;
493 void __user *buf;
494 snd_pcm_uframes_t frames;
495};
496
497struct snd_xfern {
498 snd_pcm_sframes_t result;
499 void __user * __user *bufs;
500 snd_pcm_uframes_t frames;
501};
502
503enum {
504 SNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0,
505 SNDRV_PCM_TSTAMP_TYPE_MONOTONIC,
506 SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW,
507 SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW,
508};
509
510
511enum {
512 SNDRV_CHMAP_UNKNOWN = 0,
513 SNDRV_CHMAP_NA,
514 SNDRV_CHMAP_MONO,
515
516 SNDRV_CHMAP_FL,
517 SNDRV_CHMAP_FR,
518 SNDRV_CHMAP_RL,
519 SNDRV_CHMAP_RR,
520 SNDRV_CHMAP_FC,
521 SNDRV_CHMAP_LFE,
522 SNDRV_CHMAP_SL,
523 SNDRV_CHMAP_SR,
524 SNDRV_CHMAP_RC,
525
526 SNDRV_CHMAP_FLC,
527 SNDRV_CHMAP_FRC,
528 SNDRV_CHMAP_RLC,
529 SNDRV_CHMAP_RRC,
530 SNDRV_CHMAP_FLW,
531 SNDRV_CHMAP_FRW,
532 SNDRV_CHMAP_FLH,
533 SNDRV_CHMAP_FCH,
534 SNDRV_CHMAP_FRH,
535 SNDRV_CHMAP_TC,
536 SNDRV_CHMAP_TFL,
537 SNDRV_CHMAP_TFR,
538 SNDRV_CHMAP_TFC,
539 SNDRV_CHMAP_TRL,
540 SNDRV_CHMAP_TRR,
541 SNDRV_CHMAP_TRC,
542
543 SNDRV_CHMAP_TFLC,
544 SNDRV_CHMAP_TFRC,
545 SNDRV_CHMAP_TSL,
546 SNDRV_CHMAP_TSR,
547 SNDRV_CHMAP_LLFE,
548 SNDRV_CHMAP_RLFE,
549 SNDRV_CHMAP_BC,
550 SNDRV_CHMAP_BLC,
551 SNDRV_CHMAP_BRC,
552 SNDRV_CHMAP_LAST = SNDRV_CHMAP_BRC,
553};
554
555#define SNDRV_CHMAP_POSITION_MASK 0xffff
556#define SNDRV_CHMAP_PHASE_INVERSE (0x01 << 16)
557#define SNDRV_CHMAP_DRIVER_SPEC (0x02 << 16)
558
559#define SNDRV_PCM_IOCTL_PVERSION _IOR('A', 0x00, int)
560#define SNDRV_PCM_IOCTL_INFO _IOR('A', 0x01, struct snd_pcm_info)
561#define SNDRV_PCM_IOCTL_TSTAMP _IOW('A', 0x02, int)
562#define SNDRV_PCM_IOCTL_TTSTAMP _IOW('A', 0x03, int)
563#define SNDRV_PCM_IOCTL_HW_REFINE _IOWR('A', 0x10, struct snd_pcm_hw_params)
564#define SNDRV_PCM_IOCTL_HW_PARAMS _IOWR('A', 0x11, struct snd_pcm_hw_params)
565#define SNDRV_PCM_IOCTL_HW_FREE _IO('A', 0x12)
566#define SNDRV_PCM_IOCTL_SW_PARAMS _IOWR('A', 0x13, struct snd_pcm_sw_params)
567#define SNDRV_PCM_IOCTL_STATUS _IOR('A', 0x20, struct snd_pcm_status)
568#define SNDRV_PCM_IOCTL_DELAY _IOR('A', 0x21, snd_pcm_sframes_t)
569#define SNDRV_PCM_IOCTL_HWSYNC _IO('A', 0x22)
570#define SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct snd_pcm_sync_ptr)
571#define SNDRV_PCM_IOCTL_STATUS_EXT _IOWR('A', 0x24, struct snd_pcm_status)
572#define SNDRV_PCM_IOCTL_CHANNEL_INFO _IOR('A', 0x32, struct snd_pcm_channel_info)
573#define SNDRV_PCM_IOCTL_PREPARE _IO('A', 0x40)
574#define SNDRV_PCM_IOCTL_RESET _IO('A', 0x41)
575#define SNDRV_PCM_IOCTL_START _IO('A', 0x42)
576#define SNDRV_PCM_IOCTL_DROP _IO('A', 0x43)
577#define SNDRV_PCM_IOCTL_DRAIN _IO('A', 0x44)
578#define SNDRV_PCM_IOCTL_PAUSE _IOW('A', 0x45, int)
579#define SNDRV_PCM_IOCTL_REWIND _IOW('A', 0x46, snd_pcm_uframes_t)
580#define SNDRV_PCM_IOCTL_RESUME _IO('A', 0x47)
581#define SNDRV_PCM_IOCTL_XRUN _IO('A', 0x48)
582#define SNDRV_PCM_IOCTL_FORWARD _IOW('A', 0x49, snd_pcm_uframes_t)
583#define SNDRV_PCM_IOCTL_WRITEI_FRAMES _IOW('A', 0x50, struct snd_xferi)
584#define SNDRV_PCM_IOCTL_READI_FRAMES _IOR('A', 0x51, struct snd_xferi)
585#define SNDRV_PCM_IOCTL_WRITEN_FRAMES _IOW('A', 0x52, struct snd_xfern)
586#define SNDRV_PCM_IOCTL_READN_FRAMES _IOR('A', 0x53, struct snd_xfern)
587#define SNDRV_PCM_IOCTL_LINK _IOW('A', 0x60, int)
588#define SNDRV_PCM_IOCTL_UNLINK _IO('A', 0x61)
589
590
591
592
593
594
595
596
597
598
599
600#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0)
601
602enum {
603 SNDRV_RAWMIDI_STREAM_OUTPUT = 0,
604 SNDRV_RAWMIDI_STREAM_INPUT,
605 SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT,
606};
607
608#define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001
609#define SNDRV_RAWMIDI_INFO_INPUT 0x00000002
610#define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004
611
612struct snd_rawmidi_info {
613 unsigned int device;
614 unsigned int subdevice;
615 int stream;
616 int card;
617 unsigned int flags;
618 unsigned char id[64];
619 unsigned char name[80];
620 unsigned char subname[32];
621 unsigned int subdevices_count;
622 unsigned int subdevices_avail;
623 unsigned char reserved[64];
624};
625
626struct snd_rawmidi_params {
627 int stream;
628 size_t buffer_size;
629 size_t avail_min;
630 unsigned int no_active_sensing: 1;
631 unsigned char reserved[16];
632};
633
634struct snd_rawmidi_status {
635 int stream;
636 struct timespec tstamp;
637 size_t avail;
638 size_t xruns;
639 unsigned char reserved[16];
640};
641
642#define SNDRV_RAWMIDI_IOCTL_PVERSION _IOR('W', 0x00, int)
643#define SNDRV_RAWMIDI_IOCTL_INFO _IOR('W', 0x01, struct snd_rawmidi_info)
644#define SNDRV_RAWMIDI_IOCTL_PARAMS _IOWR('W', 0x10, struct snd_rawmidi_params)
645#define SNDRV_RAWMIDI_IOCTL_STATUS _IOWR('W', 0x20, struct snd_rawmidi_status)
646#define SNDRV_RAWMIDI_IOCTL_DROP _IOW('W', 0x30, int)
647#define SNDRV_RAWMIDI_IOCTL_DRAIN _IOW('W', 0x31, int)
648
649
650
651
652
653#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 6)
654
655enum {
656 SNDRV_TIMER_CLASS_NONE = -1,
657 SNDRV_TIMER_CLASS_SLAVE = 0,
658 SNDRV_TIMER_CLASS_GLOBAL,
659 SNDRV_TIMER_CLASS_CARD,
660 SNDRV_TIMER_CLASS_PCM,
661 SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM,
662};
663
664
665enum {
666 SNDRV_TIMER_SCLASS_NONE = 0,
667 SNDRV_TIMER_SCLASS_APPLICATION,
668 SNDRV_TIMER_SCLASS_SEQUENCER,
669 SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
670 SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
671};
672
673
674#define SNDRV_TIMER_GLOBAL_SYSTEM 0
675#define SNDRV_TIMER_GLOBAL_RTC 1
676#define SNDRV_TIMER_GLOBAL_HPET 2
677#define SNDRV_TIMER_GLOBAL_HRTIMER 3
678
679
680#define SNDRV_TIMER_FLG_SLAVE (1<<0)
681
682struct snd_timer_id {
683 int dev_class;
684 int dev_sclass;
685 int card;
686 int device;
687 int subdevice;
688};
689
690struct snd_timer_ginfo {
691 struct snd_timer_id tid;
692 unsigned int flags;
693 int card;
694 unsigned char id[64];
695 unsigned char name[80];
696 unsigned long reserved0;
697 unsigned long resolution;
698 unsigned long resolution_min;
699 unsigned long resolution_max;
700 unsigned int clients;
701 unsigned char reserved[32];
702};
703
704struct snd_timer_gparams {
705 struct snd_timer_id tid;
706 unsigned long period_num;
707 unsigned long period_den;
708 unsigned char reserved[32];
709};
710
711struct snd_timer_gstatus {
712 struct snd_timer_id tid;
713 unsigned long resolution;
714 unsigned long resolution_num;
715 unsigned long resolution_den;
716 unsigned char reserved[32];
717};
718
719struct snd_timer_select {
720 struct snd_timer_id id;
721 unsigned char reserved[32];
722};
723
724struct snd_timer_info {
725 unsigned int flags;
726 int card;
727 unsigned char id[64];
728 unsigned char name[80];
729 unsigned long reserved0;
730 unsigned long resolution;
731 unsigned char reserved[64];
732};
733
734#define SNDRV_TIMER_PSFLG_AUTO (1<<0)
735#define SNDRV_TIMER_PSFLG_EXCLUSIVE (1<<1)
736#define SNDRV_TIMER_PSFLG_EARLY_EVENT (1<<2)
737
738struct snd_timer_params {
739 unsigned int flags;
740 unsigned int ticks;
741 unsigned int queue_size;
742 unsigned int reserved0;
743 unsigned int filter;
744 unsigned char reserved[60];
745};
746
747struct snd_timer_status {
748 struct timespec tstamp;
749 unsigned int resolution;
750 unsigned int lost;
751 unsigned int overrun;
752 unsigned int queue;
753 unsigned char reserved[64];
754};
755
756#define SNDRV_TIMER_IOCTL_PVERSION _IOR('T', 0x00, int)
757#define SNDRV_TIMER_IOCTL_NEXT_DEVICE _IOWR('T', 0x01, struct snd_timer_id)
758#define SNDRV_TIMER_IOCTL_TREAD _IOW('T', 0x02, int)
759#define SNDRV_TIMER_IOCTL_GINFO _IOWR('T', 0x03, struct snd_timer_ginfo)
760#define SNDRV_TIMER_IOCTL_GPARAMS _IOW('T', 0x04, struct snd_timer_gparams)
761#define SNDRV_TIMER_IOCTL_GSTATUS _IOWR('T', 0x05, struct snd_timer_gstatus)
762#define SNDRV_TIMER_IOCTL_SELECT _IOW('T', 0x10, struct snd_timer_select)
763#define SNDRV_TIMER_IOCTL_INFO _IOR('T', 0x11, struct snd_timer_info)
764#define SNDRV_TIMER_IOCTL_PARAMS _IOW('T', 0x12, struct snd_timer_params)
765#define SNDRV_TIMER_IOCTL_STATUS _IOR('T', 0x14, struct snd_timer_status)
766
767#define SNDRV_TIMER_IOCTL_START _IO('T', 0xa0)
768#define SNDRV_TIMER_IOCTL_STOP _IO('T', 0xa1)
769#define SNDRV_TIMER_IOCTL_CONTINUE _IO('T', 0xa2)
770#define SNDRV_TIMER_IOCTL_PAUSE _IO('T', 0xa3)
771
772struct snd_timer_read {
773 unsigned int resolution;
774 unsigned int ticks;
775};
776
777enum {
778 SNDRV_TIMER_EVENT_RESOLUTION = 0,
779 SNDRV_TIMER_EVENT_TICK,
780 SNDRV_TIMER_EVENT_START,
781 SNDRV_TIMER_EVENT_STOP,
782 SNDRV_TIMER_EVENT_CONTINUE,
783 SNDRV_TIMER_EVENT_PAUSE,
784 SNDRV_TIMER_EVENT_EARLY,
785 SNDRV_TIMER_EVENT_SUSPEND,
786 SNDRV_TIMER_EVENT_RESUME,
787
788 SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10,
789 SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10,
790 SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10,
791 SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10,
792 SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10,
793 SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10,
794};
795
796struct snd_timer_tread {
797 int event;
798 struct timespec tstamp;
799 unsigned int val;
800};
801
802
803
804
805
806
807
808#define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7)
809
810struct snd_ctl_card_info {
811 int card;
812 int pad;
813 unsigned char id[16];
814 unsigned char driver[16];
815 unsigned char name[32];
816 unsigned char longname[80];
817 unsigned char reserved_[16];
818 unsigned char mixername[80];
819 unsigned char components[128];
820};
821
822typedef int __bitwise snd_ctl_elem_type_t;
823#define SNDRV_CTL_ELEM_TYPE_NONE ((__force snd_ctl_elem_type_t) 0)
824#define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((__force snd_ctl_elem_type_t) 1)
825#define SNDRV_CTL_ELEM_TYPE_INTEGER ((__force snd_ctl_elem_type_t) 2)
826#define SNDRV_CTL_ELEM_TYPE_ENUMERATED ((__force snd_ctl_elem_type_t) 3)
827#define SNDRV_CTL_ELEM_TYPE_BYTES ((__force snd_ctl_elem_type_t) 4)
828#define SNDRV_CTL_ELEM_TYPE_IEC958 ((__force snd_ctl_elem_type_t) 5)
829#define SNDRV_CTL_ELEM_TYPE_INTEGER64 ((__force snd_ctl_elem_type_t) 6)
830#define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64
831
832typedef int __bitwise snd_ctl_elem_iface_t;
833#define SNDRV_CTL_ELEM_IFACE_CARD ((__force snd_ctl_elem_iface_t) 0)
834#define SNDRV_CTL_ELEM_IFACE_HWDEP ((__force snd_ctl_elem_iface_t) 1)
835#define SNDRV_CTL_ELEM_IFACE_MIXER ((__force snd_ctl_elem_iface_t) 2)
836#define SNDRV_CTL_ELEM_IFACE_PCM ((__force snd_ctl_elem_iface_t) 3)
837#define SNDRV_CTL_ELEM_IFACE_RAWMIDI ((__force snd_ctl_elem_iface_t) 4)
838#define SNDRV_CTL_ELEM_IFACE_TIMER ((__force snd_ctl_elem_iface_t) 5)
839#define SNDRV_CTL_ELEM_IFACE_SEQUENCER ((__force snd_ctl_elem_iface_t) 6)
840#define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER
841
842#define SNDRV_CTL_ELEM_ACCESS_READ (1<<0)
843#define SNDRV_CTL_ELEM_ACCESS_WRITE (1<<1)
844#define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE)
845#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2)
846#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1<<3)
847#define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1<<4)
848#define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1<<5)
849#define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ|SNDRV_CTL_ELEM_ACCESS_TLV_WRITE)
850#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1<<6)
851#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1<<8)
852#define SNDRV_CTL_ELEM_ACCESS_LOCK (1<<9)
853#define SNDRV_CTL_ELEM_ACCESS_OWNER (1<<10)
854#define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1<<28)
855#define SNDRV_CTL_ELEM_ACCESS_USER (1<<29)
856
857
858
859#define SNDRV_CTL_POWER_D0 0x0000
860#define SNDRV_CTL_POWER_D1 0x0100
861#define SNDRV_CTL_POWER_D2 0x0200
862#define SNDRV_CTL_POWER_D3 0x0300
863#define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3|0x0000)
864#define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3|0x0001)
865
866#define SNDRV_CTL_ELEM_ID_NAME_MAXLEN 44
867
868struct snd_ctl_elem_id {
869 unsigned int numid;
870 snd_ctl_elem_iface_t iface;
871 unsigned int device;
872 unsigned int subdevice;
873 unsigned char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
874 unsigned int index;
875};
876
877struct snd_ctl_elem_list {
878 unsigned int offset;
879 unsigned int space;
880 unsigned int used;
881 unsigned int count;
882 struct snd_ctl_elem_id __user *pids;
883 unsigned char reserved[50];
884};
885
886struct snd_ctl_elem_info {
887 struct snd_ctl_elem_id id;
888 snd_ctl_elem_type_t type;
889 unsigned int access;
890 unsigned int count;
891 __kernel_pid_t owner;
892 union {
893 struct {
894 long min;
895 long max;
896 long step;
897 } integer;
898 struct {
899 long long min;
900 long long max;
901 long long step;
902 } integer64;
903 struct {
904 unsigned int items;
905 unsigned int item;
906 char name[64];
907 __u64 names_ptr;
908 unsigned int names_length;
909 } enumerated;
910 unsigned char reserved[128];
911 } value;
912 union {
913 unsigned short d[4];
914 unsigned short *d_ptr;
915 } dimen;
916 unsigned char reserved[64-4*sizeof(unsigned short)];
917};
918
919struct snd_ctl_elem_value {
920 struct snd_ctl_elem_id id;
921 unsigned int indirect: 1;
922 union {
923 union {
924 long value[128];
925 long *value_ptr;
926 } integer;
927 union {
928 long long value[64];
929 long long *value_ptr;
930 } integer64;
931 union {
932 unsigned int item[128];
933 unsigned int *item_ptr;
934 } enumerated;
935 union {
936 unsigned char data[512];
937 unsigned char *data_ptr;
938 } bytes;
939 struct snd_aes_iec958 iec958;
940 } value;
941 struct timespec tstamp;
942 unsigned char reserved[128-sizeof(struct timespec)];
943};
944
945struct snd_ctl_tlv {
946 unsigned int numid;
947 unsigned int length;
948 unsigned int tlv[0];
949};
950
951#define SNDRV_CTL_IOCTL_PVERSION _IOR('U', 0x00, int)
952#define SNDRV_CTL_IOCTL_CARD_INFO _IOR('U', 0x01, struct snd_ctl_card_info)
953#define SNDRV_CTL_IOCTL_ELEM_LIST _IOWR('U', 0x10, struct snd_ctl_elem_list)
954#define SNDRV_CTL_IOCTL_ELEM_INFO _IOWR('U', 0x11, struct snd_ctl_elem_info)
955#define SNDRV_CTL_IOCTL_ELEM_READ _IOWR('U', 0x12, struct snd_ctl_elem_value)
956#define SNDRV_CTL_IOCTL_ELEM_WRITE _IOWR('U', 0x13, struct snd_ctl_elem_value)
957#define SNDRV_CTL_IOCTL_ELEM_LOCK _IOW('U', 0x14, struct snd_ctl_elem_id)
958#define SNDRV_CTL_IOCTL_ELEM_UNLOCK _IOW('U', 0x15, struct snd_ctl_elem_id)
959#define SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS _IOWR('U', 0x16, int)
960#define SNDRV_CTL_IOCTL_ELEM_ADD _IOWR('U', 0x17, struct snd_ctl_elem_info)
961#define SNDRV_CTL_IOCTL_ELEM_REPLACE _IOWR('U', 0x18, struct snd_ctl_elem_info)
962#define SNDRV_CTL_IOCTL_ELEM_REMOVE _IOWR('U', 0x19, struct snd_ctl_elem_id)
963#define SNDRV_CTL_IOCTL_TLV_READ _IOWR('U', 0x1a, struct snd_ctl_tlv)
964#define SNDRV_CTL_IOCTL_TLV_WRITE _IOWR('U', 0x1b, struct snd_ctl_tlv)
965#define SNDRV_CTL_IOCTL_TLV_COMMAND _IOWR('U', 0x1c, struct snd_ctl_tlv)
966#define SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE _IOWR('U', 0x20, int)
967#define SNDRV_CTL_IOCTL_HWDEP_INFO _IOR('U', 0x21, struct snd_hwdep_info)
968#define SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE _IOR('U', 0x30, int)
969#define SNDRV_CTL_IOCTL_PCM_INFO _IOWR('U', 0x31, struct snd_pcm_info)
970#define SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE _IOW('U', 0x32, int)
971#define SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE _IOWR('U', 0x40, int)
972#define SNDRV_CTL_IOCTL_RAWMIDI_INFO _IOWR('U', 0x41, struct snd_rawmidi_info)
973#define SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE _IOW('U', 0x42, int)
974#define SNDRV_CTL_IOCTL_POWER _IOWR('U', 0xd0, int)
975#define SNDRV_CTL_IOCTL_POWER_STATE _IOR('U', 0xd1, int)
976
977
978
979
980
981enum sndrv_ctl_event_type {
982 SNDRV_CTL_EVENT_ELEM = 0,
983 SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM,
984};
985
986#define SNDRV_CTL_EVENT_MASK_VALUE (1<<0)
987#define SNDRV_CTL_EVENT_MASK_INFO (1<<1)
988#define SNDRV_CTL_EVENT_MASK_ADD (1<<2)
989#define SNDRV_CTL_EVENT_MASK_TLV (1<<3)
990#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U)
991
992struct snd_ctl_event {
993 int type;
994 union {
995 struct {
996 unsigned int mask;
997 struct snd_ctl_elem_id id;
998 } elem;
999 unsigned char data8[60];
1000 } data;
1001};
1002
1003
1004
1005
1006
1007#define SNDRV_CTL_NAME_NONE ""
1008#define SNDRV_CTL_NAME_PLAYBACK "Playback "
1009#define SNDRV_CTL_NAME_CAPTURE "Capture "
1010
1011#define SNDRV_CTL_NAME_IEC958_NONE ""
1012#define SNDRV_CTL_NAME_IEC958_SWITCH "Switch"
1013#define SNDRV_CTL_NAME_IEC958_VOLUME "Volume"
1014#define SNDRV_CTL_NAME_IEC958_DEFAULT "Default"
1015#define SNDRV_CTL_NAME_IEC958_MASK "Mask"
1016#define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask"
1017#define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask"
1018#define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream"
1019#define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_##direction SNDRV_CTL_NAME_IEC958_##what
1020
1021#endif
1022