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11#ifndef __ASM_MCIP_H
12#define __ASM_MCIP_H
13
14#ifdef CONFIG_ISA_ARCV2
15
16#include <asm/arcregs.h>
17
18#define ARC_REG_MCIP_BCR 0x0d0
19#define ARC_REG_MCIP_CMD 0x600
20#define ARC_REG_MCIP_WDATA 0x601
21#define ARC_REG_MCIP_READBACK 0x602
22
23struct mcip_cmd {
24#ifdef CONFIG_CPU_BIG_ENDIAN
25 unsigned int pad:8, param:16, cmd:8;
26#else
27 unsigned int cmd:8, param:16, pad:8;
28#endif
29
30#define CMD_INTRPT_GENERATE_IRQ 0x01
31#define CMD_INTRPT_GENERATE_ACK 0x02
32#define CMD_INTRPT_READ_STATUS 0x03
33#define CMD_INTRPT_CHECK_SOURCE 0x04
34
35
36#define CMD_SEMA_CLAIM_AND_READ 0x11
37#define CMD_SEMA_RELEASE 0x12
38
39#define CMD_DEBUG_SET_MASK 0x34
40#define CMD_DEBUG_SET_SELECT 0x36
41
42#define CMD_GFRC_READ_LO 0x42
43#define CMD_GFRC_READ_HI 0x43
44
45#define CMD_IDU_ENABLE 0x71
46#define CMD_IDU_DISABLE 0x72
47#define CMD_IDU_SET_MODE 0x74
48#define CMD_IDU_SET_DEST 0x76
49#define CMD_IDU_SET_MASK 0x7C
50
51#define IDU_M_TRIG_LEVEL 0x0
52#define IDU_M_TRIG_EDGE 0x1
53
54#define IDU_M_DISTRI_RR 0x0
55#define IDU_M_DISTRI_DEST 0x2
56};
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65
66static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
67{
68 struct mcip_cmd buf;
69
70 buf.pad = 0;
71 buf.cmd = cmd;
72 buf.param = param;
73
74 WRITE_AUX(ARC_REG_MCIP_CMD, buf);
75}
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80
81static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
82 unsigned int data)
83{
84 write_aux_reg(ARC_REG_MCIP_WDATA, data);
85
86 __mcip_cmd(cmd, param);
87}
88
89#endif
90
91#endif
92