1#ifndef __ASM_ARM_SWITCH_TO_H 2#define __ASM_ARM_SWITCH_TO_H 3 4#include <linux/thread_info.h> 5 6/* 7 * For v7 SMP cores running a preemptible kernel we may be pre-empted 8 * during a TLB maintenance operation, so execute an inner-shareable dsb 9 * to ensure that the maintenance completes in case we migrate to another 10 * CPU. 11 */ 12#if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7) 13#define __complete_pending_tlbi() dsb(ish) 14#else 15#define __complete_pending_tlbi() 16#endif 17 18/* 19 * switch_to(prev, next) should switch from task `prev' to `next' 20 * `prev' will never be the same as `next'. schedule() itself 21 * contains the memory barrier to tell GCC not to cache `current'. 22 */ 23extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *); 24 25#define switch_to(prev,next,last) \ 26do { \ 27 __complete_pending_tlbi(); \ 28 last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \ 29} while (0) 30 31#endif /* __ASM_ARM_SWITCH_TO_H */ 32