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26#include <linux/linkage.h>
27#include <linux/init.h>
28#include <asm/assembler.h>
29#include <asm/asm-offsets.h>
30#include <asm/hwcap.h>
31#include <asm/pgtable-hwdef.h>
32#include <asm/pgtable.h>
33#include <asm/ptrace.h>
34
35#include "proc-macros.S"
36
37
38
39
40
41
42
43
44
45#define MAX_AREA_SIZE 32768
46
47
48
49
50#define CACHE_DLINESIZE 32
51
52
53
54
55#define CACHE_DSEGMENTS 16
56
57
58
59
60#define CACHE_DENTRIES 64
61
62
63
64
65
66
67#define CACHE_DLIMIT 32768
68
69 .text
70
71
72
73ENTRY(cpu_arm1020e_proc_init)
74 ret lr
75
76
77
78
79ENTRY(cpu_arm1020e_proc_fin)
80 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 bic r0, r0,
82 bic r0, r0,
83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
84 ret lr
85
86
87
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90
91
92
93
94
95 .align 5
96 .pushsection .idmap.text, "ax"
97ENTRY(cpu_arm1020e_reset)
98 mov ip,
99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
100 mcr p15, 0, ip, c7, c10, 4 @ drain WB
101#ifdef CONFIG_MMU
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103#endif
104 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
105 bic ip, ip,
106 bic ip, ip,
107 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
108 ret r0
109ENDPROC(cpu_arm1020e_reset)
110 .popsection
111
112
113
114
115 .align 5
116ENTRY(cpu_arm1020e_do_idle)
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 ret lr
119
120
121
122 .align 5
123
124
125
126
127
128
129ENTRY(arm1020e_flush_icache_all)
130#ifndef CONFIG_CPU_ICACHE_DISABLE
131 mov r0,
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
133#endif
134 ret lr
135ENDPROC(arm1020e_flush_icache_all)
136
137
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139
140
141
142
143ENTRY(arm1020e_flush_user_cache_all)
144
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147
148
149
150ENTRY(arm1020e_flush_kern_cache_all)
151 mov r2,
152 mov ip,
153__flush_whole_cache:
154#ifndef CONFIG_CPU_DCACHE_DISABLE
155 mcr p15, 0, ip, c7, c10, 4 @ drain WB
156 mov r1,
1571: orr r3, r1,
1582: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
159 subs r3, r3,
160 bcs 2b @ entries 63 to 0
161 subs r1, r1,
162 bcs 1b @ segments 15 to 0
163#endif
164 tst r2,
165#ifndef CONFIG_CPU_ICACHE_DISABLE
166 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
167#endif
168 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
169 ret lr
170
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179
180
181ENTRY(arm1020e_flush_user_cache_range)
182 mov ip,
183 sub r3, r1, r0 @ calculate total size
184 cmp r3,
185 bhs __flush_whole_cache
186
187#ifndef CONFIG_CPU_DCACHE_DISABLE
1881: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
189 add r0, r0,
190 cmp r0, r1
191 blo 1b
192#endif
193 tst r2,
194#ifndef CONFIG_CPU_ICACHE_DISABLE
195 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
196#endif
197 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
198 ret lr
199
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209
210ENTRY(arm1020e_coherent_kern_range)
211
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221
222ENTRY(arm1020e_coherent_user_range)
223 mov ip,
224 bic r0, r0,
2251:
226#ifndef CONFIG_CPU_DCACHE_DISABLE
227 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
228#endif
229#ifndef CONFIG_CPU_ICACHE_DISABLE
230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
231#endif
232 add r0, r0,
233 cmp r0, r1
234 blo 1b
235 mcr p15, 0, ip, c7, c10, 4 @ drain WB
236 mov r0,
237 ret lr
238
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245
246
247
248ENTRY(arm1020e_flush_kern_dcache_area)
249 mov ip,
250#ifndef CONFIG_CPU_DCACHE_DISABLE
251 add r1, r0, r1
2521: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
253 add r0, r0,
254 cmp r0, r1
255 blo 1b
256#endif
257 mcr p15, 0, ip, c7, c10, 4 @ drain WB
258 ret lr
259
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272
273arm1020e_dma_inv_range:
274 mov ip,
275#ifndef CONFIG_CPU_DCACHE_DISABLE
276 tst r0,
277 bic r0, r0,
278 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
279 tst r1,
280 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
2811: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
282 add r0, r0,
283 cmp r0, r1
284 blo 1b
285#endif
286 mcr p15, 0, ip, c7, c10, 4 @ drain WB
287 ret lr
288
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296
297
298
299arm1020e_dma_clean_range:
300 mov ip,
301#ifndef CONFIG_CPU_DCACHE_DISABLE
302 bic r0, r0,
3031: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
304 add r0, r0,
305 cmp r0, r1
306 blo 1b
307#endif
308 mcr p15, 0, ip, c7, c10, 4 @ drain WB
309 ret lr
310
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316
317
318
319ENTRY(arm1020e_dma_flush_range)
320 mov ip,
321#ifndef CONFIG_CPU_DCACHE_DISABLE
322 bic r0, r0,
3231: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
324 add r0, r0,
325 cmp r0, r1
326 blo 1b
327#endif
328 mcr p15, 0, ip, c7, c10, 4 @ drain WB
329 ret lr
330
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335
336
337ENTRY(arm1020e_dma_map_area)
338 add r1, r1, r0
339 cmp r2,
340 beq arm1020e_dma_clean_range
341 bcs arm1020e_dma_inv_range
342 b arm1020e_dma_flush_range
343ENDPROC(arm1020e_dma_map_area)
344
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347
348
349
350
351ENTRY(arm1020e_dma_unmap_area)
352 ret lr
353ENDPROC(arm1020e_dma_unmap_area)
354
355 .globl arm1020e_flush_kern_cache_louis
356 .equ arm1020e_flush_kern_cache_louis, arm1020e_flush_kern_cache_all
357
358 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
359 define_cache_functions arm1020e
360
361 .align 5
362ENTRY(cpu_arm1020e_dcache_clean_area)
363#ifndef CONFIG_CPU_DCACHE_DISABLE
364 mov ip,
3651: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
366 add r0, r0,
367 subs r1, r1,
368 bhi 1b
369#endif
370 ret lr
371
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379
380
381 .align 5
382ENTRY(cpu_arm1020e_switch_mm)
383#ifdef CONFIG_MMU
384#ifndef CONFIG_CPU_DCACHE_DISABLE
385 mcr p15, 0, r3, c7, c10, 4
386 mov r1,
3871: mov r3,
3882: mov ip, r3, LSL
389 orr ip, ip, r1, LSL
390 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
391 mov ip,
392 subs r3, r3,
393 cmp r3,
394 bge 2b @ entries 3F to 0
395 subs r1, r1,
396 cmp r1,
397 bge 1b @ segments 15 to 0
398
399#endif
400 mov r1,
401#ifndef CONFIG_CPU_ICACHE_DISABLE
402 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
403#endif
404 mcr p15, 0, r1, c7, c10, 4 @ drain WB
405 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
406 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
407#endif
408 ret lr
409
410
411
412
413
414
415 .align 5
416ENTRY(cpu_arm1020e_set_pte_ext)
417#ifdef CONFIG_MMU
418 armv3_set_pte_ext
419 mov r0, r0
420#ifndef CONFIG_CPU_DCACHE_DISABLE
421 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
422#endif
423#endif
424 ret lr
425
426 .type __arm1020e_setup,
427__arm1020e_setup:
428 mov r0,
429 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
430 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
431#ifdef CONFIG_MMU
432 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
433#endif
434 adr r5, arm1020e_crval
435 ldmia r5, {r5, r6}
436 mrc p15, 0, r0, c1, c0 @ get control register v4
437 bic r0, r0, r5
438 orr r0, r0, r6
439#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
440 orr r0, r0,
441#endif
442 ret lr
443 .size __arm1020e_setup, . - __arm1020e_setup
444
445
446
447
448
449
450 .type arm1020e_crval,
451arm1020e_crval:
452 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
453
454 __INITDATA
455 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
456 define_processor_functions arm1020e, dabort=v4t_early_abort, pabort=legacy_pabort
457
458 .section ".rodata"
459
460 string cpu_arch_name, "armv5te"
461 string cpu_elf_name, "v5"
462 string cpu_arm1020e_name, "ARM1020E"
463
464 .align
465
466 .section ".proc.info.init",
467
468 .type __arm1020e_proc_info,
469__arm1020e_proc_info:
470 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
471 .long 0xff0ffff0
472 .long PMD_TYPE_SECT | \
473 PMD_BIT4 | \
474 PMD_SECT_AP_WRITE | \
475 PMD_SECT_AP_READ
476 .long PMD_TYPE_SECT | \
477 PMD_BIT4 | \
478 PMD_SECT_AP_WRITE | \
479 PMD_SECT_AP_READ
480 initfn __arm1020e_setup, __arm1020e_proc_info
481 .long cpu_arch_name
482 .long cpu_elf_name
483 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
484 .long cpu_arm1020e_name
485 .long arm1020e_processor_functions
486 .long v4wbi_tlb_fns
487 .long v4wb_user_fns
488 .long arm1020e_cache_fns
489 .size __arm1020e_proc_info, . - __arm1020e_proc_info
490