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17#include <linux/linkage.h>
18#include <linux/init.h>
19#include <asm/assembler.h>
20#include <asm/asm-offsets.h>
21#include <asm/hwcap.h>
22#include <asm/pgtable-hwdef.h>
23#include <asm/pgtable.h>
24#include <asm/ptrace.h>
25
26#include "proc-macros.S"
27
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34
35
36#define MAX_AREA_SIZE 32768
37
38
39
40
41#define CACHE_DLINESIZE 32
42
43
44
45
46#define CACHE_DSEGMENTS 16
47
48
49
50
51#define CACHE_DENTRIES 64
52
53
54
55
56
57
58#define CACHE_DLIMIT 32768
59
60 .text
61
62
63
64ENTRY(cpu_arm1022_proc_init)
65 ret lr
66
67
68
69
70ENTRY(cpu_arm1022_proc_fin)
71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
72 bic r0, r0,
73 bic r0, r0,
74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
75 ret lr
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84
85
86 .align 5
87 .pushsection .idmap.text, "ax"
88ENTRY(cpu_arm1022_reset)
89 mov ip,
90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c7, c10, 4 @ drain WB
92#ifdef CONFIG_MMU
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
94#endif
95 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
96 bic ip, ip,
97 bic ip, ip,
98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
99 ret r0
100ENDPROC(cpu_arm1022_reset)
101 .popsection
102
103
104
105
106 .align 5
107ENTRY(cpu_arm1022_do_idle)
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
109 ret lr
110
111
112
113 .align 5
114
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118
119
120ENTRY(arm1022_flush_icache_all)
121#ifndef CONFIG_CPU_ICACHE_DISABLE
122 mov r0,
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
124#endif
125 ret lr
126ENDPROC(arm1022_flush_icache_all)
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133
134ENTRY(arm1022_flush_user_cache_all)
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141ENTRY(arm1022_flush_kern_cache_all)
142 mov r2,
143 mov ip,
144__flush_whole_cache:
145#ifndef CONFIG_CPU_DCACHE_DISABLE
146 mov r1,
1471: orr r3, r1,
1482: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
149 subs r3, r3,
150 bcs 2b @ entries 63 to 0
151 subs r1, r1,
152 bcs 1b @ segments 15 to 0
153#endif
154 tst r2,
155#ifndef CONFIG_CPU_ICACHE_DISABLE
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
157#endif
158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
159 ret lr
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170
171ENTRY(arm1022_flush_user_cache_range)
172 mov ip,
173 sub r3, r1, r0 @ calculate total size
174 cmp r3,
175 bhs __flush_whole_cache
176
177#ifndef CONFIG_CPU_DCACHE_DISABLE
1781: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
179 add r0, r0,
180 cmp r0, r1
181 blo 1b
182#endif
183 tst r2,
184#ifndef CONFIG_CPU_ICACHE_DISABLE
185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
186#endif
187 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
188 ret lr
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200ENTRY(arm1022_coherent_kern_range)
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213ENTRY(arm1022_coherent_user_range)
214 mov ip,
215 bic r0, r0,
2161:
217#ifndef CONFIG_CPU_DCACHE_DISABLE
218 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
219#endif
220#ifndef CONFIG_CPU_ICACHE_DISABLE
221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
222#endif
223 add r0, r0,
224 cmp r0, r1
225 blo 1b
226 mcr p15, 0, ip, c7, c10, 4 @ drain WB
227 mov r0,
228 ret lr
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239ENTRY(arm1022_flush_kern_dcache_area)
240 mov ip,
241#ifndef CONFIG_CPU_DCACHE_DISABLE
242 add r1, r0, r1
2431: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
244 add r0, r0,
245 cmp r0, r1
246 blo 1b
247#endif
248 mcr p15, 0, ip, c7, c10, 4 @ drain WB
249 ret lr
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264arm1022_dma_inv_range:
265 mov ip,
266#ifndef CONFIG_CPU_DCACHE_DISABLE
267 tst r0,
268 bic r0, r0,
269 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
270 tst r1,
271 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
2721: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
273 add r0, r0,
274 cmp r0, r1
275 blo 1b
276#endif
277 mcr p15, 0, ip, c7, c10, 4 @ drain WB
278 ret lr
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290arm1022_dma_clean_range:
291 mov ip,
292#ifndef CONFIG_CPU_DCACHE_DISABLE
293 bic r0, r0,
2941: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
295 add r0, r0,
296 cmp r0, r1
297 blo 1b
298#endif
299 mcr p15, 0, ip, c7, c10, 4 @ drain WB
300 ret lr
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310ENTRY(arm1022_dma_flush_range)
311 mov ip,
312#ifndef CONFIG_CPU_DCACHE_DISABLE
313 bic r0, r0,
3141: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
315 add r0, r0,
316 cmp r0, r1
317 blo 1b
318#endif
319 mcr p15, 0, ip, c7, c10, 4 @ drain WB
320 ret lr
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327
328ENTRY(arm1022_dma_map_area)
329 add r1, r1, r0
330 cmp r2,
331 beq arm1022_dma_clean_range
332 bcs arm1022_dma_inv_range
333 b arm1022_dma_flush_range
334ENDPROC(arm1022_dma_map_area)
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342ENTRY(arm1022_dma_unmap_area)
343 ret lr
344ENDPROC(arm1022_dma_unmap_area)
345
346 .globl arm1022_flush_kern_cache_louis
347 .equ arm1022_flush_kern_cache_louis, arm1022_flush_kern_cache_all
348
349 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
350 define_cache_functions arm1022
351
352 .align 5
353ENTRY(cpu_arm1022_dcache_clean_area)
354#ifndef CONFIG_CPU_DCACHE_DISABLE
355 mov ip,
3561: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
357 add r0, r0,
358 subs r1, r1,
359 bhi 1b
360#endif
361 ret lr
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371
372 .align 5
373ENTRY(cpu_arm1022_switch_mm)
374#ifdef CONFIG_MMU
375#ifndef CONFIG_CPU_DCACHE_DISABLE
376 mov r1,
3771: orr r3, r1,
3782: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
379 subs r3, r3,
380 bcs 2b @ entries 63 to 0
381 subs r1, r1,
382 bcs 1b @ segments 15 to 0
383#endif
384 mov r1,
385#ifndef CONFIG_CPU_ICACHE_DISABLE
386 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
387#endif
388 mcr p15, 0, r1, c7, c10, 4 @ drain WB
389 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
390 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
391#endif
392 ret lr
393
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397
398
399 .align 5
400ENTRY(cpu_arm1022_set_pte_ext)
401#ifdef CONFIG_MMU
402 armv3_set_pte_ext
403 mov r0, r0
404#ifndef CONFIG_CPU_DCACHE_DISABLE
405 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
406#endif
407#endif
408 ret lr
409
410 .type __arm1022_setup,
411__arm1022_setup:
412 mov r0,
413 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
414 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
415#ifdef CONFIG_MMU
416 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
417#endif
418 adr r5, arm1022_crval
419 ldmia r5, {r5, r6}
420 mrc p15, 0, r0, c1, c0 @ get control register v4
421 bic r0, r0, r5
422 orr r0, r0, r6
423#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
424 orr r0, r0,
425#endif
426 ret lr
427 .size __arm1022_setup, . - __arm1022_setup
428
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431
432
433
434
435 .type arm1022_crval,
436arm1022_crval:
437 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
438
439 __INITDATA
440 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
441 define_processor_functions arm1022, dabort=v4t_early_abort, pabort=legacy_pabort
442
443 .section ".rodata"
444
445 string cpu_arch_name, "armv5te"
446 string cpu_elf_name, "v5"
447 string cpu_arm1022_name, "ARM1022"
448
449 .align
450
451 .section ".proc.info.init",
452
453 .type __arm1022_proc_info,
454__arm1022_proc_info:
455 .long 0x4105a220 @ ARM 1022E (v5TE)
456 .long 0xff0ffff0
457 .long PMD_TYPE_SECT | \
458 PMD_BIT4 | \
459 PMD_SECT_AP_WRITE | \
460 PMD_SECT_AP_READ
461 .long PMD_TYPE_SECT | \
462 PMD_BIT4 | \
463 PMD_SECT_AP_WRITE | \
464 PMD_SECT_AP_READ
465 initfn __arm1022_setup, __arm1022_proc_info
466 .long cpu_arch_name
467 .long cpu_elf_name
468 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
469 .long cpu_arm1022_name
470 .long arm1022_processor_functions
471 .long v4wbi_tlb_fns
472 .long v4wb_user_fns
473 .long arm1022_cache_fns
474 .size __arm1022_proc_info, . - __arm1022_proc_info
475