LXR linux/arch/sparc/kernel/sbus.c

   1/*
   2 * sbus.c: UltraSparc SBUS controller support.
   3 *
   4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
   5 */
   6
   7#include <linux/kernel.h>
   8#include <linux/types.h>
   9#include <linux/mm.h>
  10#include <linux/spinlock.h>
  11#include <linux/slab.h>
  12#include <linux/export.h>
  13#include <linux/init.h>
  14#include <linux/interrupt.h>
  15#include <linux/of.h>
  16#include <linux/of_device.h>
  17
  18#include <asm/page.h>
  19#include <asm/io.h>
  20#include <asm/upa.h>
  21#include <asm/cache.h>
  22#include <asm/dma.h>
  23#include <asm/irq.h>
  24#include <asm/prom.h>
  25#include <asm/oplib.h>
  26#include <asm/starfire.h>
  27
  28#include "iommu_common.h"
  29
  30#define MAP_BASE        ((u32)0xc0000000)
  31
  32/* Offsets from iommu_regs */
  33#define SYSIO_IOMMUREG_BASE     0x2400UL
  34#define IOMMU_CONTROL   (0x2400UL - 0x2400UL)   /* IOMMU control register */
  35#define IOMMU_TSBBASE   (0x2408UL - 0x2400UL)   /* TSB base address register */
  36#define IOMMU_FLUSH     (0x2410UL - 0x2400UL)   /* IOMMU flush register */
  37#define IOMMU_VADIAG    (0x4400UL - 0x2400UL)   /* SBUS virtual address diagnostic */
  38#define IOMMU_TAGCMP    (0x4408UL - 0x2400UL)   /* TLB tag compare diagnostics */
  39#define IOMMU_LRUDIAG   (0x4500UL - 0x2400UL)   /* IOMMU LRU queue diagnostics */
  40#define IOMMU_TAGDIAG   (0x4580UL - 0x2400UL)   /* TLB tag diagnostics */
  41#define IOMMU_DRAMDIAG  (0x4600UL - 0x2400UL)   /* TLB data RAM diagnostics */
  42
  43#define IOMMU_DRAM_VALID        (1UL << 30UL)
  44
  45/* Offsets from strbuf_regs */
  46#define SYSIO_STRBUFREG_BASE    0x2800UL
  47#define STRBUF_CONTROL  (0x2800UL - 0x2800UL)   /* Control */
  48#define STRBUF_PFLUSH   (0x2808UL - 0x2800UL)   /* Page flush/invalidate */
  49#define STRBUF_FSYNC    (0x2810UL - 0x2800UL)   /* Flush synchronization */
  50#define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL)   /* data RAM diagnostic */
  51#define STRBUF_ERRDIAG  (0x5400UL - 0x2800UL)   /* error status diagnostics */
  52#define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL)   /* Page tag diagnostics */
  53#define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL)   /* Line tag diagnostics */
  54
  55#define STRBUF_TAG_VALID        0x02UL
  56
  57/* Enable 64-bit DVMA mode for the given device. */
  58void sbus_set_sbus64(struct device *dev, int bursts)
  59{
  60        struct iommu *iommu = dev->archdata.iommu;
  61        struct platform_device *op = to_platform_device(dev);
  62        const struct linux_prom_registers *regs;
  63        unsigned long cfg_reg;
  64        int slot;
  65        u64 val;
  66
  67        regs = of_get_property(op->dev.of_node, "reg", NULL);
  68        if (!regs) {
  69                printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %s\n",
  70                       op->dev.of_node->full_name);
  71                return;
  72        }
  73        slot = regs->which_io;
  74
  75        cfg_reg = iommu->write_complete_reg;
  76        switch (slot) {
  77        case 0:
  78                cfg_reg += 0x20UL;
  79                break;
  80        case 1:
  81                cfg_reg += 0x28UL;
  82                break;
  83        case 2:
  84                cfg_reg += 0x30UL;
  85                break;
  86        case 3:
  87                cfg_reg += 0x38UL;
  88                break;
  89        case 13:
  90                cfg_reg += 0x40UL;
  91                break;
  92        case 14:
  93                cfg_reg += 0x48UL;
  94                break;
  95        case 15:
  96                cfg_reg += 0x50UL;
  97                break;
  98
  99        default:
 100                return;
 101        }
 102
 103        val = upa_readq(cfg_reg);
 104        if (val & (1UL << 14UL)) {
 105                /* Extended transfer mode already enabled. */
 106                return;
 107        }
 108
 109        val |= (1UL << 14UL);
 110
 111        if (bursts & DMA_BURST8)
 112                val |= (1UL << 1UL);
 113        if (bursts & DMA_BURST16)
 114                val |= (1UL << 2UL);
 115        if (bursts & DMA_BURST32)
 116                val |= (1UL << 3UL);
 117        if (bursts & DMA_BURST64)
 118                val |= (1UL << 4UL);
 119        upa_writeq(val, cfg_reg);
 120}
 121EXPORT_SYMBOL(sbus_set_sbus64);
 122
 123/* INO number to IMAP register offset for SYSIO external IRQ's.
 124 * This should conform to both Sunfire/Wildfire server and Fusion
 125 * desktop designs.
 126 */
 127#define SYSIO_IMAP_SLOT0        0x2c00UL
 128#define SYSIO_IMAP_SLOT1        0x2c08UL
 129#define SYSIO_IMAP_SLOT2        0x2c10UL
 130#define SYSIO_IMAP_SLOT3        0x2c18UL
 131#define SYSIO_IMAP_SCSI         0x3000UL
 132#define SYSIO_IMAP_ETH          0x3008UL
 133#define SYSIO_IMAP_BPP          0x3010UL
 134#define SYSIO_IMAP_AUDIO        0x3018UL
 135#define SYSIO_IMAP_PFAIL        0x3020UL
 136#define SYSIO_IMAP_KMS          0x3028UL
 137#define SYSIO_IMAP_FLPY         0x3030UL
 138#define SYSIO_IMAP_SHW          0x3038UL
 139#define SYSIO_IMAP_KBD          0x3040UL
 140#define SYSIO_IMAP_MS           0x3048UL
 141#define SYSIO_IMAP_SER          0x3050UL
 142#define SYSIO_IMAP_TIM0         0x3060UL
 143#define SYSIO_IMAP_TIM1         0x3068UL
 144#define SYSIO_IMAP_UE           0x3070UL
 145#define SYSIO_IMAP_CE           0x3078UL
 146#define SYSIO_IMAP_SBERR        0x3080UL
 147#define SYSIO_IMAP_PMGMT        0x3088UL
 148#define SYSIO_IMAP_GFX          0x3090UL
 149#define SYSIO_IMAP_EUPA         0x3098UL
 150
 151#define bogon     ((unsigned long) -1)
 152static unsigned long sysio_irq_offsets[] = {
 153        /* SBUS Slot 0 --> 3, level 1 --> 7 */
 154        SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
 155        SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
 156        SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
 157        SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
 158        SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
 159        SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
 160        SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
 161        SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
 162
 163        /* Onboard devices (not relevant/used on SunFire). */
 164        SYSIO_IMAP_SCSI,
 165        SYSIO_IMAP_ETH,
 166        SYSIO_IMAP_BPP,
 167        bogon,
 168        SYSIO_IMAP_AUDIO,
 169        SYSIO_IMAP_PFAIL,
 170        bogon,
 171        bogon,
 172        SYSIO_IMAP_KMS,
 173        SYSIO_IMAP_FLPY,
 174        SYSIO_IMAP_SHW,
 175        SYSIO_IMAP_KBD,
 176        SYSIO_IMAP_MS,
 177        SYSIO_IMAP_SER,
 178        bogon,
 179        bogon,
 180        SYSIO_IMAP_TIM0,
 181        SYSIO_IMAP_TIM1,
 182        bogon,
 183        bogon,
 184        SYSIO_IMAP_UE,
 185        SYSIO_IMAP_CE,
 186        SYSIO_IMAP_SBERR,
 187        SYSIO_IMAP_PMGMT,
 188};
 189
 190#undef bogon
 191
 192#define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
 193
 194/* Convert Interrupt Mapping register pointer to associated
 195 * Interrupt Clear register pointer, SYSIO specific version.
 196 */
 197#define SYSIO_ICLR_UNUSED0      0x3400UL
 198#define SYSIO_ICLR_SLOT0        0x3408UL
 199#define SYSIO_ICLR_SLOT1        0x3448UL
 200#define SYSIO_ICLR_SLOT2        0x3488UL
 201#define SYSIO_ICLR_SLOT3        0x34c8UL
 202static unsigned long sysio_imap_to_iclr(unsigned long imap)
 203{
 204        unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
 205        return imap + diff;
 206}
 207
 208static unsigned int sbus_build_irq(struct platform_device *op, unsigned int ino)
 209{
 210        struct iommu *iommu = op->dev.archdata.iommu;
 211        unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
 212        unsigned long imap, iclr;
 213        int sbus_level = 0;
 214
 215        imap = sysio_irq_offsets[ino];
 216        if (imap == ((unsigned long)-1)) {
 217                prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
 218                            ino);
 219                prom_halt();
 220        }
 221        imap += reg_base;
 222
 223        /* SYSIO inconsistency.  For external SLOTS, we have to select
 224         * the right ICLR register based upon the lower SBUS irq level
 225         * bits.
 226         */
 227        if (ino >= 0x20) {
 228                iclr = sysio_imap_to_iclr(imap);
 229        } else {
 230                int sbus_slot = (ino & 0x18)>>3;
 231                
 232                sbus_level = ino & 0x7;
 233
 234                switch(sbus_slot) {
 235                case 0:
 236                        iclr = reg_base + SYSIO_ICLR_SLOT0;
 237                        break;
 238                case 1:
 239                        iclr = reg_base + SYSIO_ICLR_SLOT1;
 240                        break;
 241                case 2:
 242                        iclr = reg_base + SYSIO_ICLR_SLOT2;
 243                        break;
 244                default:
 245                case 3:
 246                        iclr = reg_base + SYSIO_ICLR_SLOT3;
 247                        break;
 248                }
 249
 250                iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
 251        }
 252        return build_irq(sbus_level, iclr, imap);
 253}
 254
 255/* Error interrupt handling. */
 256#define SYSIO_UE_AFSR   0x0030UL
 257#define SYSIO_UE_AFAR   0x0038UL
 258#define  SYSIO_UEAFSR_PPIO  0x8000000000000000UL /* Primary PIO cause         */
 259#define  SYSIO_UEAFSR_PDRD  0x4000000000000000UL /* Primary DVMA read cause   */
 260#define  SYSIO_UEAFSR_PDWR  0x2000000000000000UL /* Primary DVMA write cause  */
 261#define  SYSIO_UEAFSR_SPIO  0x1000000000000000UL /* Secondary PIO is cause    */
 262#define  SYSIO_UEAFSR_SDRD  0x0800000000000000UL /* Secondary DVMA read cause */
 263#define  SYSIO_UEAFSR_SDWR  0x0400000000000000UL /* Secondary DVMA write cause*/
 264#define  SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved                  */
 265#define  SYSIO_UEAFSR_DOFF  0x0000e00000000000UL /* Doubleword Offset         */
 266#define  SYSIO_UEAFSR_SIZE  0x00001c0000000000UL /* Bad transfer size 2^SIZE  */
 267#define  SYSIO_UEAFSR_MID   0x000003e000000000UL /* UPA MID causing the fault */
 268#define  SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved                  */
 269static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
 270{
 271        struct platform_device *op = dev_id;
 272        struct iommu *iommu = op->dev.archdata.iommu;
 273        unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
 274        unsigned long afsr_reg, afar_reg;
 275        unsigned long afsr, afar, error_bits;
 276        int reported, portid;
 277
 278        afsr_reg = reg_base + SYSIO_UE_AFSR;
 279        afar_reg = reg_base + SYSIO_UE_AFAR;
 280
 281        /* Latch error status. */
 282        afsr = upa_readq(afsr_reg);
 283        afar = upa_readq(afar_reg);
 284
 285        /* Clear primary/secondary error status bits. */
 286        error_bits = afsr &
 287                (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
 288                 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
 289        upa_writeq(error_bits, afsr_reg);
 290
 291        portid = of_getintprop_default(op->dev.of_node, "portid", -1);
 292
 293        /* Log the error. */
 294        printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
 295               portid,
 296               (((error_bits & SYSIO_UEAFSR_PPIO) ?
 297                 "PIO" :
 298                 ((error_bits & SYSIO_UEAFSR_PDRD) ?
 299                  "DVMA Read" :
 300                  ((error_bits & SYSIO_UEAFSR_PDWR) ?
 301                   "DVMA Write" : "???")))));
 302        printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
 303               portid,
 304               (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
 305               (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
 306               (afsr & SYSIO_UEAFSR_MID) >> 37UL);
 307        printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
 308        printk("SYSIO[%x]: Secondary UE errors [", portid);
 309        reported = 0;
 310        if (afsr & SYSIO_UEAFSR_SPIO) {
 311                reported++;
 312                printk("(PIO)");
 313        }
 314        if (afsr & SYSIO_UEAFSR_SDRD) {
 315                reported++;
 316                printk("(DVMA Read)");
 317        }
 318        if (afsr & SYSIO_UEAFSR_SDWR) {
 319                reported++;
 320                printk("(DVMA Write)");
 321        }
 322        if (!reported)
 323                printk("(none)");
 324        printk("]\n");
 325
 326        return IRQ_HANDLED;
 327}
 328
 329#define SYSIO_CE_AFSR   0x0040UL
 330#define SYSIO_CE_AFAR   0x0048UL
 331#define  SYSIO_CEAFSR_PPIO  0x8000000000000000UL /* Primary PIO cause         */
 332#define  SYSIO_CEAFSR_PDRD  0x4000000000000000UL /* Primary DVMA read cause   */
 333#define  SYSIO_CEAFSR_PDWR  0x2000000000000000UL /* Primary DVMA write cause  */
 334#define  SYSIO_CEAFSR_SPIO  0x1000000000000000UL /* Secondary PIO cause       */
 335#define  SYSIO_CEAFSR_SDRD  0x0800000000000000UL /* Secondary DVMA read cause */
 336#define  SYSIO_CEAFSR_SDWR  0x0400000000000000UL /* Secondary DVMA write cause*/
 337#define  SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved                  */
 338#define  SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits             */
 339#define  SYSIO_CEAFSR_DOFF  0x0000e00000000000UL /* Double Offset             */
 340#define  SYSIO_CEAFSR_SIZE  0x00001c0000000000UL /* Bad transfer size 2^SIZE  */
 341#define  SYSIO_CEAFSR_MID   0x000003e000000000UL /* UPA MID causing the fault */
 342#define  SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved                  */
 343static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
 344{
 345        struct platform_device *op = dev_id;
 346        struct iommu *iommu = op->dev.archdata.iommu;
 347        unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
 348        unsigned long afsr_reg, afar_reg;
 349        unsigned long afsr, afar, error_bits;
 350        int reported, portid;
 351
 352        afsr_reg = reg_base + SYSIO_CE_AFSR;
 353        afar_reg = reg_base + SYSIO_CE_AFAR;
 354
 355        /* Latch error status. */
 356        afsr = upa_readq(afsr_reg);
 357        afar = upa_readq(afar_reg);
 358
 359        /* Clear primary/secondary error status bits. */
 360        error_bits = afsr &
 361                (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
 362                 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
 363        upa_writeq(error_bits, afsr_reg);
 364
 365        portid = of_getintprop_default(op->dev.of_node, "portid", -1);
 366
 367        printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
 368               portid,
 369               (((error_bits & SYSIO_CEAFSR_PPIO) ?
 370                 "PIO" :
 371                 ((error_bits & SYSIO_CEAFSR_PDRD) ?
 372                  "DVMA Read" :
 373                  ((error_bits & SYSIO_CEAFSR_PDWR) ?
 374                   "DVMA Write" : "???")))));
 375
 376        /* XXX Use syndrome and afar to print out module string just like
 377         * XXX UDB CE trap handler does... -DaveM
 378         */
 379        printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
 380               portid,
 381               (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
 382               (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
 383               (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
 384               (afsr & SYSIO_CEAFSR_MID) >> 37UL);
 385        printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
 386
 387        printk("SYSIO[%x]: Secondary CE errors [", portid);
 388        reported = 0;
 389        if (afsr & SYSIO_CEAFSR_SPIO) {
 390                reported++;
 391                printk("(PIO)");
 392        }
 393        if (afsr & SYSIO_CEAFSR_SDRD) {
 394                reported++;
 395                printk("(DVMA Read)");
 396        }
 397        if (afsr & SYSIO_CEAFSR_SDWR) {
 398                reported++;
 399                printk("(DVMA Write)");
 400        }
 401        if (!reported)
 402                printk("(none)");
 403        printk("]\n");
 404
 405        return IRQ_HANDLED;
 406}
 407
 408#define SYSIO_SBUS_AFSR         0x2010UL
 409#define SYSIO_SBUS_AFAR         0x2018UL
 410#define  SYSIO_SBAFSR_PLE   0x8000000000000000UL /* Primary Late PIO Error    */
 411#define  SYSIO_SBAFSR_PTO   0x4000000000000000UL /* Primary SBUS Timeout      */
 412#define  SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK    */
 413#define  SYSIO_SBAFSR_SLE   0x1000000000000000UL /* Secondary Late PIO Error  */
 414#define  SYSIO_SBAFSR_STO   0x0800000000000000UL /* Secondary SBUS Timeout    */
 415#define  SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK  */
 416#define  SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved                  */
 417#define  SYSIO_SBAFSR_RD    0x0000800000000000UL /* Primary was late PIO read */
 418#define  SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved                  */
 419#define  SYSIO_SBAFSR_SIZE  0x00001c0000000000UL /* Size of transfer          */
 420#define  SYSIO_SBAFSR_MID   0x000003e000000000UL /* MID causing the error     */
 421#define  SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved                  */
 422static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
 423{
 424        struct platform_device *op = dev_id;
 425        struct iommu *iommu = op->dev.archdata.iommu;
 426        unsigned long afsr_reg, afar_reg, reg_base;
 427        unsigned long afsr, afar, error_bits;
 428        int reported, portid;
 429
 430        reg_base = iommu->write_complete_reg - 0x2000UL;
 431        afsr_reg = reg_base + SYSIO_SBUS_AFSR;
 432        afar_reg = reg_base + SYSIO_SBUS_AFAR;
 433
 434        afsr = upa_readq(afsr_reg);
 435        afar = upa_readq(afar_reg);
 436
 437        /* Clear primary/secondary error status bits. */
 438        error_bits = afsr &
 439                (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
 440                 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
 441        upa_writeq(error_bits, afsr_reg);
 442
 443        portid = of_getintprop_default(op->dev.of_node, "portid", -1);
 444
 445        /* Log the error. */
 446        printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
 447               portid,
 448               (((error_bits & SYSIO_SBAFSR_PLE) ?
 449                 "Late PIO Error" :
 450                 ((error_bits & SYSIO_SBAFSR_PTO) ?
 451                  "Time Out" :
 452                  ((error_bits & SYSIO_SBAFSR_PBERR) ?
 453                   "Error Ack" : "???")))),
 454               (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
 455        printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
 456               portid,
 457               (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
 458               (afsr & SYSIO_SBAFSR_MID) >> 37UL);
 459        printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
 460        printk("SYSIO[%x]: Secondary SBUS errors [", portid);
 461        reported = 0;
 462        if (afsr & SYSIO_SBAFSR_SLE) {
 463                reported++;
 464                printk("(Late PIO Error)");
 465        }
 466        if (afsr & SYSIO_SBAFSR_STO) {
 467                reported++;
 468                printk("(Time Out)");
 469        }
 470        if (afsr & SYSIO_SBAFSR_SBERR) {
 471                reported++;
 472                printk("(Error Ack)");
 473        }
 474        if (!reported)
 475                printk("(none)");
 476        printk("]\n");
 477
 478        /* XXX check iommu/strbuf for further error status XXX */
 479
 480        return IRQ_HANDLED;
 481}
 482
 483#define ECC_CONTROL     0x0020UL
 484#define  SYSIO_ECNTRL_ECCEN     0x8000000000000000UL /* Enable ECC Checking   */
 485#define  SYSIO_ECNTRL_UEEN      0x4000000000000000UL /* Enable UE Interrupts  */
 486#define  SYSIO_ECNTRL_CEEN      0x2000000000000000UL /* Enable CE Interrupts  */
 487
 488#define SYSIO_UE_INO            0x34
 489#define SYSIO_CE_INO            0x35
 490#define SYSIO_SBUSERR_INO       0x36
 491
 492static void __init sysio_register_error_handlers(struct platform_device *op)
 493{
 494        struct iommu *iommu = op->dev.archdata.iommu;
 495        unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
 496        unsigned int irq;
 497        u64 control;
 498        int portid;
 499
 500        portid = of_getintprop_default(op->dev.of_node, "portid", -1);
 501
 502        irq = sbus_build_irq(op, SYSIO_UE_INO);
 503        if (request_irq(irq, sysio_ue_handler, 0,
 504                        "SYSIO_UE", op) < 0) {
 505                prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
 506                            portid);
 507                prom_halt();
 508        }
 509
 510        irq = sbus_build_irq(op, SYSIO_CE_INO);
 511        if (request_irq(irq, sysio_ce_handler, 0,
 512                        "SYSIO_CE", op) < 0) {
 513                prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
 514                            portid);
 515                prom_halt();
 516        }
 517
 518        irq = sbus_build_irq(op, SYSIO_SBUSERR_INO);
 519        if (request_irq(irq, sysio_sbus_error_handler, 0,
 520                        "SYSIO_SBERR", op) < 0) {
 521                prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
 522                            portid);
 523                prom_halt();
 524        }
 525
 526        /* Now turn the error interrupts on and also enable ECC checking. */
 527        upa_writeq((SYSIO_ECNTRL_ECCEN |
 528                    SYSIO_ECNTRL_UEEN  |
 529                    SYSIO_ECNTRL_CEEN),
 530                   reg_base + ECC_CONTROL);
 531
 532        control = upa_readq(iommu->write_complete_reg);
 533        control |= 0x100UL; /* SBUS Error Interrupt Enable */
 534        upa_writeq(control, iommu->write_complete_reg);
 535}
 536
 537/* Boot time initialization. */
 538static void __init sbus_iommu_init(struct platform_device *op)
 539{
 540        const struct linux_prom64_registers *pr;
 541        struct device_node *dp = op->dev.of_node;
 542        struct iommu *iommu;
 543        struct strbuf *strbuf;
 544        unsigned long regs, reg_base;
 545        int i, portid;
 546        u64 control;
 547
 548        pr = of_get_property(dp, "reg", NULL);
 549        if (!pr) {
 550                prom_printf("sbus_iommu_init: Cannot map SYSIO "
 551                            "control registers.\n");
 552                prom_halt();
 553        }
 554        regs = pr->phys_addr;
 555
 556        iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
 557        strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC);
 558        if (!iommu || !strbuf)
 559                goto fatal_memory_error;
 560
 561        op->dev.archdata.iommu = iommu;
 562        op->dev.archdata.stc = strbuf;
 563        op->dev.archdata.numa_node = -1;
 564
 565        reg_base = regs + SYSIO_IOMMUREG_BASE;
 566        iommu->iommu_control = reg_base + IOMMU_CONTROL;
 567        iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE;
 568        iommu->iommu_flush = reg_base + IOMMU_FLUSH;
 569        iommu->iommu_tags = iommu->iommu_control +
 570                (IOMMU_TAGDIAG - IOMMU_CONTROL);
 571
 572        reg_base = regs + SYSIO_STRBUFREG_BASE;
 573        strbuf->strbuf_control = reg_base + STRBUF_CONTROL;
 574        strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH;
 575        strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC;
 576
 577        strbuf->strbuf_enabled = 1;
 578
 579        strbuf->strbuf_flushflag = (volatile unsigned long *)
 580                ((((unsigned long)&strbuf->__flushflag_buf[0])
 581                  + 63UL)
 582                 & ~63UL);
 583        strbuf->strbuf_flushflag_pa = (unsigned long)
 584                __pa(strbuf->strbuf_flushflag);
 585
 586        /* The SYSIO SBUS control register is used for dummy reads
 587         * in order to ensure write completion.
 588         */
 589        iommu->write_complete_reg = regs + 0x2000UL;
 590
 591        portid = of_getintprop_default(op->dev.of_node, "portid", -1);
 592        printk(KERN_INFO "SYSIO: UPA portID %x, at %016lx\n",
 593               portid, regs);
 594
 595        /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
 596        if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1))
 597                goto fatal_memory_error;
 598
 599        control = upa_readq(iommu->iommu_control);
 600        control = ((7UL << 16UL)        |
 601                   (0UL << 2UL)         |
 602                   (1UL << 1UL)         |
 603                   (1UL << 0UL));
 604        upa_writeq(control, iommu->iommu_control);
 605
 606        /* Clean out any cruft in the IOMMU using
 607         * diagnostic accesses.
 608         */
 609        for (i = 0; i < 16; i++) {
 610                unsigned long dram, tag;
 611
 612                dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL);
 613                tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL);
 614
 615                dram += (unsigned long)i * 8UL;
 616                tag += (unsigned long)i * 8UL;
 617                upa_writeq(0, dram);
 618                upa_writeq(0, tag);
 619        }
 620        upa_readq(iommu->write_complete_reg);
 621
 622        /* Give the TSB to SYSIO. */
 623        upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
 624
 625        /* Setup streaming buffer, DE=1 SB_EN=1 */
 626        control = (1UL << 1UL) | (1UL << 0UL);
 627        upa_writeq(control, strbuf->strbuf_control);
 628
 629        /* Clear out the tags using diagnostics. */
 630        for (i = 0; i < 16; i++) {
 631                unsigned long ptag, ltag;
 632
 633                ptag = strbuf->strbuf_control +
 634                        (STRBUF_PTAGDIAG - STRBUF_CONTROL);
 635                ltag = strbuf->strbuf_control +
 636                        (STRBUF_LTAGDIAG - STRBUF_CONTROL);
 637                ptag += (unsigned long)i * 8UL;
 638                ltag += (unsigned long)i * 8UL;
 639
 640                upa_writeq(0UL, ptag);
 641                upa_writeq(0UL, ltag);
 642        }
 643
 644        /* Enable DVMA arbitration for all devices/slots. */
 645        control = upa_readq(iommu->write_complete_reg);
 646        control |= 0x3fUL;
 647        upa_writeq(control, iommu->write_complete_reg);
 648
 649        /* Now some Xfire specific grot... */
 650        if (this_is_starfire)
 651                starfire_hookup(portid);
 652
 653        sysio_register_error_handlers(op);
 654        return;
 655
 656fatal_memory_error:
 657        kfree(iommu);
 658        kfree(strbuf);
 659        prom_printf("sbus_iommu_init: Fatal memory allocation error.\n");
 660}
 661
 662static int __init sbus_init(void)
 663{
 664        struct device_node *dp;
 665
 666        for_each_node_by_name(dp, "sbus") {
 667                struct platform_device *op = of_find_device_by_node(dp);
 668
 669                sbus_iommu_init(op);
 670                of_propagate_archdata(op);
 671        }
 672
 673        return 0;
 674}
 675
 676subsys_initcall(sbus_init);
 677