1/* 2 * Copyright 2012 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15/* Machine-generated file; do not edit. */ 16 17#ifndef __ARCH_MPIPE_H__ 18#define __ARCH_MPIPE_H__ 19 20#include <arch/abi.h> 21#include <arch/mpipe_def.h> 22 23#ifndef __ASSEMBLER__ 24 25/* 26 * MMIO Ingress DMA Release Region Address. 27 * This is a description of the physical addresses used to manipulate ingress 28 * credit counters. Accesses to this address space should use an address of 29 * this form and a value like that specified in IDMA_RELEASE_REGION_VAL. 30 */ 31 32__extension__ 33typedef union 34{ 35 struct 36 { 37#ifndef __BIG_ENDIAN__ 38 /* Reserved. */ 39 uint_reg_t __reserved_0 : 3; 40 /* NotifRing to be released */ 41 uint_reg_t ring : 8; 42 /* Bucket to be released */ 43 uint_reg_t bucket : 13; 44 /* Enable NotifRing release */ 45 uint_reg_t ring_enable : 1; 46 /* Enable Bucket release */ 47 uint_reg_t bucket_enable : 1; 48 /* 49 * This field of the address selects the region (address space) to be 50 * accessed. For the iDMA release region, this field must be 4. 51 */ 52 uint_reg_t region : 3; 53 /* Reserved. */ 54 uint_reg_t __reserved_1 : 6; 55 /* This field of the address indexes the 32 entry service domain table. */ 56 uint_reg_t svc_dom : 5; 57 /* Reserved. */ 58 uint_reg_t __reserved_2 : 24; 59#else /* __BIG_ENDIAN__ */ 60 uint_reg_t __reserved_2 : 24; 61 uint_reg_t svc_dom : 5; 62 uint_reg_t __reserved_1 : 6; 63 uint_reg_t region : 3; 64 uint_reg_t bucket_enable : 1; 65 uint_reg_t ring_enable : 1; 66 uint_reg_t bucket : 13; 67 uint_reg_t ring : 8; 68 uint_reg_t __reserved_0 : 3; 69#endif 70 }; 71 72 uint_reg_t word; 73} MPIPE_IDMA_RELEASE_REGION_ADDR_t; 74 75/* 76 * MMIO Ingress DMA Release Region Value - Release NotifRing and/or Bucket. 77 * Provides release of the associated NotifRing. The address of the MMIO 78 * operation is described in IDMA_RELEASE_REGION_ADDR. 79 */ 80 81__extension__ 82typedef union 83{ 84 struct 85 { 86#ifndef __BIG_ENDIAN__ 87 /* 88 * Number of packets being released. The load balancer's count of 89 * inflight packets will be decremented by this amount for the associated 90 * Bucket and/or NotifRing 91 */ 92 uint_reg_t count : 16; 93 /* Reserved. */ 94 uint_reg_t __reserved : 48; 95#else /* __BIG_ENDIAN__ */ 96 uint_reg_t __reserved : 48; 97 uint_reg_t count : 16; 98#endif 99 }; 100 101 uint_reg_t word; 102} MPIPE_IDMA_RELEASE_REGION_VAL_t; 103 104/* 105 * MMIO Buffer Stack Manager Region Address. 106 * This MMIO region is used for posting or fetching buffers to/from the 107 * buffer stack manager. On an MMIO load, this pops a buffer descriptor from 108 * the top of stack if one is available. On an MMIO store, this pushes a 109 * buffer to the stack. The value read or written is described in 110 * BSM_REGION_VAL. 111 */ 112 113__extension__ 114typedef union 115{ 116 struct 117 { 118#ifndef __BIG_ENDIAN__ 119 /* Reserved. */ 120 uint_reg_t __reserved_0 : 3; 121 /* BufferStack being accessed. */ 122 uint_reg_t stack : 5; 123 /* Reserved. */ 124 uint_reg_t __reserved_1 : 18; 125 /* 126 * This field of the address selects the region (address space) to be 127 * accessed. For the buffer stack manager region, this field must be 6. 128 */ 129 uint_reg_t region : 3; 130 /* Reserved. */ 131 uint_reg_t __reserved_2 : 6; 132 /* This field of the address indexes the 32 entry service domain table. */ 133 uint_reg_t svc_dom : 5; 134 /* Reserved. */ 135 uint_reg_t __reserved_3 : 24; 136#else /* __BIG_ENDIAN__ */ 137 uint_reg_t __reserved_3 : 24; 138 uint_reg_t svc_dom : 5; 139 uint_reg_t __reserved_2 : 6; 140 uint_reg_t region : 3; 141 uint_reg_t __reserved_1 : 18; 142 uint_reg_t stack : 5; 143 uint_reg_t __reserved_0 : 3; 144#endif 145 }; 146 147 uint_reg_t word; 148} MPIPE_BSM_REGION_ADDR_t; 149 150/* 151 * MMIO Buffer Stack Manager Region Value. 152 * This MMIO region is used for posting or fetching buffers to/from the 153 * buffer stack manager. On an MMIO load, this pops a buffer descriptor from 154 * the top of stack if one is available. On an MMIO store, this pushes a 155 * buffer to the stack. The address of the MMIO operation is described in 156 * BSM_REGION_ADDR. 157 */ 158 159__extension__ 160typedef union 161{ 162 struct 163 { 164#ifndef __BIG_ENDIAN__ 165 /* Reserved. */ 166 uint_reg_t __reserved_0 : 7; 167 /* 168 * Base virtual address of the buffer. Must be sign extended by consumer. 169 */ 170 int_reg_t va : 35; 171 /* Reserved. */ 172 uint_reg_t __reserved_1 : 6; 173 /* 174 * Index of the buffer stack to which this buffer belongs. Ignored on 175 * writes since the offset bits specify the stack being accessed. 176 */ 177 uint_reg_t stack_idx : 5; 178 /* Reserved. */ 179 uint_reg_t __reserved_2 : 3; 180 /* 181 * Instance ID. For devices that support automatic buffer return between 182 * mPIPE instances, this field indicates the buffer owner. If the INST 183 * field does not match the mPIPE's instance number when a packet is 184 * egressed, buffers with HWB set will be returned to the other mPIPE 185 * instance. Note that not all devices support multi-mPIPE buffer 186 * return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates 187 * whether the INST field in the buffer descriptor is populated by iDMA 188 * hardware. This field is ignored on writes. 189 */ 190 uint_reg_t inst : 2; 191 /* 192 * Reads as one to indicate that this is a hardware managed buffer. 193 * Ignored on writes since all buffers on a given stack are the same size. 194 */ 195 uint_reg_t hwb : 1; 196 /* 197 * Encoded size of buffer (ignored on writes): 198 * 0 = 128 bytes 199 * 1 = 256 bytes 200 * 2 = 512 bytes 201 * 3 = 1024 bytes 202 * 4 = 1664 bytes 203 * 5 = 4096 bytes 204 * 6 = 10368 bytes 205 * 7 = 16384 bytes 206 */ 207 uint_reg_t size : 3; 208 /* 209 * Valid indication for the buffer. Ignored on writes. 210 * 0 : Valid buffer descriptor popped from stack. 211 * 3 : Could not pop a buffer from the stack. Either the stack is empty, 212 * or the hardware's prefetch buffer is empty for this stack. 213 */ 214 uint_reg_t c : 2; 215#else /* __BIG_ENDIAN__ */ 216 uint_reg_t c : 2; 217 uint_reg_t size : 3; 218 uint_reg_t hwb : 1; 219 uint_reg_t inst : 2; 220 uint_reg_t __reserved_2 : 3; 221 uint_reg_t stack_idx : 5; 222 uint_reg_t __reserved_1 : 6; 223 int_reg_t va : 35; 224 uint_reg_t __reserved_0 : 7; 225#endif 226 }; 227 228 uint_reg_t word; 229} MPIPE_BSM_REGION_VAL_t; 230 231/* 232 * MMIO Egress DMA Post Region Address. 233 * Used to post descriptor locations to the eDMA descriptor engine. The 234 * value to be written is described in EDMA_POST_REGION_VAL 235 */ 236 237__extension__ 238typedef union 239{ 240 struct 241 { 242#ifndef __BIG_ENDIAN__ 243 /* Reserved. */ 244 uint_reg_t __reserved_0 : 3; 245 /* eDMA ring being accessed */ 246 uint_reg_t ring : 6; 247 /* Reserved. */ 248 uint_reg_t __reserved_1 : 17; 249 /* 250 * This field of the address selects the region (address space) to be 251 * accessed. For the egress DMA post region, this field must be 5. 252 */ 253 uint_reg_t region : 3; 254 /* Reserved. */ 255 uint_reg_t __reserved_2 : 6; 256 /* This field of the address indexes the 32 entry service domain table. */ 257 uint_reg_t svc_dom : 5; 258 /* Reserved. */ 259 uint_reg_t __reserved_3 : 24; 260#else /* __BIG_ENDIAN__ */ 261 uint_reg_t __reserved_3 : 24; 262 uint_reg_t svc_dom : 5; 263 uint_reg_t __reserved_2 : 6; 264 uint_reg_t region : 3; 265 uint_reg_t __reserved_1 : 17; 266 uint_reg_t ring : 6; 267 uint_reg_t __reserved_0 : 3; 268#endif 269 }; 270 271 uint_reg_t word; 272} MPIPE_EDMA_POST_REGION_ADDR_t; 273 274/* 275 * MMIO Egress DMA Post Region Value. 276 * Used to post descriptor locations to the eDMA descriptor engine. The 277 * address is described in EDMA_POST_REGION_ADDR. 278 */ 279 280__extension__ 281typedef union 282{ 283 struct 284 { 285#ifndef __BIG_ENDIAN__ 286 /* 287 * For writes, this specifies the current ring tail pointer prior to any 288 * post. For example, to post 1 or more descriptors starting at location 289 * 23, this would contain 23 (not 24). On writes, this index must be 290 * masked based on the ring size. The new tail pointer after this post 291 * is COUNT+RING_IDX (masked by the ring size). 292 * 293 * For reads, this provides the hardware descriptor fetcher's head 294 * pointer. The descriptors prior to the head pointer, however, may not 295 * yet have been processed so this indicator is only used to determine 296 * how full the ring is and if software may post more descriptors. 297 */ 298 uint_reg_t ring_idx : 16; 299 /* 300 * For writes, this specifies number of contiguous descriptors that are 301 * being posted. Software may post up to RingSize descriptors with a 302 * single MMIO store. A zero in this field on a write will "wake up" an 303 * eDMA ring and cause it fetch descriptors regardless of the hardware's 304 * current view of the state of the tail pointer. 305 * 306 * For reads, this field provides a rolling count of the number of 307 * descriptors that have been completely processed. This may be used by 308 * software to determine when buffers associated with a descriptor may be 309 * returned or reused. When the ring's flush bit is cleared by software 310 * (after having been set by HW or SW), the COUNT will be cleared. 311 */ 312 uint_reg_t count : 16; 313 /* 314 * For writes, this specifies the generation number of the tail being 315 * posted. Note that if tail+cnt wraps to the beginning of the ring, the 316 * eDMA hardware assumes that the descriptors posted at the beginning of 317 * the ring are also valid so it is okay to post around the wrap point. 318 * 319 * For reads, this is the current generation number. Valid descriptors 320 * will have the inverse of this generation number. 321 */ 322 uint_reg_t gen : 1; 323 /* Reserved. */ 324 uint_reg_t __reserved : 31; 325#else /* __BIG_ENDIAN__ */ 326 uint_reg_t __reserved : 31; 327 uint_reg_t gen : 1; 328 uint_reg_t count : 16; 329 uint_reg_t ring_idx : 16; 330#endif 331 }; 332 333 uint_reg_t word; 334} MPIPE_EDMA_POST_REGION_VAL_t; 335 336/* 337 * Load Balancer Bucket Status Data. 338 * Read/Write data for load balancer Bucket-Status Table. 4160 entries 339 * indexed by LBL_INIT_CTL.IDX when LBL_INIT_CTL.STRUCT_SEL is BSTS_TBL 340 */ 341 342__extension__ 343typedef union 344{ 345 struct 346 { 347#ifndef __BIG_ENDIAN__ 348 /* NotifRing currently assigned to this bucket. */ 349 uint_reg_t notifring : 8; 350 /* Current reference count. */ 351 uint_reg_t count : 16; 352 /* Group associated with this bucket. */ 353 uint_reg_t group : 5; 354 /* Mode select for this bucket. */ 355 uint_reg_t mode : 3; 356 /* Reserved. */ 357 uint_reg_t __reserved : 32; 358#else /* __BIG_ENDIAN__ */ 359 uint_reg_t __reserved : 32; 360 uint_reg_t mode : 3; 361 uint_reg_t group : 5; 362 uint_reg_t count : 16; 363 uint_reg_t notifring : 8; 364#endif 365 }; 366 367 uint_reg_t word; 368} MPIPE_LBL_INIT_DAT_BSTS_TBL_t; 369#endif /* !defined(__ASSEMBLER__) */ 370 371#endif /* !defined(__ARCH_MPIPE_H__) */ 372