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11#ifndef _ASM_X86_UV_UV_BAU_H
12#define _ASM_X86_UV_UV_BAU_H
13
14#include <linux/bitmap.h>
15#define BITSPERBYTE 8
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35
36#define MAX_CPUS_PER_UVHUB 128
37#define MAX_CPUS_PER_SOCKET 64
38#define ADP_SZ 64
39#define UV_CPUS_PER_AS 32
40#define ITEMS_PER_DESC 8
41
42#define MAX_BAU_CONCURRENT 3
43#define UV_ACT_STATUS_MASK 0x3
44#define UV_ACT_STATUS_SIZE 2
45#define UV_DISTRIBUTION_SIZE 256
46#define UV_SW_ACK_NPENDING 8
47#define UV1_NET_ENDPOINT_INTD 0x38
48#define UV2_NET_ENDPOINT_INTD 0x28
49#define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51#define UV_DESC_PSHIFT 49
52#define UV_PAYLOADQ_PNODE_SHIFT 49
53#define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
54#define UV_BAU_BASENAME "sgi_uv/bau_tunables"
55#define UV_BAU_TUNABLES_DIR "sgi_uv"
56#define UV_BAU_TUNABLES_FILE "bau_tunables"
57#define WHITESPACE " \t\n"
58#define uv_mmask ((1UL << uv_hub_info->m_val) - 1)
59#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
60#define cpubit_isset(cpu, bau_local_cpumask) \
61 test_bit((cpu), (bau_local_cpumask).bits)
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69
70#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
71#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
72
73#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
74 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
75 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
76
77
78#define BAU_MISC_CONTROL_MULT_MASK 3
79
80#define UVH_AGING_PRESCALE_SEL 0x000000b000UL
81
82#define BAU_URGENCY_7_SHIFT 28
83#define BAU_URGENCY_7_MASK 7
84
85#define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
86
87#define BAU_TRANS_SHIFT 40
88#define BAU_TRANS_MASK 0x3f
89
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91
92
93#define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
94#define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
95#define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
96#define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
97#define PREFETCH_HINT_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT
98#define SB_STATUS_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
99#define write_gmmr uv_write_global_mmr64
100#define write_lmmr uv_write_local_mmr
101#define read_lmmr uv_read_local_mmr
102#define read_gmmr uv_read_global_mmr64
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106
107#define DS_IDLE 0
108#define DS_ACTIVE 1
109#define DS_DESTINATION_TIMEOUT 2
110#define DS_SOURCE_TIMEOUT 3
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123#define UV2H_DESC_IDLE 0
124#define UV2H_DESC_BUSY 2
125#define UV2H_DESC_DEST_TIMEOUT 4
126#define UV2H_DESC_DEST_STRONG_NACK 5
127#define UV2H_DESC_SOURCE_TIMEOUT 6
128#define UV2H_DESC_DEST_PUT_ERR 7
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132
133#define PLUGGED_DELAY 10
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139#define PLUGSB4RESET 100
140
141#define TIMEOUTSB4RESET 1
142
143#define IPI_RESET_LIMIT 1
144
145#define COMPLETE_THRESHOLD 5
146
147
148#define GIVEUP_LIMIT 100
149
150#define UV_LB_SUBNODEID 0x10
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152
153#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
154#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
155
156#define UV2_ACK_MASK 0x7UL
157#define UV2_ACK_UNITS_SHFT 3
158#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
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162
163#define DEST_Q_SIZE 20
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166
167#define DEST_NUM_RESOURCES 8
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171#define FLUSH_RETRY_PLUGGED 1
172#define FLUSH_RETRY_TIMEOUT 2
173#define FLUSH_GIVEUP 3
174#define FLUSH_COMPLETE 4
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178
179#define CONGESTED_RESPONSE_US 1000
180
181#define CONGESTED_REPS 10
182
183#define DISABLED_PERIOD 10
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185
186#define MSG_NOOP 0
187#define MSG_REGULAR 1
188#define MSG_RETRY 2
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199
200struct pnmask {
201 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
202};
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209struct bau_local_cpumask {
210 unsigned long bits;
211};
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230struct bau_msg_payload {
231 unsigned long address;
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234 unsigned short sending_cpu;
235
236 unsigned short acknowledge_count;
237
238 unsigned int reserved1:32;
239};
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245
246struct uv1_bau_msg_header {
247 unsigned int dest_subnodeid:6;
248
249 unsigned int base_dest_nasid:15;
250
251 unsigned int command:8;
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254 unsigned int rsvd_1:3;
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257 unsigned int rsvd_2:9;
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260 unsigned int sequence:16;
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267 unsigned int rsvd_3:1;
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272 unsigned int replied_to:1;
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275 unsigned int msg_type:3;
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278 unsigned int canceled:1;
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281 unsigned int payload_1a:1;
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283 unsigned int payload_1b:2;
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287 unsigned int payload_1ca:6;
288
289 unsigned int payload_1c:2;
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293 unsigned int payload_1d:6;
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295 unsigned int payload_1e:2;
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298 unsigned int rsvd_4:7;
299
300 unsigned int swack_flag:1;
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305 unsigned int rsvd_5:6;
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307 unsigned int rsvd_6:5;
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309 unsigned int int_both:1;
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312 unsigned int fairness:3;
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314 unsigned int multilevel:1;
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318 unsigned int chaining:1;
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321 unsigned int rsvd_7:21;
322
323};
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330struct uv2_3_bau_msg_header {
331 unsigned int base_dest_nasid:15;
332
333 unsigned int dest_subnodeid:5;
334
335 unsigned int rsvd_1:1;
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341 unsigned int replied_to:1;
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344 unsigned int msg_type:3;
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347 unsigned int canceled:1;
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350 unsigned int payload_1:3;
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354 unsigned int payload_2a:3;
355 unsigned int payload_2b:5;
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359 unsigned int payload_3:8;
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362 unsigned int rsvd_2:7;
363
364 unsigned int swack_flag:1;
365
366 unsigned int rsvd_3a:3;
367 unsigned int rsvd_3b:8;
368 unsigned int rsvd_3c:8;
369 unsigned int rsvd_3d:3;
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371 unsigned int fairness:3;
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374 unsigned int sequence:16;
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376 unsigned int chaining:1;
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379 unsigned int multilevel:1;
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382 unsigned int rsvd_4:24;
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386 unsigned int command:8;
387
388};
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395struct bau_desc {
396 struct pnmask distribution;
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400 union bau_msg_header {
401 struct uv1_bau_msg_header uv1_hdr;
402 struct uv2_3_bau_msg_header uv2_3_hdr;
403 } header;
404
405 struct bau_msg_payload payload;
406};
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439struct bau_pq_entry {
440 unsigned long address;
441
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443 unsigned short sending_cpu;
444
445 unsigned short acknowledge_count;
446
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448 unsigned short replied_to:1;
449 unsigned short msg_type:3;
450 unsigned short canceled:1;
451 unsigned short unused1:3;
452
453 unsigned char unused2a;
454
455 unsigned char unused2;
456
457 unsigned char swack_vec;
458
459 unsigned short sequence;
460
461 unsigned char unused4[2];
462
463 int number_of_cpus;
464
465 unsigned char unused5[8];
466
467};
468
469struct msg_desc {
470 struct bau_pq_entry *msg;
471 int msg_slot;
472 struct bau_pq_entry *queue_first;
473 struct bau_pq_entry *queue_last;
474};
475
476struct reset_args {
477 int sender;
478};
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483struct ptc_stats {
484
485 unsigned long s_giveup;
486
487 unsigned long s_requestor;
488
489 unsigned long s_stimeout;
490 unsigned long s_dtimeout;
491 unsigned long s_strongnacks;
492 unsigned long s_time;
493 unsigned long s_retriesok;
494 unsigned long s_ntargcpu;
495
496 unsigned long s_ntargself;
497
498 unsigned long s_ntarglocals;
499
500 unsigned long s_ntargremotes;
501
502 unsigned long s_ntarglocaluvhub;
503 unsigned long s_ntargremoteuvhub;
504 unsigned long s_ntarguvhub;
505
506 unsigned long s_ntarguvhub16;
507
508 unsigned long s_ntarguvhub8;
509
510 unsigned long s_ntarguvhub4;
511
512 unsigned long s_ntarguvhub2;
513
514 unsigned long s_ntarguvhub1;
515
516 unsigned long s_resets_plug;
517
518 unsigned long s_resets_timeout;
519
520 unsigned long s_busy;
521
522 unsigned long s_throttles;
523 unsigned long s_retry_messages;
524 unsigned long s_bau_reenabled;
525 unsigned long s_bau_disabled;
526 unsigned long s_uv2_wars;
527 unsigned long s_uv2_wars_hw;
528 unsigned long s_uv2_war_waits;
529 unsigned long s_overipilimit;
530 unsigned long s_giveuplimit;
531 unsigned long s_enters;
532 unsigned long s_ipifordisabled;
533 unsigned long s_plugged;
534 unsigned long s_congested;
535
536 unsigned long d_alltlb;
537
538 unsigned long d_onetlb;
539
540 unsigned long d_multmsg;
541
542 unsigned long d_nomsg;
543 unsigned long d_time;
544
545 unsigned long d_requestee;
546
547 unsigned long d_retries;
548
549 unsigned long d_canceled;
550
551 unsigned long d_nocanceled;
552
553 unsigned long d_resets;
554
555 unsigned long d_rcanceled;
556
557};
558
559struct tunables {
560 int *tunp;
561 int deflt;
562};
563
564struct hub_and_pnode {
565 short uvhub;
566 short pnode;
567};
568
569struct socket_desc {
570 short num_cpus;
571 short cpu_number[MAX_CPUS_PER_SOCKET];
572};
573
574struct uvhub_desc {
575 unsigned short socket_mask;
576 short num_cpus;
577 short uvhub;
578 short pnode;
579 struct socket_desc socket[2];
580};
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585struct bau_control {
586 struct bau_desc *descriptor_base;
587 struct bau_pq_entry *queue_first;
588 struct bau_pq_entry *queue_last;
589 struct bau_pq_entry *bau_msg_head;
590 struct bau_control *uvhub_master;
591 struct bau_control *socket_master;
592 struct ptc_stats *statp;
593 cpumask_t *cpumask;
594 unsigned long timeout_interval;
595 unsigned long set_bau_on_time;
596 atomic_t active_descriptor_count;
597 int plugged_tries;
598 int timeout_tries;
599 int ipi_attempts;
600 int conseccompletes;
601 bool nobau;
602 short baudisabled;
603 short cpu;
604 short osnode;
605 short uvhub_cpu;
606 short uvhub;
607 short uvhub_version;
608 short cpus_in_socket;
609 short cpus_in_uvhub;
610 short partition_base_pnode;
611 short busy;
612 unsigned short message_number;
613 unsigned short uvhub_quiesce;
614 short socket_acknowledge_count[DEST_Q_SIZE];
615 cycles_t send_message;
616 cycles_t period_end;
617 cycles_t period_time;
618 spinlock_t uvhub_lock;
619 spinlock_t queue_lock;
620 spinlock_t disable_lock;
621
622 int max_concurr;
623 int max_concurr_const;
624 int plugged_delay;
625 int plugsb4reset;
626 int timeoutsb4reset;
627 int ipi_reset_limit;
628 int complete_threshold;
629 int cong_response_us;
630 int cong_reps;
631 cycles_t disabled_period;
632 int period_giveups;
633 int giveup_limit;
634 long period_requests;
635 struct hub_and_pnode *thp;
636};
637
638static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
639{
640 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
641}
642
643static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
644{
645 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
646}
647
648static inline void write_mmr_activation(unsigned long index)
649{
650 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
651}
652
653static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
654{
655 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
656}
657
658static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
659{
660 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
661}
662
663static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
664{
665 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
666}
667
668static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
669{
670 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
671}
672
673static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
674{
675 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
676}
677
678static inline unsigned long read_mmr_misc_control(int pnode)
679{
680 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
681}
682
683static inline void write_mmr_sw_ack(unsigned long mr)
684{
685 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
686}
687
688static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
689{
690 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
691}
692
693static inline unsigned long read_mmr_sw_ack(void)
694{
695 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
696}
697
698static inline unsigned long read_gmmr_sw_ack(int pnode)
699{
700 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
701}
702
703static inline void write_mmr_data_config(int pnode, unsigned long mr)
704{
705 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
706}
707
708static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
709{
710 return constant_test_bit(uvhub, &dstp->bits[0]);
711}
712static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
713{
714 __set_bit(pnode, &dstp->bits[0]);
715}
716static inline void bau_uvhubs_clear(struct pnmask *dstp,
717 int nbits)
718{
719 bitmap_zero(&dstp->bits[0], nbits);
720}
721static inline int bau_uvhub_weight(struct pnmask *dstp)
722{
723 return bitmap_weight((unsigned long *)&dstp->bits[0],
724 UV_DISTRIBUTION_SIZE);
725}
726
727static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
728{
729 bitmap_zero(&dstp->bits, nbits);
730}
731
732extern void uv_bau_message_intr1(void);
733#ifdef CONFIG_TRACING
734#define trace_uv_bau_message_intr1 uv_bau_message_intr1
735#endif
736extern void uv_bau_timeout_intr1(void);
737
738struct atomic_short {
739 short counter;
740};
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748static inline int atomic_read_short(const struct atomic_short *v)
749{
750 return v->counter;
751}
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760static inline int atom_asr(short i, struct atomic_short *v)
761{
762 short __i = i;
763 asm volatile(LOCK_PREFIX "xaddw %0, %1"
764 : "+r" (i), "+m" (v->counter)
765 : : "memory");
766 return i + __i;
767}
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779static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
780{
781 spin_lock(lock);
782 if (atomic_read(v) >= u) {
783 spin_unlock(lock);
784 return 0;
785 }
786 atomic_inc(v);
787 spin_unlock(lock);
788 return 1;
789}
790
791#endif
792