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24#ifndef VMX_H
25#define VMX_H
26
27
28#include <linux/types.h>
29#include <uapi/asm/vmx.h>
30
31
32
33
34#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
35#define CPU_BASED_USE_TSC_OFFSETING 0x00000008
36#define CPU_BASED_HLT_EXITING 0x00000080
37#define CPU_BASED_INVLPG_EXITING 0x00000200
38#define CPU_BASED_MWAIT_EXITING 0x00000400
39#define CPU_BASED_RDPMC_EXITING 0x00000800
40#define CPU_BASED_RDTSC_EXITING 0x00001000
41#define CPU_BASED_CR3_LOAD_EXITING 0x00008000
42#define CPU_BASED_CR3_STORE_EXITING 0x00010000
43#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
44#define CPU_BASED_CR8_STORE_EXITING 0x00100000
45#define CPU_BASED_TPR_SHADOW 0x00200000
46#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
47#define CPU_BASED_MOV_DR_EXITING 0x00800000
48#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
49#define CPU_BASED_USE_IO_BITMAPS 0x02000000
50#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
51#define CPU_BASED_USE_MSR_BITMAPS 0x10000000
52#define CPU_BASED_MONITOR_EXITING 0x20000000
53#define CPU_BASED_PAUSE_EXITING 0x40000000
54#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
55
56#define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
57
58
59
60
61#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
62#define SECONDARY_EXEC_ENABLE_EPT 0x00000002
63#define SECONDARY_EXEC_RDTSCP 0x00000008
64#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
65#define SECONDARY_EXEC_ENABLE_VPID 0x00000020
66#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
67#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
68#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
69#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
70#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
71#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
72#define SECONDARY_EXEC_SHADOW_VMCS 0x00004000
73#define SECONDARY_EXEC_ENABLE_PML 0x00020000
74#define SECONDARY_EXEC_XSAVES 0x00100000
75#define SECONDARY_EXEC_TSC_SCALING 0x02000000
76
77#define PIN_BASED_EXT_INTR_MASK 0x00000001
78#define PIN_BASED_NMI_EXITING 0x00000008
79#define PIN_BASED_VIRTUAL_NMIS 0x00000020
80#define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
81#define PIN_BASED_POSTED_INTR 0x00000080
82
83#define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
84
85#define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
86#define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
87#define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
88#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
89#define VM_EXIT_SAVE_IA32_PAT 0x00040000
90#define VM_EXIT_LOAD_IA32_PAT 0x00080000
91#define VM_EXIT_SAVE_IA32_EFER 0x00100000
92#define VM_EXIT_LOAD_IA32_EFER 0x00200000
93#define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
94#define VM_EXIT_CLEAR_BNDCFGS 0x00800000
95
96#define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
97
98#define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
99#define VM_ENTRY_IA32E_MODE 0x00000200
100#define VM_ENTRY_SMM 0x00000400
101#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
102#define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
103#define VM_ENTRY_LOAD_IA32_PAT 0x00004000
104#define VM_ENTRY_LOAD_IA32_EFER 0x00008000
105#define VM_ENTRY_LOAD_BNDCFGS 0x00010000
106
107#define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
108
109#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
110#define VMX_MISC_SAVE_EFER_LMA 0x00000020
111#define VMX_MISC_ACTIVITY_HLT 0x00000040
112
113
114enum vmcs_field {
115 VIRTUAL_PROCESSOR_ID = 0x00000000,
116 POSTED_INTR_NV = 0x00000002,
117 GUEST_ES_SELECTOR = 0x00000800,
118 GUEST_CS_SELECTOR = 0x00000802,
119 GUEST_SS_SELECTOR = 0x00000804,
120 GUEST_DS_SELECTOR = 0x00000806,
121 GUEST_FS_SELECTOR = 0x00000808,
122 GUEST_GS_SELECTOR = 0x0000080a,
123 GUEST_LDTR_SELECTOR = 0x0000080c,
124 GUEST_TR_SELECTOR = 0x0000080e,
125 GUEST_INTR_STATUS = 0x00000810,
126 GUEST_PML_INDEX = 0x00000812,
127 HOST_ES_SELECTOR = 0x00000c00,
128 HOST_CS_SELECTOR = 0x00000c02,
129 HOST_SS_SELECTOR = 0x00000c04,
130 HOST_DS_SELECTOR = 0x00000c06,
131 HOST_FS_SELECTOR = 0x00000c08,
132 HOST_GS_SELECTOR = 0x00000c0a,
133 HOST_TR_SELECTOR = 0x00000c0c,
134 IO_BITMAP_A = 0x00002000,
135 IO_BITMAP_A_HIGH = 0x00002001,
136 IO_BITMAP_B = 0x00002002,
137 IO_BITMAP_B_HIGH = 0x00002003,
138 MSR_BITMAP = 0x00002004,
139 MSR_BITMAP_HIGH = 0x00002005,
140 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
141 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
142 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
143 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
144 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
145 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
146 PML_ADDRESS = 0x0000200e,
147 PML_ADDRESS_HIGH = 0x0000200f,
148 TSC_OFFSET = 0x00002010,
149 TSC_OFFSET_HIGH = 0x00002011,
150 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
151 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
152 APIC_ACCESS_ADDR = 0x00002014,
153 APIC_ACCESS_ADDR_HIGH = 0x00002015,
154 POSTED_INTR_DESC_ADDR = 0x00002016,
155 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
156 EPT_POINTER = 0x0000201a,
157 EPT_POINTER_HIGH = 0x0000201b,
158 EOI_EXIT_BITMAP0 = 0x0000201c,
159 EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
160 EOI_EXIT_BITMAP1 = 0x0000201e,
161 EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
162 EOI_EXIT_BITMAP2 = 0x00002020,
163 EOI_EXIT_BITMAP2_HIGH = 0x00002021,
164 EOI_EXIT_BITMAP3 = 0x00002022,
165 EOI_EXIT_BITMAP3_HIGH = 0x00002023,
166 VMREAD_BITMAP = 0x00002026,
167 VMWRITE_BITMAP = 0x00002028,
168 XSS_EXIT_BITMAP = 0x0000202C,
169 XSS_EXIT_BITMAP_HIGH = 0x0000202D,
170 TSC_MULTIPLIER = 0x00002032,
171 TSC_MULTIPLIER_HIGH = 0x00002033,
172 GUEST_PHYSICAL_ADDRESS = 0x00002400,
173 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
174 VMCS_LINK_POINTER = 0x00002800,
175 VMCS_LINK_POINTER_HIGH = 0x00002801,
176 GUEST_IA32_DEBUGCTL = 0x00002802,
177 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
178 GUEST_IA32_PAT = 0x00002804,
179 GUEST_IA32_PAT_HIGH = 0x00002805,
180 GUEST_IA32_EFER = 0x00002806,
181 GUEST_IA32_EFER_HIGH = 0x00002807,
182 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
183 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
184 GUEST_PDPTR0 = 0x0000280a,
185 GUEST_PDPTR0_HIGH = 0x0000280b,
186 GUEST_PDPTR1 = 0x0000280c,
187 GUEST_PDPTR1_HIGH = 0x0000280d,
188 GUEST_PDPTR2 = 0x0000280e,
189 GUEST_PDPTR2_HIGH = 0x0000280f,
190 GUEST_PDPTR3 = 0x00002810,
191 GUEST_PDPTR3_HIGH = 0x00002811,
192 GUEST_BNDCFGS = 0x00002812,
193 GUEST_BNDCFGS_HIGH = 0x00002813,
194 HOST_IA32_PAT = 0x00002c00,
195 HOST_IA32_PAT_HIGH = 0x00002c01,
196 HOST_IA32_EFER = 0x00002c02,
197 HOST_IA32_EFER_HIGH = 0x00002c03,
198 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
199 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
200 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
201 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
202 EXCEPTION_BITMAP = 0x00004004,
203 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
204 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
205 CR3_TARGET_COUNT = 0x0000400a,
206 VM_EXIT_CONTROLS = 0x0000400c,
207 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
208 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
209 VM_ENTRY_CONTROLS = 0x00004012,
210 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
211 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
212 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
213 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
214 TPR_THRESHOLD = 0x0000401c,
215 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
216 PLE_GAP = 0x00004020,
217 PLE_WINDOW = 0x00004022,
218 VM_INSTRUCTION_ERROR = 0x00004400,
219 VM_EXIT_REASON = 0x00004402,
220 VM_EXIT_INTR_INFO = 0x00004404,
221 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
222 IDT_VECTORING_INFO_FIELD = 0x00004408,
223 IDT_VECTORING_ERROR_CODE = 0x0000440a,
224 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
225 VMX_INSTRUCTION_INFO = 0x0000440e,
226 GUEST_ES_LIMIT = 0x00004800,
227 GUEST_CS_LIMIT = 0x00004802,
228 GUEST_SS_LIMIT = 0x00004804,
229 GUEST_DS_LIMIT = 0x00004806,
230 GUEST_FS_LIMIT = 0x00004808,
231 GUEST_GS_LIMIT = 0x0000480a,
232 GUEST_LDTR_LIMIT = 0x0000480c,
233 GUEST_TR_LIMIT = 0x0000480e,
234 GUEST_GDTR_LIMIT = 0x00004810,
235 GUEST_IDTR_LIMIT = 0x00004812,
236 GUEST_ES_AR_BYTES = 0x00004814,
237 GUEST_CS_AR_BYTES = 0x00004816,
238 GUEST_SS_AR_BYTES = 0x00004818,
239 GUEST_DS_AR_BYTES = 0x0000481a,
240 GUEST_FS_AR_BYTES = 0x0000481c,
241 GUEST_GS_AR_BYTES = 0x0000481e,
242 GUEST_LDTR_AR_BYTES = 0x00004820,
243 GUEST_TR_AR_BYTES = 0x00004822,
244 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
245 GUEST_ACTIVITY_STATE = 0X00004826,
246 GUEST_SYSENTER_CS = 0x0000482A,
247 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
248 HOST_IA32_SYSENTER_CS = 0x00004c00,
249 CR0_GUEST_HOST_MASK = 0x00006000,
250 CR4_GUEST_HOST_MASK = 0x00006002,
251 CR0_READ_SHADOW = 0x00006004,
252 CR4_READ_SHADOW = 0x00006006,
253 CR3_TARGET_VALUE0 = 0x00006008,
254 CR3_TARGET_VALUE1 = 0x0000600a,
255 CR3_TARGET_VALUE2 = 0x0000600c,
256 CR3_TARGET_VALUE3 = 0x0000600e,
257 EXIT_QUALIFICATION = 0x00006400,
258 GUEST_LINEAR_ADDRESS = 0x0000640a,
259 GUEST_CR0 = 0x00006800,
260 GUEST_CR3 = 0x00006802,
261 GUEST_CR4 = 0x00006804,
262 GUEST_ES_BASE = 0x00006806,
263 GUEST_CS_BASE = 0x00006808,
264 GUEST_SS_BASE = 0x0000680a,
265 GUEST_DS_BASE = 0x0000680c,
266 GUEST_FS_BASE = 0x0000680e,
267 GUEST_GS_BASE = 0x00006810,
268 GUEST_LDTR_BASE = 0x00006812,
269 GUEST_TR_BASE = 0x00006814,
270 GUEST_GDTR_BASE = 0x00006816,
271 GUEST_IDTR_BASE = 0x00006818,
272 GUEST_DR7 = 0x0000681a,
273 GUEST_RSP = 0x0000681c,
274 GUEST_RIP = 0x0000681e,
275 GUEST_RFLAGS = 0x00006820,
276 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
277 GUEST_SYSENTER_ESP = 0x00006824,
278 GUEST_SYSENTER_EIP = 0x00006826,
279 HOST_CR0 = 0x00006c00,
280 HOST_CR3 = 0x00006c02,
281 HOST_CR4 = 0x00006c04,
282 HOST_FS_BASE = 0x00006c06,
283 HOST_GS_BASE = 0x00006c08,
284 HOST_TR_BASE = 0x00006c0a,
285 HOST_GDTR_BASE = 0x00006c0c,
286 HOST_IDTR_BASE = 0x00006c0e,
287 HOST_IA32_SYSENTER_ESP = 0x00006c10,
288 HOST_IA32_SYSENTER_EIP = 0x00006c12,
289 HOST_RSP = 0x00006c14,
290 HOST_RIP = 0x00006c16,
291};
292
293
294
295
296#define INTR_INFO_VECTOR_MASK 0xff
297#define INTR_INFO_INTR_TYPE_MASK 0x700
298#define INTR_INFO_DELIVER_CODE_MASK 0x800
299#define INTR_INFO_UNBLOCK_NMI 0x1000
300#define INTR_INFO_VALID_MASK 0x80000000
301#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
302
303#define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
304#define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
305#define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
306#define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
307
308#define INTR_TYPE_EXT_INTR (0 << 8)
309#define INTR_TYPE_NMI_INTR (2 << 8)
310#define INTR_TYPE_HARD_EXCEPTION (3 << 8)
311#define INTR_TYPE_SOFT_INTR (4 << 8)
312#define INTR_TYPE_SOFT_EXCEPTION (6 << 8)
313
314
315#define GUEST_INTR_STATE_STI 0x00000001
316#define GUEST_INTR_STATE_MOV_SS 0x00000002
317#define GUEST_INTR_STATE_SMI 0x00000004
318#define GUEST_INTR_STATE_NMI 0x00000008
319
320
321#define GUEST_ACTIVITY_ACTIVE 0
322#define GUEST_ACTIVITY_HLT 1
323#define GUEST_ACTIVITY_SHUTDOWN 2
324#define GUEST_ACTIVITY_WAIT_SIPI 3
325
326
327
328
329#define CONTROL_REG_ACCESS_NUM 0x7
330#define CONTROL_REG_ACCESS_TYPE 0x30
331#define CONTROL_REG_ACCESS_REG 0xf00
332#define LMSW_SOURCE_DATA_SHIFT 16
333#define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT)
334#define REG_EAX (0 << 8)
335#define REG_ECX (1 << 8)
336#define REG_EDX (2 << 8)
337#define REG_EBX (3 << 8)
338#define REG_ESP (4 << 8)
339#define REG_EBP (5 << 8)
340#define REG_ESI (6 << 8)
341#define REG_EDI (7 << 8)
342#define REG_R8 (8 << 8)
343#define REG_R9 (9 << 8)
344#define REG_R10 (10 << 8)
345#define REG_R11 (11 << 8)
346#define REG_R12 (12 << 8)
347#define REG_R13 (13 << 8)
348#define REG_R14 (14 << 8)
349#define REG_R15 (15 << 8)
350
351
352
353
354#define DEBUG_REG_ACCESS_NUM 0x7
355#define DEBUG_REG_ACCESS_TYPE 0x10
356#define TYPE_MOV_TO_DR (0 << 4)
357#define TYPE_MOV_FROM_DR (1 << 4)
358#define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf)
359
360
361
362
363
364#define APIC_ACCESS_OFFSET 0xfff
365#define APIC_ACCESS_TYPE 0xf000
366#define TYPE_LINEAR_APIC_INST_READ (0 << 12)
367#define TYPE_LINEAR_APIC_INST_WRITE (1 << 12)
368#define TYPE_LINEAR_APIC_INST_FETCH (2 << 12)
369#define TYPE_LINEAR_APIC_EVENT (3 << 12)
370#define TYPE_PHYSICAL_APIC_EVENT (10 << 12)
371#define TYPE_PHYSICAL_APIC_INST (15 << 12)
372
373
374#define VMX_SEGMENT_AR_L_MASK (1 << 13)
375
376#define VMX_AR_TYPE_ACCESSES_MASK 1
377#define VMX_AR_TYPE_READABLE_MASK (1 << 1)
378#define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
379#define VMX_AR_TYPE_CODE_MASK (1 << 3)
380#define VMX_AR_TYPE_MASK 0x0f
381#define VMX_AR_TYPE_BUSY_64_TSS 11
382#define VMX_AR_TYPE_BUSY_32_TSS 11
383#define VMX_AR_TYPE_BUSY_16_TSS 3
384#define VMX_AR_TYPE_LDT 2
385
386#define VMX_AR_UNUSABLE_MASK (1 << 16)
387#define VMX_AR_S_MASK (1 << 4)
388#define VMX_AR_P_MASK (1 << 7)
389#define VMX_AR_L_MASK (1 << 13)
390#define VMX_AR_DB_MASK (1 << 14)
391#define VMX_AR_G_MASK (1 << 15)
392#define VMX_AR_DPL_SHIFT 5
393#define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
394
395#define VMX_AR_RESERVD_MASK 0xfffe0f00
396
397#define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
398#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1)
399#define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2)
400
401#define VMX_NR_VPIDS (1 << 16)
402#define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
403#define VMX_VPID_EXTENT_ALL_CONTEXT 2
404
405#define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0
406#define VMX_EPT_EXTENT_CONTEXT 1
407#define VMX_EPT_EXTENT_GLOBAL 2
408#define VMX_EPT_EXTENT_SHIFT 24
409
410#define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
411#define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
412#define VMX_EPTP_UC_BIT (1ull << 8)
413#define VMX_EPTP_WB_BIT (1ull << 14)
414#define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
415#define VMX_EPT_1GB_PAGE_BIT (1ull << 17)
416#define VMX_EPT_INVEPT_BIT (1ull << 20)
417#define VMX_EPT_AD_BIT (1ull << 21)
418#define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
419#define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
420
421#define VMX_VPID_INVVPID_BIT (1ull << 0)
422#define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9)
423#define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10)
424
425#define VMX_EPT_DEFAULT_GAW 3
426#define VMX_EPT_MAX_GAW 0x4
427#define VMX_EPT_MT_EPTE_SHIFT 3
428#define VMX_EPT_GAW_EPTP_SHIFT 3
429#define VMX_EPT_AD_ENABLE_BIT (1ull << 6)
430#define VMX_EPT_DEFAULT_MT 0x6ull
431#define VMX_EPT_READABLE_MASK 0x1ull
432#define VMX_EPT_WRITABLE_MASK 0x2ull
433#define VMX_EPT_EXECUTABLE_MASK 0x4ull
434#define VMX_EPT_IPAT_BIT (1ull << 6)
435#define VMX_EPT_ACCESS_BIT (1ull << 8)
436#define VMX_EPT_DIRTY_BIT (1ull << 9)
437
438#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
439
440
441#define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30"
442#define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2"
443#define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3"
444#define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30"
445#define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0"
446#define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0"
447#define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4"
448#define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4"
449#define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30"
450#define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
451#define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
452
453struct vmx_msr_entry {
454 u32 index;
455 u32 reserved;
456 u64 value;
457} __aligned(16);
458
459
460
461
462#define ENTRY_FAIL_DEFAULT 0
463#define ENTRY_FAIL_PDPTE 2
464#define ENTRY_FAIL_NMI 3
465#define ENTRY_FAIL_VMCS_LINK_PTR 4
466
467
468
469
470enum vm_instruction_error_number {
471 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
472 VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
473 VMXERR_VMCLEAR_VMXON_POINTER = 3,
474 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
475 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
476 VMXERR_VMRESUME_AFTER_VMXOFF = 6,
477 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
478 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
479 VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
480 VMXERR_VMPTRLD_VMXON_POINTER = 10,
481 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
482 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
483 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
484 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
485 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
486 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
487 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
488 VMXERR_VMCALL_NONCLEAR_VMCS = 19,
489 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
490 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
491 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
492 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
493 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
494 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
495 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
496};
497
498#endif
499
