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10#include <linux/acpi.h>
11#include <linux/gpio/driver.h>
12
13#include <linux/gpio.h>
14#include <linux/err.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/ioport.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25#include <linux/platform_device.h>
26#include <linux/property.h>
27#include <linux/spinlock.h>
28#include <linux/platform_data/gpio-dwapb.h>
29#include <linux/slab.h>
30
31#include "gpiolib.h"
32
33#define GPIO_SWPORTA_DR 0x00
34#define GPIO_SWPORTA_DDR 0x04
35#define GPIO_SWPORTB_DR 0x0c
36#define GPIO_SWPORTB_DDR 0x10
37#define GPIO_SWPORTC_DR 0x18
38#define GPIO_SWPORTC_DDR 0x1c
39#define GPIO_SWPORTD_DR 0x24
40#define GPIO_SWPORTD_DDR 0x28
41#define GPIO_INTEN 0x30
42#define GPIO_INTMASK 0x34
43#define GPIO_INTTYPE_LEVEL 0x38
44#define GPIO_INT_POLARITY 0x3c
45#define GPIO_INTSTATUS 0x40
46#define GPIO_PORTA_DEBOUNCE 0x48
47#define GPIO_PORTA_EOI 0x4c
48#define GPIO_EXT_PORTA 0x50
49#define GPIO_EXT_PORTB 0x54
50#define GPIO_EXT_PORTC 0x58
51#define GPIO_EXT_PORTD 0x5c
52
53#define DWAPB_MAX_PORTS 4
54#define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
55#define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
56#define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
57
58struct dwapb_gpio;
59
60#ifdef CONFIG_PM_SLEEP
61
62struct dwapb_context {
63 u32 data;
64 u32 dir;
65 u32 ext;
66 u32 int_en;
67 u32 int_mask;
68 u32 int_type;
69 u32 int_pol;
70 u32 int_deb;
71};
72#endif
73
74struct dwapb_gpio_port {
75 struct gpio_chip gc;
76 bool is_registered;
77 struct dwapb_gpio *gpio;
78#ifdef CONFIG_PM_SLEEP
79 struct dwapb_context *ctx;
80#endif
81 unsigned int idx;
82};
83
84struct dwapb_gpio {
85 struct device *dev;
86 void __iomem *regs;
87 struct dwapb_gpio_port *ports;
88 unsigned int nr_ports;
89 struct irq_domain *domain;
90};
91
92static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
93{
94 struct gpio_chip *gc = &gpio->ports[0].gc;
95 void __iomem *reg_base = gpio->regs;
96
97 return gc->read_reg(reg_base + offset);
98}
99
100static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
101 u32 val)
102{
103 struct gpio_chip *gc = &gpio->ports[0].gc;
104 void __iomem *reg_base = gpio->regs;
105
106 gc->write_reg(reg_base + offset, val);
107}
108
109static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
110{
111 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
112 struct dwapb_gpio *gpio = port->gpio;
113
114 return irq_find_mapping(gpio->domain, offset);
115}
116
117static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
118{
119 u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
120
121 if (gpio_get_value(gpio->ports[0].gc.base + offs))
122 v &= ~BIT(offs);
123 else
124 v |= BIT(offs);
125
126 dwapb_write(gpio, GPIO_INT_POLARITY, v);
127}
128
129static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
130{
131 u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
132 u32 ret = irq_status;
133
134 while (irq_status) {
135 int hwirq = fls(irq_status) - 1;
136 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
137
138 generic_handle_irq(gpio_irq);
139 irq_status &= ~BIT(hwirq);
140
141 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
142 == IRQ_TYPE_EDGE_BOTH)
143 dwapb_toggle_trigger(gpio, hwirq);
144 }
145
146 return ret;
147}
148
149static void dwapb_irq_handler(struct irq_desc *desc)
150{
151 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
152 struct irq_chip *chip = irq_desc_get_chip(desc);
153
154 dwapb_do_irq(gpio);
155
156 if (chip->irq_eoi)
157 chip->irq_eoi(irq_desc_get_irq_data(desc));
158}
159
160static void dwapb_irq_enable(struct irq_data *d)
161{
162 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
163 struct dwapb_gpio *gpio = igc->private;
164 struct gpio_chip *gc = &gpio->ports[0].gc;
165 unsigned long flags;
166 u32 val;
167
168 spin_lock_irqsave(&gc->bgpio_lock, flags);
169 val = dwapb_read(gpio, GPIO_INTEN);
170 val |= BIT(d->hwirq);
171 dwapb_write(gpio, GPIO_INTEN, val);
172 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
173}
174
175static void dwapb_irq_disable(struct irq_data *d)
176{
177 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
178 struct dwapb_gpio *gpio = igc->private;
179 struct gpio_chip *gc = &gpio->ports[0].gc;
180 unsigned long flags;
181 u32 val;
182
183 spin_lock_irqsave(&gc->bgpio_lock, flags);
184 val = dwapb_read(gpio, GPIO_INTEN);
185 val &= ~BIT(d->hwirq);
186 dwapb_write(gpio, GPIO_INTEN, val);
187 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
188}
189
190static int dwapb_irq_reqres(struct irq_data *d)
191{
192 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
193 struct dwapb_gpio *gpio = igc->private;
194 struct gpio_chip *gc = &gpio->ports[0].gc;
195
196 if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) {
197 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
198 irqd_to_hwirq(d));
199 return -EINVAL;
200 }
201 return 0;
202}
203
204static void dwapb_irq_relres(struct irq_data *d)
205{
206 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
207 struct dwapb_gpio *gpio = igc->private;
208 struct gpio_chip *gc = &gpio->ports[0].gc;
209
210 gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
211}
212
213static int dwapb_irq_set_type(struct irq_data *d, u32 type)
214{
215 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
216 struct dwapb_gpio *gpio = igc->private;
217 struct gpio_chip *gc = &gpio->ports[0].gc;
218 int bit = d->hwirq;
219 unsigned long level, polarity, flags;
220
221 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
222 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
223 return -EINVAL;
224
225 spin_lock_irqsave(&gc->bgpio_lock, flags);
226 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
227 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
228
229 switch (type) {
230 case IRQ_TYPE_EDGE_BOTH:
231 level |= BIT(bit);
232 dwapb_toggle_trigger(gpio, bit);
233 break;
234 case IRQ_TYPE_EDGE_RISING:
235 level |= BIT(bit);
236 polarity |= BIT(bit);
237 break;
238 case IRQ_TYPE_EDGE_FALLING:
239 level |= BIT(bit);
240 polarity &= ~BIT(bit);
241 break;
242 case IRQ_TYPE_LEVEL_HIGH:
243 level &= ~BIT(bit);
244 polarity |= BIT(bit);
245 break;
246 case IRQ_TYPE_LEVEL_LOW:
247 level &= ~BIT(bit);
248 polarity &= ~BIT(bit);
249 break;
250 }
251
252 irq_setup_alt_chip(d, type);
253
254 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
255 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
256 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
257
258 return 0;
259}
260
261static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
262 unsigned offset, unsigned debounce)
263{
264 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
265 struct dwapb_gpio *gpio = port->gpio;
266 unsigned long flags, val_deb;
267 unsigned long mask = gc->pin2mask(gc, offset);
268
269 spin_lock_irqsave(&gc->bgpio_lock, flags);
270
271 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
272 if (debounce)
273 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
274 else
275 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
276
277 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
278
279 return 0;
280}
281
282static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
283{
284 u32 worked;
285 struct dwapb_gpio *gpio = dev_id;
286
287 worked = dwapb_do_irq(gpio);
288
289 return worked ? IRQ_HANDLED : IRQ_NONE;
290}
291
292static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
293 struct dwapb_gpio_port *port,
294 struct dwapb_port_property *pp)
295{
296 struct gpio_chip *gc = &port->gc;
297 struct fwnode_handle *fwnode = pp->fwnode;
298 struct irq_chip_generic *irq_gc = NULL;
299 unsigned int hwirq, ngpio = gc->ngpio;
300 struct irq_chip_type *ct;
301 int err, i;
302
303 gpio->domain = irq_domain_create_linear(fwnode, ngpio,
304 &irq_generic_chip_ops, gpio);
305 if (!gpio->domain)
306 return;
307
308 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
309 "gpio-dwapb", handle_level_irq,
310 IRQ_NOREQUEST, 0,
311 IRQ_GC_INIT_NESTED_LOCK);
312 if (err) {
313 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
314 irq_domain_remove(gpio->domain);
315 gpio->domain = NULL;
316 return;
317 }
318
319 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
320 if (!irq_gc) {
321 irq_domain_remove(gpio->domain);
322 gpio->domain = NULL;
323 return;
324 }
325
326 irq_gc->reg_base = gpio->regs;
327 irq_gc->private = gpio;
328
329 for (i = 0; i < 2; i++) {
330 ct = &irq_gc->chip_types[i];
331 ct->chip.irq_ack = irq_gc_ack_set_bit;
332 ct->chip.irq_mask = irq_gc_mask_set_bit;
333 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
334 ct->chip.irq_set_type = dwapb_irq_set_type;
335 ct->chip.irq_enable = dwapb_irq_enable;
336 ct->chip.irq_disable = dwapb_irq_disable;
337 ct->chip.irq_request_resources = dwapb_irq_reqres;
338 ct->chip.irq_release_resources = dwapb_irq_relres;
339 ct->regs.ack = GPIO_PORTA_EOI;
340 ct->regs.mask = GPIO_INTMASK;
341 ct->type = IRQ_TYPE_LEVEL_MASK;
342 }
343
344 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
345 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
346 irq_gc->chip_types[1].handler = handle_edge_irq;
347
348 if (!pp->irq_shared) {
349 irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler,
350 gpio);
351 } else {
352
353
354
355
356 err = devm_request_irq(gpio->dev, pp->irq,
357 dwapb_irq_handler_mfd,
358 IRQF_SHARED, "gpio-dwapb-mfd", gpio);
359 if (err) {
360 dev_err(gpio->dev, "error requesting IRQ\n");
361 irq_domain_remove(gpio->domain);
362 gpio->domain = NULL;
363 return;
364 }
365 }
366
367 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
368 irq_create_mapping(gpio->domain, hwirq);
369
370 port->gc.to_irq = dwapb_gpio_to_irq;
371}
372
373static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
374{
375 struct dwapb_gpio_port *port = &gpio->ports[0];
376 struct gpio_chip *gc = &port->gc;
377 unsigned int ngpio = gc->ngpio;
378 irq_hw_number_t hwirq;
379
380 if (!gpio->domain)
381 return;
382
383 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
384 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
385
386 irq_domain_remove(gpio->domain);
387 gpio->domain = NULL;
388}
389
390static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
391 struct dwapb_port_property *pp,
392 unsigned int offs)
393{
394 struct dwapb_gpio_port *port;
395 void __iomem *dat, *set, *dirout;
396 int err;
397
398 port = &gpio->ports[offs];
399 port->gpio = gpio;
400 port->idx = pp->idx;
401
402#ifdef CONFIG_PM_SLEEP
403 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
404 if (!port->ctx)
405 return -ENOMEM;
406#endif
407
408 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
409 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
410 dirout = gpio->regs + GPIO_SWPORTA_DDR +
411 (pp->idx * GPIO_SWPORT_DDR_SIZE);
412
413 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
414 NULL, false);
415 if (err) {
416 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
417 port->idx);
418 return err;
419 }
420
421#ifdef CONFIG_OF_GPIO
422 port->gc.of_node = to_of_node(pp->fwnode);
423#endif
424 port->gc.ngpio = pp->ngpio;
425 port->gc.base = pp->gpio_base;
426
427
428 if (pp->idx == 0)
429 port->gc.set_debounce = dwapb_gpio_set_debounce;
430
431 if (pp->irq)
432 dwapb_configure_irqs(gpio, port, pp);
433
434 err = gpiochip_add_data(&port->gc, port);
435 if (err)
436 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
437 port->idx);
438 else
439 port->is_registered = true;
440
441
442 if (pp->irq)
443 acpi_gpiochip_request_interrupts(&port->gc);
444
445 return err;
446}
447
448static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
449{
450 unsigned int m;
451
452 for (m = 0; m < gpio->nr_ports; ++m)
453 if (gpio->ports[m].is_registered)
454 gpiochip_remove(&gpio->ports[m].gc);
455}
456
457static struct dwapb_platform_data *
458dwapb_gpio_get_pdata(struct device *dev)
459{
460 struct fwnode_handle *fwnode;
461 struct dwapb_platform_data *pdata;
462 struct dwapb_port_property *pp;
463 int nports;
464 int i;
465
466 nports = device_get_child_node_count(dev);
467 if (nports == 0)
468 return ERR_PTR(-ENODEV);
469
470 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
471 if (!pdata)
472 return ERR_PTR(-ENOMEM);
473
474 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
475 if (!pdata->properties)
476 return ERR_PTR(-ENOMEM);
477
478 pdata->nports = nports;
479
480 i = 0;
481 device_for_each_child_node(dev, fwnode) {
482 pp = &pdata->properties[i++];
483 pp->fwnode = fwnode;
484
485 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
486 pp->idx >= DWAPB_MAX_PORTS) {
487 dev_err(dev,
488 "missing/invalid port index for port%d\n", i);
489 fwnode_handle_put(fwnode);
490 return ERR_PTR(-EINVAL);
491 }
492
493 if (fwnode_property_read_u32(fwnode, "snps,nr-gpios",
494 &pp->ngpio)) {
495 dev_info(dev,
496 "failed to get number of gpios for port%d\n",
497 i);
498 pp->ngpio = 32;
499 }
500
501
502
503
504
505 if (dev->of_node && pp->idx == 0 &&
506 fwnode_property_read_bool(fwnode,
507 "interrupt-controller")) {
508 pp->irq = irq_of_parse_and_map(to_of_node(fwnode), 0);
509 if (!pp->irq)
510 dev_warn(dev, "no irq for port%d\n", pp->idx);
511 }
512
513 if (has_acpi_companion(dev) && pp->idx == 0)
514 pp->irq = platform_get_irq(to_platform_device(dev), 0);
515
516 pp->irq_shared = false;
517 pp->gpio_base = -1;
518 }
519
520 return pdata;
521}
522
523static int dwapb_gpio_probe(struct platform_device *pdev)
524{
525 unsigned int i;
526 struct resource *res;
527 struct dwapb_gpio *gpio;
528 int err;
529 struct device *dev = &pdev->dev;
530 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
531
532 if (!pdata) {
533 pdata = dwapb_gpio_get_pdata(dev);
534 if (IS_ERR(pdata))
535 return PTR_ERR(pdata);
536 }
537
538 if (!pdata->nports)
539 return -ENODEV;
540
541 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
542 if (!gpio)
543 return -ENOMEM;
544
545 gpio->dev = &pdev->dev;
546 gpio->nr_ports = pdata->nports;
547
548 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
549 sizeof(*gpio->ports), GFP_KERNEL);
550 if (!gpio->ports)
551 return -ENOMEM;
552
553 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
554 gpio->regs = devm_ioremap_resource(&pdev->dev, res);
555 if (IS_ERR(gpio->regs))
556 return PTR_ERR(gpio->regs);
557
558 for (i = 0; i < gpio->nr_ports; i++) {
559 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
560 if (err)
561 goto out_unregister;
562 }
563 platform_set_drvdata(pdev, gpio);
564
565 return 0;
566
567out_unregister:
568 dwapb_gpio_unregister(gpio);
569 dwapb_irq_teardown(gpio);
570
571 return err;
572}
573
574static int dwapb_gpio_remove(struct platform_device *pdev)
575{
576 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
577
578 dwapb_gpio_unregister(gpio);
579 dwapb_irq_teardown(gpio);
580
581 return 0;
582}
583
584static const struct of_device_id dwapb_of_match[] = {
585 { .compatible = "snps,dw-apb-gpio" },
586 { }
587};
588MODULE_DEVICE_TABLE(of, dwapb_of_match);
589
590static const struct acpi_device_id dwapb_acpi_match[] = {
591 {"HISI0181", 0},
592 {"APMC0D07", 0},
593 { }
594};
595MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
596
597#ifdef CONFIG_PM_SLEEP
598static int dwapb_gpio_suspend(struct device *dev)
599{
600 struct platform_device *pdev = to_platform_device(dev);
601 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
602 struct gpio_chip *gc = &gpio->ports[0].gc;
603 unsigned long flags;
604 int i;
605
606 spin_lock_irqsave(&gc->bgpio_lock, flags);
607 for (i = 0; i < gpio->nr_ports; i++) {
608 unsigned int offset;
609 unsigned int idx = gpio->ports[i].idx;
610 struct dwapb_context *ctx = gpio->ports[i].ctx;
611
612 BUG_ON(!ctx);
613
614 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
615 ctx->dir = dwapb_read(gpio, offset);
616
617 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
618 ctx->data = dwapb_read(gpio, offset);
619
620 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
621 ctx->ext = dwapb_read(gpio, offset);
622
623
624 if (idx == 0) {
625 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
626 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
627 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
628 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
629 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
630
631
632 dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
633 }
634 }
635 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
636
637 return 0;
638}
639
640static int dwapb_gpio_resume(struct device *dev)
641{
642 struct platform_device *pdev = to_platform_device(dev);
643 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
644 struct gpio_chip *gc = &gpio->ports[0].gc;
645 unsigned long flags;
646 int i;
647
648 spin_lock_irqsave(&gc->bgpio_lock, flags);
649 for (i = 0; i < gpio->nr_ports; i++) {
650 unsigned int offset;
651 unsigned int idx = gpio->ports[i].idx;
652 struct dwapb_context *ctx = gpio->ports[i].ctx;
653
654 BUG_ON(!ctx);
655
656 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
657 dwapb_write(gpio, offset, ctx->data);
658
659 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
660 dwapb_write(gpio, offset, ctx->dir);
661
662 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
663 dwapb_write(gpio, offset, ctx->ext);
664
665
666 if (idx == 0) {
667 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
668 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
669 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
670 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
671 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
672
673
674 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
675 }
676 }
677 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
678
679 return 0;
680}
681#endif
682
683static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
684 dwapb_gpio_resume);
685
686static struct platform_driver dwapb_gpio_driver = {
687 .driver = {
688 .name = "gpio-dwapb",
689 .pm = &dwapb_gpio_pm_ops,
690 .of_match_table = of_match_ptr(dwapb_of_match),
691 .acpi_match_table = ACPI_PTR(dwapb_acpi_match),
692 },
693 .probe = dwapb_gpio_probe,
694 .remove = dwapb_gpio_remove,
695};
696
697module_platform_driver(dwapb_gpio_driver);
698
699MODULE_LICENSE("GPL");
700MODULE_AUTHOR("Jamie Iles");
701MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
702
