linux/drivers/gpio/gpio-pl061.c
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   1/*
   2 * Copyright (C) 2008, 2009 Provigent Ltd.
   3 *
   4 * Author: Baruch Siach <baruch@tkos.co.il>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 *
  10 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
  11 *
  12 * Data sheet: ARM DDI 0190B, September 2000
  13 */
  14#include <linux/spinlock.h>
  15#include <linux/errno.h>
  16#include <linux/init.h>
  17#include <linux/io.h>
  18#include <linux/ioport.h>
  19#include <linux/interrupt.h>
  20#include <linux/irq.h>
  21#include <linux/irqchip/chained_irq.h>
  22#include <linux/bitops.h>
  23#include <linux/gpio.h>
  24#include <linux/device.h>
  25#include <linux/amba/bus.h>
  26#include <linux/amba/pl061.h>
  27#include <linux/slab.h>
  28#include <linux/pinctrl/consumer.h>
  29#include <linux/pm.h>
  30
  31#define GPIODIR 0x400
  32#define GPIOIS  0x404
  33#define GPIOIBE 0x408
  34#define GPIOIEV 0x40C
  35#define GPIOIE  0x410
  36#define GPIORIS 0x414
  37#define GPIOMIS 0x418
  38#define GPIOIC  0x41C
  39
  40#define PL061_GPIO_NR   8
  41
  42#ifdef CONFIG_PM
  43struct pl061_context_save_regs {
  44        u8 gpio_data;
  45        u8 gpio_dir;
  46        u8 gpio_is;
  47        u8 gpio_ibe;
  48        u8 gpio_iev;
  49        u8 gpio_ie;
  50};
  51#endif
  52
  53struct pl061_gpio {
  54        spinlock_t              lock;
  55
  56        void __iomem            *base;
  57        struct gpio_chip        gc;
  58
  59#ifdef CONFIG_PM
  60        struct pl061_context_save_regs csave_regs;
  61#endif
  62};
  63
  64static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
  65{
  66        struct pl061_gpio *chip = gpiochip_get_data(gc);
  67
  68        return !(readb(chip->base + GPIODIR) & BIT(offset));
  69}
  70
  71static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
  72{
  73        struct pl061_gpio *chip = gpiochip_get_data(gc);
  74        unsigned long flags;
  75        unsigned char gpiodir;
  76
  77        spin_lock_irqsave(&chip->lock, flags);
  78        gpiodir = readb(chip->base + GPIODIR);
  79        gpiodir &= ~(BIT(offset));
  80        writeb(gpiodir, chip->base + GPIODIR);
  81        spin_unlock_irqrestore(&chip->lock, flags);
  82
  83        return 0;
  84}
  85
  86static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
  87                int value)
  88{
  89        struct pl061_gpio *chip = gpiochip_get_data(gc);
  90        unsigned long flags;
  91        unsigned char gpiodir;
  92
  93        spin_lock_irqsave(&chip->lock, flags);
  94        writeb(!!value << offset, chip->base + (BIT(offset + 2)));
  95        gpiodir = readb(chip->base + GPIODIR);
  96        gpiodir |= BIT(offset);
  97        writeb(gpiodir, chip->base + GPIODIR);
  98
  99        /*
 100         * gpio value is set again, because pl061 doesn't allow to set value of
 101         * a gpio pin before configuring it in OUT mode.
 102         */
 103        writeb(!!value << offset, chip->base + (BIT(offset + 2)));
 104        spin_unlock_irqrestore(&chip->lock, flags);
 105
 106        return 0;
 107}
 108
 109static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
 110{
 111        struct pl061_gpio *chip = gpiochip_get_data(gc);
 112
 113        return !!readb(chip->base + (BIT(offset + 2)));
 114}
 115
 116static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
 117{
 118        struct pl061_gpio *chip = gpiochip_get_data(gc);
 119
 120        writeb(!!value << offset, chip->base + (BIT(offset + 2)));
 121}
 122
 123static int pl061_irq_type(struct irq_data *d, unsigned trigger)
 124{
 125        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 126        struct pl061_gpio *chip = gpiochip_get_data(gc);
 127        int offset = irqd_to_hwirq(d);
 128        unsigned long flags;
 129        u8 gpiois, gpioibe, gpioiev;
 130        u8 bit = BIT(offset);
 131
 132        if (offset < 0 || offset >= PL061_GPIO_NR)
 133                return -EINVAL;
 134
 135        if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
 136            (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
 137        {
 138                dev_err(gc->parent,
 139                        "trying to configure line %d for both level and edge "
 140                        "detection, choose one!\n",
 141                        offset);
 142                return -EINVAL;
 143        }
 144
 145
 146        spin_lock_irqsave(&chip->lock, flags);
 147
 148        gpioiev = readb(chip->base + GPIOIEV);
 149        gpiois = readb(chip->base + GPIOIS);
 150        gpioibe = readb(chip->base + GPIOIBE);
 151
 152        if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 153                bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
 154
 155                /* Disable edge detection */
 156                gpioibe &= ~bit;
 157                /* Enable level detection */
 158                gpiois |= bit;
 159                /* Select polarity */
 160                if (polarity)
 161                        gpioiev |= bit;
 162                else
 163                        gpioiev &= ~bit;
 164                irq_set_handler_locked(d, handle_level_irq);
 165                dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
 166                        offset,
 167                        polarity ? "HIGH" : "LOW");
 168        } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 169                /* Disable level detection */
 170                gpiois &= ~bit;
 171                /* Select both edges, setting this makes GPIOEV be ignored */
 172                gpioibe |= bit;
 173                irq_set_handler_locked(d, handle_edge_irq);
 174                dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
 175        } else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
 176                   (trigger & IRQ_TYPE_EDGE_FALLING)) {
 177                bool rising = trigger & IRQ_TYPE_EDGE_RISING;
 178
 179                /* Disable level detection */
 180                gpiois &= ~bit;
 181                /* Clear detection on both edges */
 182                gpioibe &= ~bit;
 183                /* Select edge */
 184                if (rising)
 185                        gpioiev |= bit;
 186                else
 187                        gpioiev &= ~bit;
 188                irq_set_handler_locked(d, handle_edge_irq);
 189                dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
 190                        offset,
 191                        rising ? "RISING" : "FALLING");
 192        } else {
 193                /* No trigger: disable everything */
 194                gpiois &= ~bit;
 195                gpioibe &= ~bit;
 196                gpioiev &= ~bit;
 197                irq_set_handler_locked(d, handle_bad_irq);
 198                dev_warn(gc->parent, "no trigger selected for line %d\n",
 199                         offset);
 200        }
 201
 202        writeb(gpiois, chip->base + GPIOIS);
 203        writeb(gpioibe, chip->base + GPIOIBE);
 204        writeb(gpioiev, chip->base + GPIOIEV);
 205
 206        spin_unlock_irqrestore(&chip->lock, flags);
 207
 208        return 0;
 209}
 210
 211static void pl061_irq_handler(struct irq_desc *desc)
 212{
 213        unsigned long pending;
 214        int offset;
 215        struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 216        struct pl061_gpio *chip = gpiochip_get_data(gc);
 217        struct irq_chip *irqchip = irq_desc_get_chip(desc);
 218
 219        chained_irq_enter(irqchip, desc);
 220
 221        pending = readb(chip->base + GPIOMIS);
 222        if (pending) {
 223                for_each_set_bit(offset, &pending, PL061_GPIO_NR)
 224                        generic_handle_irq(irq_find_mapping(gc->irqdomain,
 225                                                            offset));
 226        }
 227
 228        chained_irq_exit(irqchip, desc);
 229}
 230
 231static void pl061_irq_mask(struct irq_data *d)
 232{
 233        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 234        struct pl061_gpio *chip = gpiochip_get_data(gc);
 235        u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
 236        u8 gpioie;
 237
 238        spin_lock(&chip->lock);
 239        gpioie = readb(chip->base + GPIOIE) & ~mask;
 240        writeb(gpioie, chip->base + GPIOIE);
 241        spin_unlock(&chip->lock);
 242}
 243
 244static void pl061_irq_unmask(struct irq_data *d)
 245{
 246        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 247        struct pl061_gpio *chip = gpiochip_get_data(gc);
 248        u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
 249        u8 gpioie;
 250
 251        spin_lock(&chip->lock);
 252        gpioie = readb(chip->base + GPIOIE) | mask;
 253        writeb(gpioie, chip->base + GPIOIE);
 254        spin_unlock(&chip->lock);
 255}
 256
 257/**
 258 * pl061_irq_ack() - ACK an edge IRQ
 259 * @d: IRQ data for this IRQ
 260 *
 261 * This gets called from the edge IRQ handler to ACK the edge IRQ
 262 * in the GPIOIC (interrupt-clear) register. For level IRQs this is
 263 * not needed: these go away when the level signal goes away.
 264 */
 265static void pl061_irq_ack(struct irq_data *d)
 266{
 267        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 268        struct pl061_gpio *chip = gpiochip_get_data(gc);
 269        u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
 270
 271        spin_lock(&chip->lock);
 272        writeb(mask, chip->base + GPIOIC);
 273        spin_unlock(&chip->lock);
 274}
 275
 276static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
 277{
 278        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 279
 280        return irq_set_irq_wake(gc->irq_parent, state);
 281}
 282
 283static struct irq_chip pl061_irqchip = {
 284        .name           = "pl061",
 285        .irq_ack        = pl061_irq_ack,
 286        .irq_mask       = pl061_irq_mask,
 287        .irq_unmask     = pl061_irq_unmask,
 288        .irq_set_type   = pl061_irq_type,
 289        .irq_set_wake   = pl061_irq_set_wake,
 290};
 291
 292static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
 293{
 294        struct device *dev = &adev->dev;
 295        struct pl061_platform_data *pdata = dev_get_platdata(dev);
 296        struct pl061_gpio *chip;
 297        int ret, irq, i, irq_base;
 298
 299        chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
 300        if (chip == NULL)
 301                return -ENOMEM;
 302
 303        if (pdata) {
 304                chip->gc.base = pdata->gpio_base;
 305                irq_base = pdata->irq_base;
 306                if (irq_base <= 0) {
 307                        dev_err(&adev->dev, "invalid IRQ base in pdata\n");
 308                        return -ENODEV;
 309                }
 310        } else {
 311                chip->gc.base = -1;
 312                irq_base = 0;
 313        }
 314
 315        chip->base = devm_ioremap_resource(dev, &adev->res);
 316        if (IS_ERR(chip->base))
 317                return PTR_ERR(chip->base);
 318
 319        spin_lock_init(&chip->lock);
 320        if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
 321                chip->gc.request = gpiochip_generic_request;
 322                chip->gc.free = gpiochip_generic_free;
 323        }
 324
 325        chip->gc.get_direction = pl061_get_direction;
 326        chip->gc.direction_input = pl061_direction_input;
 327        chip->gc.direction_output = pl061_direction_output;
 328        chip->gc.get = pl061_get_value;
 329        chip->gc.set = pl061_set_value;
 330        chip->gc.ngpio = PL061_GPIO_NR;
 331        chip->gc.label = dev_name(dev);
 332        chip->gc.parent = dev;
 333        chip->gc.owner = THIS_MODULE;
 334
 335        ret = gpiochip_add_data(&chip->gc, chip);
 336        if (ret)
 337                return ret;
 338
 339        /*
 340         * irq_chip support
 341         */
 342        writeb(0, chip->base + GPIOIE); /* disable irqs */
 343        irq = adev->irq[0];
 344        if (irq < 0) {
 345                dev_err(&adev->dev, "invalid IRQ\n");
 346                return -ENODEV;
 347        }
 348
 349        ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
 350                                   irq_base, handle_bad_irq,
 351                                   IRQ_TYPE_NONE);
 352        if (ret) {
 353                dev_info(&adev->dev, "could not add irqchip\n");
 354                return ret;
 355        }
 356        gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
 357                                     irq, pl061_irq_handler);
 358
 359        for (i = 0; i < PL061_GPIO_NR; i++) {
 360                if (pdata) {
 361                        if (pdata->directions & (BIT(i)))
 362                                pl061_direction_output(&chip->gc, i,
 363                                                pdata->values & (BIT(i)));
 364                        else
 365                                pl061_direction_input(&chip->gc, i);
 366                }
 367        }
 368
 369        amba_set_drvdata(adev, chip);
 370        dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
 371                 &adev->res.start);
 372
 373        return 0;
 374}
 375
 376#ifdef CONFIG_PM
 377static int pl061_suspend(struct device *dev)
 378{
 379        struct pl061_gpio *chip = dev_get_drvdata(dev);
 380        int offset;
 381
 382        chip->csave_regs.gpio_data = 0;
 383        chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
 384        chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
 385        chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
 386        chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
 387        chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
 388
 389        for (offset = 0; offset < PL061_GPIO_NR; offset++) {
 390                if (chip->csave_regs.gpio_dir & (BIT(offset)))
 391                        chip->csave_regs.gpio_data |=
 392                                pl061_get_value(&chip->gc, offset) << offset;
 393        }
 394
 395        return 0;
 396}
 397
 398static int pl061_resume(struct device *dev)
 399{
 400        struct pl061_gpio *chip = dev_get_drvdata(dev);
 401        int offset;
 402
 403        for (offset = 0; offset < PL061_GPIO_NR; offset++) {
 404                if (chip->csave_regs.gpio_dir & (BIT(offset)))
 405                        pl061_direction_output(&chip->gc, offset,
 406                                        chip->csave_regs.gpio_data &
 407                                        (BIT(offset)));
 408                else
 409                        pl061_direction_input(&chip->gc, offset);
 410        }
 411
 412        writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
 413        writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
 414        writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
 415        writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
 416
 417        return 0;
 418}
 419
 420static const struct dev_pm_ops pl061_dev_pm_ops = {
 421        .suspend = pl061_suspend,
 422        .resume = pl061_resume,
 423        .freeze = pl061_suspend,
 424        .restore = pl061_resume,
 425};
 426#endif
 427
 428static struct amba_id pl061_ids[] = {
 429        {
 430                .id     = 0x00041061,
 431                .mask   = 0x000fffff,
 432        },
 433        { 0, 0 },
 434};
 435
 436static struct amba_driver pl061_gpio_driver = {
 437        .drv = {
 438                .name   = "pl061_gpio",
 439#ifdef CONFIG_PM
 440                .pm     = &pl061_dev_pm_ops,
 441#endif
 442        },
 443        .id_table       = pl061_ids,
 444        .probe          = pl061_probe,
 445};
 446
 447static int __init pl061_gpio_init(void)
 448{
 449        return amba_driver_register(&pl061_gpio_driver);
 450}
 451device_initcall(pl061_gpio_init);
 452