LXR linux/drivers/gpio/gpio-zynq.c

   1/*
   2 * Xilinx Zynq GPIO device driver
   3 *
   4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it under
   7 * the terms of the GNU General Public License as published by the Free Software
   8 * Foundation; either version 2 of the License, or (at your option) any later
   9 * version.
  10 */
  11
  12#include <linux/bitops.h>
  13#include <linux/clk.h>
  14#include <linux/gpio/driver.h>
  15#include <linux/init.h>
  16#include <linux/interrupt.h>
  17#include <linux/io.h>
  18#include <linux/module.h>
  19#include <linux/platform_device.h>
  20#include <linux/pm_runtime.h>
  21#include <linux/of.h>
  22
  23#define DRIVER_NAME "zynq-gpio"
  24
  25/* Maximum banks */
  26#define ZYNQ_GPIO_MAX_BANK      4
  27#define ZYNQMP_GPIO_MAX_BANK    6
  28
  29#define ZYNQ_GPIO_BANK0_NGPIO   32
  30#define ZYNQ_GPIO_BANK1_NGPIO   22
  31#define ZYNQ_GPIO_BANK2_NGPIO   32
  32#define ZYNQ_GPIO_BANK3_NGPIO   32
  33
  34#define ZYNQMP_GPIO_BANK0_NGPIO 26
  35#define ZYNQMP_GPIO_BANK1_NGPIO 26
  36#define ZYNQMP_GPIO_BANK2_NGPIO 26
  37#define ZYNQMP_GPIO_BANK3_NGPIO 32
  38#define ZYNQMP_GPIO_BANK4_NGPIO 32
  39#define ZYNQMP_GPIO_BANK5_NGPIO 32
  40
  41#define ZYNQ_GPIO_NR_GPIOS      118
  42#define ZYNQMP_GPIO_NR_GPIOS    174
  43
  44#define ZYNQ_GPIO_BANK0_PIN_MIN(str)    0
  45#define ZYNQ_GPIO_BANK0_PIN_MAX(str)    (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
  46                                        ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
  47#define ZYNQ_GPIO_BANK1_PIN_MIN(str)    (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
  48#define ZYNQ_GPIO_BANK1_PIN_MAX(str)    (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
  49                                        ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
  50#define ZYNQ_GPIO_BANK2_PIN_MIN(str)    (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
  51#define ZYNQ_GPIO_BANK2_PIN_MAX(str)    (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
  52                                        ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
  53#define ZYNQ_GPIO_BANK3_PIN_MIN(str)    (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
  54#define ZYNQ_GPIO_BANK3_PIN_MAX(str)    (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
  55                                        ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
  56#define ZYNQ_GPIO_BANK4_PIN_MIN(str)    (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
  57#define ZYNQ_GPIO_BANK4_PIN_MAX(str)    (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
  58                                        ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
  59#define ZYNQ_GPIO_BANK5_PIN_MIN(str)    (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
  60#define ZYNQ_GPIO_BANK5_PIN_MAX(str)    (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
  61                                        ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
  62
  63
  64/* Register offsets for the GPIO device */
  65/* LSW Mask & Data -WO */
  66#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
  67/* MSW Mask & Data -WO */
  68#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
  69/* Data Register-RW */
  70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)  (0x060 + (4 * BANK))
  71/* Direction mode reg-RW */
  72#define ZYNQ_GPIO_DIRM_OFFSET(BANK)     (0x204 + (0x40 * BANK))
  73/* Output enable reg-RW */
  74#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)    (0x208 + (0x40 * BANK))
  75/* Interrupt mask reg-RO */
  76#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)  (0x20C + (0x40 * BANK))
  77/* Interrupt enable reg-WO */
  78#define ZYNQ_GPIO_INTEN_OFFSET(BANK)    (0x210 + (0x40 * BANK))
  79/* Interrupt disable reg-WO */
  80#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)   (0x214 + (0x40 * BANK))
  81/* Interrupt status reg-RO */
  82#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)   (0x218 + (0x40 * BANK))
  83/* Interrupt type reg-RW */
  84#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)  (0x21C + (0x40 * BANK))
  85/* Interrupt polarity reg-RW */
  86#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)   (0x220 + (0x40 * BANK))
  87/* Interrupt on any, reg-RW */
  88#define ZYNQ_GPIO_INTANY_OFFSET(BANK)   (0x224 + (0x40 * BANK))
  89
  90/* Disable all interrupts mask */
  91#define ZYNQ_GPIO_IXR_DISABLE_ALL       0xFFFFFFFF
  92
  93/* Mid pin number of a bank */
  94#define ZYNQ_GPIO_MID_PIN_NUM 16
  95
  96/* GPIO upper 16 bit mask */
  97#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
  98
  99/**
 100 * struct zynq_gpio - gpio device private data structure
 101 * @chip:       instance of the gpio_chip
 102 * @base_addr:  base address of the GPIO device
 103 * @clk:        clock resource for this controller
 104 * @irq:        interrupt for the GPIO device
 105 * @p_data:     pointer to platform data
 106 */
 107struct zynq_gpio {
 108        struct gpio_chip chip;
 109        void __iomem *base_addr;
 110        struct clk *clk;
 111        int irq;
 112        const struct zynq_platform_data *p_data;
 113};
 114
 115/**
 116 * struct zynq_platform_data -  zynq gpio platform data structure
 117 * @label:      string to store in gpio->label
 118 * @ngpio:      max number of gpio pins
 119 * @max_bank:   maximum number of gpio banks
 120 * @bank_min:   this array represents bank's min pin
 121 * @bank_max:   this array represents bank's max pin
 122*/
 123struct zynq_platform_data {
 124        const char *label;
 125        u16 ngpio;
 126        int max_bank;
 127        int bank_min[ZYNQMP_GPIO_MAX_BANK];
 128        int bank_max[ZYNQMP_GPIO_MAX_BANK];
 129};
 130
 131static struct irq_chip zynq_gpio_level_irqchip;
 132static struct irq_chip zynq_gpio_edge_irqchip;
 133
 134/**
 135 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
 136 * for a given pin in the GPIO device
 137 * @pin_num:    gpio pin number within the device
 138 * @bank_num:   an output parameter used to return the bank number of the gpio
 139 *              pin
 140 * @bank_pin_num: an output parameter used to return pin number within a bank
 141 *                for the given gpio pin
 142 *
 143 * Returns the bank number and pin offset within the bank.
 144 */
 145static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
 146                                          unsigned int *bank_num,
 147                                          unsigned int *bank_pin_num,
 148                                          struct zynq_gpio *gpio)
 149{
 150        int bank;
 151
 152        for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
 153                if ((pin_num >= gpio->p_data->bank_min[bank]) &&
 154                        (pin_num <= gpio->p_data->bank_max[bank])) {
 155                                *bank_num = bank;
 156                                *bank_pin_num = pin_num -
 157                                                gpio->p_data->bank_min[bank];
 158                                return;
 159                }
 160        }
 161
 162        /* default */
 163        WARN(true, "invalid GPIO pin number: %u", pin_num);
 164        *bank_num = 0;
 165        *bank_pin_num = 0;
 166}
 167
 168/**
 169 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
 170 * @chip:       gpio_chip instance to be worked on
 171 * @pin:        gpio pin number within the device
 172 *
 173 * This function reads the state of the specified pin of the GPIO device.
 174 *
 175 * Return: 0 if the pin is low, 1 if pin is high.
 176 */
 177static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
 178{
 179        u32 data;
 180        unsigned int bank_num, bank_pin_num;
 181        struct zynq_gpio *gpio = gpiochip_get_data(chip);
 182
 183        zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 184
 185        data = readl_relaxed(gpio->base_addr +
 186                             ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
 187
 188        return (data >> bank_pin_num) & 1;
 189}
 190
 191/**
 192 * zynq_gpio_set_value - Modify the state of the pin with specified value
 193 * @chip:       gpio_chip instance to be worked on
 194 * @pin:        gpio pin number within the device
 195 * @state:      value used to modify the state of the specified pin
 196 *
 197 * This function calculates the register offset (i.e to lower 16 bits or
 198 * upper 16 bits) based on the given pin number and sets the state of a
 199 * gpio pin to the specified value. The state is either 0 or non-zero.
 200 */
 201static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
 202                                int state)
 203{
 204        unsigned int reg_offset, bank_num, bank_pin_num;
 205        struct zynq_gpio *gpio = gpiochip_get_data(chip);
 206
 207        zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 208
 209        if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
 210                /* only 16 data bits in bit maskable reg */
 211                bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
 212                reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
 213        } else {
 214                reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
 215        }
 216
 217        /*
 218         * get the 32 bit value to be written to the mask/data register where
 219         * the upper 16 bits is the mask and lower 16 bits is the data
 220         */
 221        state = !!state;
 222        state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
 223                ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
 224
 225        writel_relaxed(state, gpio->base_addr + reg_offset);
 226}
 227
 228/**
 229 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
 230 * @chip:       gpio_chip instance to be worked on
 231 * @pin:        gpio pin number within the device
 232 *
 233 * This function uses the read-modify-write sequence to set the direction of
 234 * the gpio pin as input.
 235 *
 236 * Return: 0 always
 237 */
 238static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
 239{
 240        u32 reg;
 241        unsigned int bank_num, bank_pin_num;
 242        struct zynq_gpio *gpio = gpiochip_get_data(chip);
 243
 244        zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 245
 246        /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
 247        if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
 248                return -EINVAL;
 249
 250        /* clear the bit in direction mode reg to set the pin as input */
 251        reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 252        reg &= ~BIT(bank_pin_num);
 253        writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 254
 255        return 0;
 256}
 257
 258/**
 259 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
 260 * @chip:       gpio_chip instance to be worked on
 261 * @pin:        gpio pin number within the device
 262 * @state:      value to be written to specified pin
 263 *
 264 * This function sets the direction of specified GPIO pin as output, configures
 265 * the Output Enable register for the pin and uses zynq_gpio_set to set
 266 * the state of the pin to the value specified.
 267 *
 268 * Return: 0 always
 269 */
 270static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
 271                             int state)
 272{
 273        u32 reg;
 274        unsigned int bank_num, bank_pin_num;
 275        struct zynq_gpio *gpio = gpiochip_get_data(chip);
 276
 277        zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 278
 279        /* set the GPIO pin as output */
 280        reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 281        reg |= BIT(bank_pin_num);
 282        writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 283
 284        /* configure the output enable reg for the pin */
 285        reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
 286        reg |= BIT(bank_pin_num);
 287        writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
 288
 289        /* set the state of the pin */
 290        zynq_gpio_set_value(chip, pin, state);
 291        return 0;
 292}
 293
 294/**
 295 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
 296 * @irq_data:   per irq and chip data passed down to chip functions
 297 *
 298 * This function calculates gpio pin number from irq number and sets the
 299 * bit in the Interrupt Disable register of the corresponding bank to disable
 300 * interrupts for that pin.
 301 */
 302static void zynq_gpio_irq_mask(struct irq_data *irq_data)
 303{
 304        unsigned int device_pin_num, bank_num, bank_pin_num;
 305        struct zynq_gpio *gpio =
 306                gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
 307
 308        device_pin_num = irq_data->hwirq;
 309        zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 310        writel_relaxed(BIT(bank_pin_num),
 311                       gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
 312}
 313
 314/**
 315 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
 316 * @irq_data:   irq data containing irq number of gpio pin for the interrupt
 317 *              to enable
 318 *
 319 * This function calculates the gpio pin number from irq number and sets the
 320 * bit in the Interrupt Enable register of the corresponding bank to enable
 321 * interrupts for that pin.
 322 */
 323static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
 324{
 325        unsigned int device_pin_num, bank_num, bank_pin_num;
 326        struct zynq_gpio *gpio =
 327                gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
 328
 329        device_pin_num = irq_data->hwirq;
 330        zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 331        writel_relaxed(BIT(bank_pin_num),
 332                       gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
 333}
 334
 335/**
 336 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
 337 * @irq_data:   irq data containing irq number of gpio pin for the interrupt
 338 *              to ack
 339 *
 340 * This function calculates gpio pin number from irq number and sets the bit
 341 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
 342 */
 343static void zynq_gpio_irq_ack(struct irq_data *irq_data)
 344{
 345        unsigned int device_pin_num, bank_num, bank_pin_num;
 346        struct zynq_gpio *gpio =
 347                gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
 348
 349        device_pin_num = irq_data->hwirq;
 350        zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 351        writel_relaxed(BIT(bank_pin_num),
 352                       gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
 353}
 354
 355/**
 356 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
 357 * @irq_data:   irq data containing irq number of gpio pin for the interrupt
 358 *              to enable
 359 *
 360 * Clears the INTSTS bit and unmasks the given interrupt.
 361 */
 362static void zynq_gpio_irq_enable(struct irq_data *irq_data)
 363{
 364        /*
 365         * The Zynq GPIO controller does not disable interrupt detection when
 366         * the interrupt is masked and only disables the propagation of the
 367         * interrupt. This means when the controller detects an interrupt
 368         * condition while the interrupt is logically disabled it will propagate
 369         * that interrupt event once the interrupt is enabled. This will cause
 370         * the interrupt consumer to see spurious interrupts to prevent this
 371         * first make sure that the interrupt is not asserted and then enable
 372         * it.
 373         */
 374        zynq_gpio_irq_ack(irq_data);
 375        zynq_gpio_irq_unmask(irq_data);
 376}
 377
 378/**
 379 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
 380 * @irq_data:   irq data containing irq number of gpio pin
 381 * @type:       interrupt type that is to be set for the gpio pin
 382 *
 383 * This function gets the gpio pin number and its bank from the gpio pin number
 384 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
 385 *
 386 * Return: 0, negative error otherwise.
 387 * TYPE-EDGE_RISING,  INT_TYPE - 1, INT_POLARITY - 1,  INT_ANY - 0;
 388 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0,  INT_ANY - 0;
 389 * TYPE-EDGE_BOTH,    INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
 390 * TYPE-LEVEL_HIGH,   INT_TYPE - 0, INT_POLARITY - 1,  INT_ANY - NA;
 391 * TYPE-LEVEL_LOW,    INT_TYPE - 0, INT_POLARITY - 0,  INT_ANY - NA
 392 */
 393static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
 394{
 395        u32 int_type, int_pol, int_any;
 396        unsigned int device_pin_num, bank_num, bank_pin_num;
 397        struct zynq_gpio *gpio =
 398                gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
 399
 400        device_pin_num = irq_data->hwirq;
 401        zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 402
 403        int_type = readl_relaxed(gpio->base_addr +
 404                                 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
 405        int_pol = readl_relaxed(gpio->base_addr +
 406                                ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
 407        int_any = readl_relaxed(gpio->base_addr +
 408                                ZYNQ_GPIO_INTANY_OFFSET(bank_num));
 409
 410        /*
 411         * based on the type requested, configure the INT_TYPE, INT_POLARITY
 412         * and INT_ANY registers
 413         */
 414        switch (type) {
 415        case IRQ_TYPE_EDGE_RISING:
 416                int_type |= BIT(bank_pin_num);
 417                int_pol |= BIT(bank_pin_num);
 418                int_any &= ~BIT(bank_pin_num);
 419                break;
 420        case IRQ_TYPE_EDGE_FALLING:
 421                int_type |= BIT(bank_pin_num);
 422                int_pol &= ~BIT(bank_pin_num);
 423                int_any &= ~BIT(bank_pin_num);
 424                break;
 425        case IRQ_TYPE_EDGE_BOTH:
 426                int_type |= BIT(bank_pin_num);
 427                int_any |= BIT(bank_pin_num);
 428                break;
 429        case IRQ_TYPE_LEVEL_HIGH:
 430                int_type &= ~BIT(bank_pin_num);
 431                int_pol |= BIT(bank_pin_num);
 432                break;
 433        case IRQ_TYPE_LEVEL_LOW:
 434                int_type &= ~BIT(bank_pin_num);
 435                int_pol &= ~BIT(bank_pin_num);
 436                break;
 437        default:
 438                return -EINVAL;
 439        }
 440
 441        writel_relaxed(int_type,
 442                       gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
 443        writel_relaxed(int_pol,
 444                       gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
 445        writel_relaxed(int_any,
 446                       gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
 447
 448        if (type & IRQ_TYPE_LEVEL_MASK) {
 449                irq_set_chip_handler_name_locked(irq_data,
 450                        &zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
 451        } else {
 452                irq_set_chip_handler_name_locked(irq_data,
 453                        &zynq_gpio_edge_irqchip, handle_level_irq, NULL);
 454        }
 455
 456        return 0;
 457}
 458
 459static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
 460{
 461        struct zynq_gpio *gpio =
 462                gpiochip_get_data(irq_data_get_irq_chip_data(data));
 463
 464        irq_set_irq_wake(gpio->irq, on);
 465
 466        return 0;
 467}
 468
 469/* irq chip descriptor */
 470static struct irq_chip zynq_gpio_level_irqchip = {
 471        .name           = DRIVER_NAME,
 472        .irq_enable     = zynq_gpio_irq_enable,
 473        .irq_eoi        = zynq_gpio_irq_ack,
 474        .irq_mask       = zynq_gpio_irq_mask,
 475        .irq_unmask     = zynq_gpio_irq_unmask,
 476        .irq_set_type   = zynq_gpio_set_irq_type,
 477        .irq_set_wake   = zynq_gpio_set_wake,
 478        .flags          = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
 479                          IRQCHIP_MASK_ON_SUSPEND,
 480};
 481
 482static struct irq_chip zynq_gpio_edge_irqchip = {
 483        .name           = DRIVER_NAME,
 484        .irq_enable     = zynq_gpio_irq_enable,
 485        .irq_ack        = zynq_gpio_irq_ack,
 486        .irq_mask       = zynq_gpio_irq_mask,
 487        .irq_unmask     = zynq_gpio_irq_unmask,
 488        .irq_set_type   = zynq_gpio_set_irq_type,
 489        .irq_set_wake   = zynq_gpio_set_wake,
 490        .flags          = IRQCHIP_MASK_ON_SUSPEND,
 491};
 492
 493static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
 494                                      unsigned int bank_num,
 495                                      unsigned long pending)
 496{
 497        unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
 498        struct irq_domain *irqdomain = gpio->chip.irqdomain;
 499        int offset;
 500
 501        if (!pending)
 502                return;
 503
 504        for_each_set_bit(offset, &pending, 32) {
 505                unsigned int gpio_irq;
 506
 507                gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
 508                generic_handle_irq(gpio_irq);
 509        }
 510}
 511
 512/**
 513 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
 514 * @irq:        irq number of the gpio bank where interrupt has occurred
 515 * @desc:       irq descriptor instance of the 'irq'
 516 *
 517 * This function reads the Interrupt Status Register of each bank to get the
 518 * gpio pin number which has triggered an interrupt. It then acks the triggered
 519 * interrupt and calls the pin specific handler set by the higher layer
 520 * application for that pin.
 521 * Note: A bug is reported if no handler is set for the gpio pin.
 522 */
 523static void zynq_gpio_irqhandler(struct irq_desc *desc)
 524{
 525        u32 int_sts, int_enb;
 526        unsigned int bank_num;
 527        struct zynq_gpio *gpio =
 528                gpiochip_get_data(irq_desc_get_handler_data(desc));
 529        struct irq_chip *irqchip = irq_desc_get_chip(desc);
 530
 531        chained_irq_enter(irqchip, desc);
 532
 533        for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
 534                int_sts = readl_relaxed(gpio->base_addr +
 535                                        ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
 536                int_enb = readl_relaxed(gpio->base_addr +
 537                                        ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
 538                zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
 539        }
 540
 541        chained_irq_exit(irqchip, desc);
 542}
 543
 544static int __maybe_unused zynq_gpio_suspend(struct device *dev)
 545{
 546        struct platform_device *pdev = to_platform_device(dev);
 547        int irq = platform_get_irq(pdev, 0);
 548        struct irq_data *data = irq_get_irq_data(irq);
 549
 550        if (!irqd_is_wakeup_set(data))
 551                return pm_runtime_force_suspend(dev);
 552
 553        return 0;
 554}
 555
 556static int __maybe_unused zynq_gpio_resume(struct device *dev)
 557{
 558        struct platform_device *pdev = to_platform_device(dev);
 559        int irq = platform_get_irq(pdev, 0);
 560        struct irq_data *data = irq_get_irq_data(irq);
 561
 562        if (!irqd_is_wakeup_set(data))
 563                return pm_runtime_force_resume(dev);
 564
 565        return 0;
 566}
 567
 568static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
 569{
 570        struct platform_device *pdev = to_platform_device(dev);
 571        struct zynq_gpio *gpio = platform_get_drvdata(pdev);
 572
 573        clk_disable_unprepare(gpio->clk);
 574
 575        return 0;
 576}
 577
 578static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
 579{
 580        struct platform_device *pdev = to_platform_device(dev);
 581        struct zynq_gpio *gpio = platform_get_drvdata(pdev);
 582
 583        return clk_prepare_enable(gpio->clk);
 584}
 585
 586static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset)
 587{
 588        int ret;
 589
 590        ret = pm_runtime_get_sync(chip->parent);
 591
 592        /*
 593         * If the device is already active pm_runtime_get() will return 1 on
 594         * success, but gpio_request still needs to return 0.
 595         */
 596        return ret < 0 ? ret : 0;
 597}
 598
 599static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset)
 600{
 601        pm_runtime_put(chip->parent);
 602}
 603
 604static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
 605        SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
 606        SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
 607                        zynq_gpio_runtime_resume, NULL)
 608};
 609
 610static const struct zynq_platform_data zynqmp_gpio_def = {
 611        .label = "zynqmp_gpio",
 612        .ngpio = ZYNQMP_GPIO_NR_GPIOS,
 613        .max_bank = ZYNQMP_GPIO_MAX_BANK,
 614        .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
 615        .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
 616        .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
 617        .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
 618        .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
 619        .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
 620        .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
 621        .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
 622        .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
 623        .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
 624        .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
 625        .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
 626};
 627
 628static const struct zynq_platform_data zynq_gpio_def = {
 629        .label = "zynq_gpio",
 630        .ngpio = ZYNQ_GPIO_NR_GPIOS,
 631        .max_bank = ZYNQ_GPIO_MAX_BANK,
 632        .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
 633        .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
 634        .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
 635        .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
 636        .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
 637        .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
 638        .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
 639        .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
 640};
 641
 642static const struct of_device_id zynq_gpio_of_match[] = {
 643        { .compatible = "xlnx,zynq-gpio-1.0", .data = (void *)&zynq_gpio_def },
 644        { .compatible = "xlnx,zynqmp-gpio-1.0",
 645                                        .data = (void *)&zynqmp_gpio_def },
 646        { /* end of table */ }
 647};
 648MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
 649
 650/**
 651 * zynq_gpio_probe - Initialization method for a zynq_gpio device
 652 * @pdev:       platform device instance
 653 *
 654 * This function allocates memory resources for the gpio device and registers
 655 * all the banks of the device. It will also set up interrupts for the gpio
 656 * pins.
 657 * Note: Interrupts are disabled for all the banks during initialization.
 658 *
 659 * Return: 0 on success, negative error otherwise.
 660 */
 661static int zynq_gpio_probe(struct platform_device *pdev)
 662{
 663        int ret, bank_num;
 664        struct zynq_gpio *gpio;
 665        struct gpio_chip *chip;
 666        struct resource *res;
 667        const struct of_device_id *match;
 668
 669        gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
 670        if (!gpio)
 671                return -ENOMEM;
 672
 673        match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
 674        if (!match) {
 675                dev_err(&pdev->dev, "of_match_node() failed\n");
 676                return -EINVAL;
 677        }
 678        gpio->p_data = match->data;
 679        platform_set_drvdata(pdev, gpio);
 680
 681        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 682        gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
 683        if (IS_ERR(gpio->base_addr))
 684                return PTR_ERR(gpio->base_addr);
 685
 686        gpio->irq = platform_get_irq(pdev, 0);
 687        if (gpio->irq < 0) {
 688                dev_err(&pdev->dev, "invalid IRQ\n");
 689                return gpio->irq;
 690        }
 691
 692        /* configure the gpio chip */
 693        chip = &gpio->chip;
 694        chip->label = gpio->p_data->label;
 695        chip->owner = THIS_MODULE;
 696        chip->parent = &pdev->dev;
 697        chip->get = zynq_gpio_get_value;
 698        chip->set = zynq_gpio_set_value;
 699        chip->request = zynq_gpio_request;
 700        chip->free = zynq_gpio_free;
 701        chip->direction_input = zynq_gpio_dir_in;
 702        chip->direction_output = zynq_gpio_dir_out;
 703        chip->base = -1;
 704        chip->ngpio = gpio->p_data->ngpio;
 705
 706        /* Retrieve GPIO clock */
 707        gpio->clk = devm_clk_get(&pdev->dev, NULL);
 708        if (IS_ERR(gpio->clk)) {
 709                dev_err(&pdev->dev, "input clock not found.\n");
 710                return PTR_ERR(gpio->clk);
 711        }
 712        ret = clk_prepare_enable(gpio->clk);
 713        if (ret) {
 714                dev_err(&pdev->dev, "Unable to enable clock.\n");
 715                return ret;
 716        }
 717
 718        pm_runtime_set_active(&pdev->dev);
 719        pm_runtime_enable(&pdev->dev);
 720        ret = pm_runtime_get_sync(&pdev->dev);
 721        if (ret < 0)
 722                goto err_pm_dis;
 723
 724        /* report a bug if gpio chip registration fails */
 725        ret = gpiochip_add_data(chip, gpio);
 726        if (ret) {
 727                dev_err(&pdev->dev, "Failed to add gpio chip\n");
 728                goto err_pm_put;
 729        }
 730
 731        /* disable interrupts for all banks */
 732        for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
 733                writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
 734                               ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
 735
 736        ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
 737                                   handle_level_irq, IRQ_TYPE_NONE);
 738        if (ret) {
 739                dev_err(&pdev->dev, "Failed to add irq chip\n");
 740                goto err_rm_gpiochip;
 741        }
 742
 743        gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
 744                                     zynq_gpio_irqhandler);
 745
 746        pm_runtime_put(&pdev->dev);
 747
 748        return 0;
 749
 750err_rm_gpiochip:
 751        gpiochip_remove(chip);
 752err_pm_put:
 753        pm_runtime_put(&pdev->dev);
 754err_pm_dis:
 755        pm_runtime_disable(&pdev->dev);
 756        clk_disable_unprepare(gpio->clk);
 757
 758        return ret;
 759}
 760
 761/**
 762 * zynq_gpio_remove - Driver removal function
 763 * @pdev:       platform device instance
 764 *
 765 * Return: 0 always
 766 */
 767static int zynq_gpio_remove(struct platform_device *pdev)
 768{
 769        struct zynq_gpio *gpio = platform_get_drvdata(pdev);
 770
 771        pm_runtime_get_sync(&pdev->dev);
 772        gpiochip_remove(&gpio->chip);
 773        clk_disable_unprepare(gpio->clk);
 774        device_set_wakeup_capable(&pdev->dev, 0);
 775        pm_runtime_disable(&pdev->dev);
 776        return 0;
 777}
 778
 779static struct platform_driver zynq_gpio_driver = {
 780        .driver = {
 781                .name = DRIVER_NAME,
 782                .pm = &zynq_gpio_dev_pm_ops,
 783                .of_match_table = zynq_gpio_of_match,
 784        },
 785        .probe = zynq_gpio_probe,
 786        .remove = zynq_gpio_remove,
 787};
 788
 789/**
 790 * zynq_gpio_init - Initial driver registration call
 791 *
 792 * Return: value from platform_driver_register
 793 */
 794static int __init zynq_gpio_init(void)
 795{
 796        return platform_driver_register(&zynq_gpio_driver);
 797}
 798postcore_initcall(zynq_gpio_init);
 799
 800static void __exit zynq_gpio_exit(void)
 801{
 802        platform_driver_unregister(&zynq_gpio_driver);
 803}
 804module_exit(zynq_gpio_exit);
 805
 806MODULE_AUTHOR("Xilinx Inc.");
 807MODULE_DESCRIPTION("Zynq GPIO driver");
 808MODULE_LICENSE("GPL");
 809