/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include "linux/delay.h"

#include "hwmgr.h"
#include "fiji_smumgr.h"
#include "atombios.h"
#include "hardwaremanager.h"
#include "ppatomctrl.h"
#include "atombios.h"
#include "cgs_common.h"
#include "fiji_dyn_defaults.h"
#include "fiji_powertune.h"
#include "smu73.h"
#include "smu/smu_7_1_3_d.h"
#include "smu/smu_7_1_3_sh_mask.h"
#include "gmc/gmc_8_1_d.h"
#include "gmc/gmc_8_1_sh_mask.h"
#include "bif/bif_5_0_d.h"
#include "bif/bif_5_0_sh_mask.h"
#include "dce/dce_10_0_d.h"
#include "dce/dce_10_0_sh_mask.h"
#include "pppcielanes.h"
#include "fiji_hwmgr.h"
#include "tonga_processpptables.h"
#include "tonga_pptable.h"
#include "pp_debug.h"
#include "pp_acpi.h"
#include "amd_pcie_helpers.h"
#include "cgs_linux.h"
#include "ppinterrupt.h"

#include "fiji_clockpowergating.h"
#include "fiji_thermal.h"

#define VOLTAGE_SCALE   4
#define SMC_RAM_END             0x40000
#define VDDC_VDDCI_DELTA        300

#define MC_SEQ_MISC0_GDDR5_SHIFT 28
#define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
#define MC_SEQ_MISC0_GDDR5_VALUE 5

#define MC_CG_ARB_FREQ_F0           0x0a /* boot-up default */
#define MC_CG_ARB_FREQ_F1           0x0b
#define MC_CG_ARB_FREQ_F2           0x0c
#define MC_CG_ARB_FREQ_F3           0x0d

/* From smc_reg.h */
#define SMC_CG_IND_START            0xc0030000
#define SMC_CG_IND_END              0xc0040000  /* First byte after SMC_CG_IND */

#define VOLTAGE_SCALE               4
#define VOLTAGE_VID_OFFSET_SCALE1   625
#define VOLTAGE_VID_OFFSET_SCALE2   100

#define VDDC_VDDCI_DELTA            300

#define ixSWRST_COMMAND_1           0x1400103
#define MC_SEQ_CNTL__CAC_EN_MASK    0x40000000

/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
enum DPM_EVENT_SRC {
    DPM_EVENT_SRC_ANALOG = 0,               /* Internal analog trip point */
    DPM_EVENT_SRC_EXTERNAL = 1,             /* External (GPIO 17) signal */
    DPM_EVENT_SRC_DIGITAL = 2,              /* Internal digital trip point (DIG_THERM_DPM) */
    DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,   /* Internal analog or external */
    DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4   /* Internal digital or external */
};


/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
 * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
 */
static const uint16_t fiji_clock_stretcher_lookup_table[2][4] =
{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };

/* [FF, SS] type, [] 4 voltage ranges, and
 * [Floor Freq, Boundary Freq, VID min , VID max]
 */
static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
{ { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
  { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };

/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
 * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
 */
static const uint8_t fiji_clock_stretch_amount_conversion[2][6] =
{ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };

static const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);

struct fiji_power_state *cast_phw_fiji_power_state(
                                  struct pp_hw_power_state *hw_ps)
{
        PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
                                "Invalid Powerstate Type!",
                                 return NULL;);

        return (struct fiji_power_state *)hw_ps;
}

const struct fiji_power_state *cast_const_phw_fiji_power_state(
                                 const struct pp_hw_power_state *hw_ps)
{
        PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
                                "Invalid Powerstate Type!",
                                 return NULL;);

        return (const struct fiji_power_state *)hw_ps;
}

static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
{
        return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
                        CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
                        ? true : false;
}

static void fiji_init_dpm_defaults(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct fiji_ulv_parm *ulv = &data->ulv;

        ulv->cg_ulv_parameter = PPFIJI_CGULVPARAMETER_DFLT;
        data->voting_rights_clients0 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0;
        data->voting_rights_clients1 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1;
        data->voting_rights_clients2 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2;
        data->voting_rights_clients3 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3;
        data->voting_rights_clients4 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4;
        data->voting_rights_clients5 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5;
        data->voting_rights_clients6 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6;
        data->voting_rights_clients7 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7;

        data->static_screen_threshold_unit =
                        PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT;
        data->static_screen_threshold =
                        PPFIJI_STATICSCREENTHRESHOLD_DFLT;

        /* Unset ABM cap as it moved to DAL.
         * Add PHM_PlatformCaps_NonABMSupportInPPLib
         * for re-direct ABM related request to DAL
         */
        phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_ABM);
        phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_NonABMSupportInPPLib);

        phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_DynamicACTiming);

        fiji_initialize_power_tune_defaults(hwmgr);

        data->mclk_stutter_mode_threshold = 60000;
        data->pcie_gen_performance.max = PP_PCIEGen1;
        data->pcie_gen_performance.min = PP_PCIEGen3;
        data->pcie_gen_power_saving.max = PP_PCIEGen1;
        data->pcie_gen_power_saving.min = PP_PCIEGen3;
        data->pcie_lane_performance.max = 0;
        data->pcie_lane_performance.min = 16;
        data->pcie_lane_power_saving.max = 0;
        data->pcie_lane_power_saving.min = 16;

        phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_DynamicUVDState);
}

static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
        phm_ppt_v1_voltage_lookup_table *lookup_table,
        uint16_t virtual_voltage_id, int32_t *sclk)
{
        uint8_t entryId;
        uint8_t voltageId;
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);

        PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);

        /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
        for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
                voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
                if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
                        break;
        }

        PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
                        "Can't find requested voltage id in vdd_dep_on_sclk table!",
                        return -EINVAL;
                        );

        *sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;

        return 0;
}

/**
* Get Leakage VDDC based on leakage ID.
*
* @param    hwmgr  the address of the powerplay hardware manager.
* @return   always 0
*/
static int fiji_get_evv_voltages(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        uint16_t    vv_id;
        uint16_t    vddc = 0;
        uint16_t    evv_default = 1150;
        uint16_t    i, j;
        uint32_t  sclk = 0;
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)hwmgr->pptable;
        struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
                        table_info->vdd_dep_on_sclk;
        int result;

        for (i = 0; i < FIJI_MAX_LEAKAGE_COUNT; i++) {
                vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
                if (!fiji_get_sclk_for_voltage_evv(hwmgr,
                                table_info->vddc_lookup_table, vv_id, &sclk)) {
                        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                                        PHM_PlatformCaps_ClockStretcher)) {
                                for (j = 1; j < sclk_table->count; j++) {
                                        if (sclk_table->entries[j].clk == sclk &&
                                                        sclk_table->entries[j].cks_enable == 0) {
                                                sclk += 5000;
                                                break;
                                        }
                                }
                        }

                        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                                        PHM_PlatformCaps_EnableDriverEVV))
                                result = atomctrl_calculate_voltage_evv_on_sclk(hwmgr,
                                                VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc, i, true);
                        else
                                result = -EINVAL;

                        if (result)
                                result = atomctrl_get_voltage_evv_on_sclk(hwmgr,
                                                VOLTAGE_TYPE_VDDC, sclk,vv_id, &vddc);

                        /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
                        PP_ASSERT_WITH_CODE((vddc < 2000),
                                        "Invalid VDDC value, greater than 2v!", result = -EINVAL;);

                        if (result)
                                /* 1.15V is the default safe value for Fiji */
                                vddc = evv_default;

                        /* the voltage should not be zero nor equal to leakage ID */
                        if (vddc != 0 && vddc != vv_id) {
                                data->vddc_leakage.actual_voltage
                                [data->vddc_leakage.count] = vddc;
                                data->vddc_leakage.leakage_id
                                [data->vddc_leakage.count] = vv_id;
                                data->vddc_leakage.count++;
                        }
                }
        }
        return 0;
}

/**
 * Change virtual leakage voltage to actual value.
 *
 * @param     hwmgr  the address of the powerplay hardware manager.
 * @param     pointer to changing voltage
 * @param     pointer to leakage table
 */
static void fiji_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
                uint16_t *voltage, struct fiji_leakage_voltage *leakage_table)
{
        uint32_t index;

        /* search for leakage voltage ID 0xff01 ~ 0xff08 */
        for (index = 0; index < leakage_table->count; index++) {
                /* if this voltage matches a leakage voltage ID */
                /* patch with actual leakage voltage */
                if (leakage_table->leakage_id[index] == *voltage) {
                        *voltage = leakage_table->actual_voltage[index];
                        break;
                }
        }

        if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
                printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
}

/**
* Patch voltage lookup table by EVV leakages.
*
* @param     hwmgr  the address of the powerplay hardware manager.
* @param     pointer to voltage lookup table
* @param     pointer to leakage table
* @return     always 0
*/
static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
                phm_ppt_v1_voltage_lookup_table *lookup_table,
                struct fiji_leakage_voltage *leakage_table)
{
        uint32_t i;

        for (i = 0; i < lookup_table->count; i++)
                fiji_patch_with_vdd_leakage(hwmgr,
                                &lookup_table->entries[i].us_vdd, leakage_table);

        return 0;
}

static int fiji_patch_clock_voltage_limits_with_vddc_leakage(
                struct pp_hwmgr *hwmgr, struct fiji_leakage_voltage *leakage_table,
                uint16_t *vddc)
{
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        fiji_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
        hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
                        table_info->max_clock_voltage_on_dc.vddc;
        return 0;
}

static int fiji_patch_voltage_dependency_tables_with_lookup_table(
                struct pp_hwmgr *hwmgr)
{
        uint8_t entryId;
        uint8_t voltageId;
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);

        struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
                        table_info->vdd_dep_on_sclk;
        struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
                        table_info->vdd_dep_on_mclk;
        struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
                        table_info->mm_dep_table;

        for (entryId = 0; entryId < sclk_table->count; ++entryId) {
                voltageId = sclk_table->entries[entryId].vddInd;
                sclk_table->entries[entryId].vddc =
                                table_info->vddc_lookup_table->entries[voltageId].us_vdd;
        }

        for (entryId = 0; entryId < mclk_table->count; ++entryId) {
                voltageId = mclk_table->entries[entryId].vddInd;
                mclk_table->entries[entryId].vddc =
                        table_info->vddc_lookup_table->entries[voltageId].us_vdd;
        }

        for (entryId = 0; entryId < mm_table->count; ++entryId) {
                voltageId = mm_table->entries[entryId].vddcInd;
                mm_table->entries[entryId].vddc =
                        table_info->vddc_lookup_table->entries[voltageId].us_vdd;
        }

        return 0;

}

static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
{
        /* Need to determine if we need calculated voltage. */
        return 0;
}

static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
{
        /* Need to determine if we need calculated voltage from mm table. */
        return 0;
}

static int fiji_sort_lookup_table(struct pp_hwmgr *hwmgr,
                struct phm_ppt_v1_voltage_lookup_table *lookup_table)
{
        uint32_t table_size, i, j;
        struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
        table_size = lookup_table->count;

        PP_ASSERT_WITH_CODE(0 != lookup_table->count,
                "Lookup table is empty", return -EINVAL);

        /* Sorting voltages */
        for (i = 0; i < table_size - 1; i++) {
                for (j = i + 1; j > 0; j--) {
                        if (lookup_table->entries[j].us_vdd <
                                        lookup_table->entries[j - 1].us_vdd) {
                                tmp_voltage_lookup_record = lookup_table->entries[j - 1];
                                lookup_table->entries[j - 1] = lookup_table->entries[j];
                                lookup_table->entries[j] = tmp_voltage_lookup_record;
                        }
                }
        }

        return 0;
}

static int fiji_complete_dependency_tables(struct pp_hwmgr *hwmgr)
{
        int result = 0;
        int tmp_result;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);

        tmp_result = fiji_patch_lookup_table_with_leakage(hwmgr,
                        table_info->vddc_lookup_table, &(data->vddc_leakage));
        if (tmp_result)
                result = tmp_result;

        tmp_result = fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
                        &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
        if (tmp_result)
                result = tmp_result;

        tmp_result = fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
        if (tmp_result)
                result = tmp_result;

        tmp_result = fiji_calc_voltage_dependency_tables(hwmgr);
        if (tmp_result)
                result = tmp_result;

        tmp_result = fiji_calc_mm_voltage_dependency_table(hwmgr);
        if (tmp_result)
                result = tmp_result;

        tmp_result = fiji_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
        if(tmp_result)
                result = tmp_result;

        return result;
}

static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);

        struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
                        table_info->vdd_dep_on_sclk;
        struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
                        table_info->vdd_dep_on_mclk;

        PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
                "VDD dependency on SCLK table is missing.       \
                This table is mandatory", return -EINVAL);
        PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
                "VDD dependency on SCLK table has to have is missing.   \
                This table is mandatory", return -EINVAL);

        PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
                "VDD dependency on MCLK table is missing.       \
                This table is mandatory", return -EINVAL);
        PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
                "VDD dependency on MCLK table has to have is missing.    \
                This table is mandatory", return -EINVAL);

        data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
        data->max_vddc_in_pptable =     (uint16_t)allowed_sclk_vdd_table->
                        entries[allowed_sclk_vdd_table->count - 1].vddc;

        table_info->max_clock_voltage_on_ac.sclk =
                allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
        table_info->max_clock_voltage_on_ac.mclk =
                allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
        table_info->max_clock_voltage_on_ac.vddc =
                allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
        table_info->max_clock_voltage_on_ac.vddci =
                allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;

        hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
                table_info->max_clock_voltage_on_ac.sclk;
        hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
                table_info->max_clock_voltage_on_ac.mclk;
        hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
                table_info->max_clock_voltage_on_ac.vddc;
        hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
                table_info->max_clock_voltage_on_ac.vddci;

        return 0;
}

static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
{
        uint32_t speedCntl = 0;

        /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
        speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
                        ixPCIE_LC_SPEED_CNTL);
        return((uint16_t)PHM_GET_FIELD(speedCntl,
                        PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
}

static int fiji_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
{
        uint32_t link_width;

        /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
        link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
                        PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);

        PP_ASSERT_WITH_CODE((7 >= link_width),
                        "Invalid PCIe lane width!", return 0);

        return decode_pcie_lane_width(link_width);
}

/** Patch the Boot State to match VBIOS boot clocks and voltage.
*
* @param hwmgr Pointer to the hardware manager.
* @param pPowerState The address of the PowerState instance being created.
*
*/
static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
                struct pp_hw_power_state *hw_ps)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct fiji_power_state *ps = (struct fiji_power_state *)hw_ps;
        ATOM_FIRMWARE_INFO_V2_2 *fw_info;
        uint16_t size;
        uint8_t frev, crev;
        int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);

        /* First retrieve the Boot clocks and VDDC from the firmware info table.
         * We assume here that fw_info is unchanged if this call fails.
         */
        fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
                        hwmgr->device, index,
                        &size, &frev, &crev);
        if (!fw_info)
                /* During a test, there is no firmware info table. */
                return 0;

        /* Patch the state. */
        data->vbios_boot_state.sclk_bootup_value =
                        le32_to_cpu(fw_info->ulDefaultEngineClock);
        data->vbios_boot_state.mclk_bootup_value =
                        le32_to_cpu(fw_info->ulDefaultMemoryClock);
        data->vbios_boot_state.mvdd_bootup_value =
                        le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
        data->vbios_boot_state.vddc_bootup_value =
                        le16_to_cpu(fw_info->usBootUpVDDCVoltage);
        data->vbios_boot_state.vddci_bootup_value =
                        le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
        data->vbios_boot_state.pcie_gen_bootup_value =
                        fiji_get_current_pcie_speed(hwmgr);
        data->vbios_boot_state.pcie_lane_bootup_value =
                        (uint16_t)fiji_get_current_pcie_lane_number(hwmgr);

        /* set boot power state */
        ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
        ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
        ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
        ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;

        return 0;
}

static int fiji_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
{
        return phm_hwmgr_backend_fini(hwmgr);
}

static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data;
        uint32_t i;
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        bool stay_in_boot;
        int result;

        data = kzalloc(sizeof(struct fiji_hwmgr), GFP_KERNEL);
        if (data == NULL)
                return -ENOMEM;

        hwmgr->backend = data;

        data->dll_default_on = false;
        data->sram_end = SMC_RAM_END;

        for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
                data->activity_target[i] = FIJI_AT_DFLT;

        data->vddc_vddci_delta = VDDC_VDDCI_DELTA;

        data->mclk_activity_target = PPFIJI_MCLK_TARGETACTIVITY_DFLT;
        data->mclk_dpm0_activity_target = 0xa;

        data->sclk_dpm_key_disabled = 0;
        data->mclk_dpm_key_disabled = 0;
        data->pcie_dpm_key_disabled = 0;

        phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_UnTabledHardwareInterface);
        phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_TablelessHardwareInterface);

        phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_SclkDeepSleep);

        data->gpio_debug = 0;

        phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_DynamicPatchPowerState);

        /* need to set voltage control types before EVV patching */
        data->voltage_control = FIJI_VOLTAGE_CONTROL_NONE;
        data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
        data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;

        data->force_pcie_gen = PP_PCIEGenInvalid;

        if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
                        VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
                data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;

        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_EnableMVDDControl))
                if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
                                VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
                        data->mvdd_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;

        if (data->mvdd_control == FIJI_VOLTAGE_CONTROL_NONE)
                phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_EnableMVDDControl);

        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_ControlVDDCI)) {
                if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
                                VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
                        data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
                else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
                                VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
                        data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
        }

        if (data->vddci_control == FIJI_VOLTAGE_CONTROL_NONE)
                phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
                                PHM_PlatformCaps_ControlVDDCI);

        if (table_info && table_info->cac_dtp_table->usClockStretchAmount)
                phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                PHM_PlatformCaps_ClockStretcher);

        fiji_init_dpm_defaults(hwmgr);

        /* Get leakage voltage based on leakage ID. */
        fiji_get_evv_voltages(hwmgr);

        /* Patch our voltage dependency table with actual leakage voltage
         * We need to perform leakage translation before it's used by other functions
         */
        fiji_complete_dependency_tables(hwmgr);

        /* Parse pptable data read from VBIOS */
        fiji_set_private_data_based_on_pptable(hwmgr);

        /* ULV Support */
        data->ulv.ulv_supported = true; /* ULV feature is enabled by default */

        /* Initalize Dynamic State Adjustment Rule Settings */
        result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);

        if (!result) {
                data->uvd_enabled = false;
                phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                PHM_PlatformCaps_EnableSMU7ThermalManagement);
                data->vddc_phase_shed_control = false;
        }

        stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_StayInBootState);

        if (0 == result) {
                struct cgs_system_info sys_info = {0};

                data->is_tlu_enabled = false;
                hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
                                FIJI_MAX_HARDWARE_POWERLEVELS;
                hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
                hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;

                phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                PHM_PlatformCaps_FanSpeedInTableIsRPM);

                if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp &&
                                hwmgr->thermal_controller.
                                advanceFanControlParameters.ucFanControlMode) {
                        hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
                        hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
                        hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
                                        table_info->cac_dtp_table->usOperatingTempMinLimit;
                        hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
                                        table_info->cac_dtp_table->usOperatingTempMaxLimit;
                        hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
                                        table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
                        hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
                                        table_info->cac_dtp_table->usOperatingTempStep;
                        hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
                                        table_info->cac_dtp_table->usTargetOperatingTemp;

                        phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                        PHM_PlatformCaps_ODFuzzyFanControlSupport);
                }

                sys_info.size = sizeof(struct cgs_system_info);
                sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
                result = cgs_query_system_info(hwmgr->device, &sys_info);
                if (result)
                        data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
                else
                        data->pcie_gen_cap = (uint32_t)sys_info.value;
                if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
                        data->pcie_spc_cap = 20;
                sys_info.size = sizeof(struct cgs_system_info);
                sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
                result = cgs_query_system_info(hwmgr->device, &sys_info);
                if (result)
                        data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
                else
                        data->pcie_lane_cap = (uint32_t)sys_info.value;
        } else {
                /* Ignore return value in here, we are cleaning up a mess. */
                fiji_hwmgr_backend_fini(hwmgr);
        }

        return 0;
}

/**
 * Read clock related registers.
 *
 * @param    hwmgr  the address of the powerplay hardware manager.
 * @return   always 0
 */
static int fiji_read_clock_registers(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);

        data->clock_registers.vCG_SPLL_FUNC_CNTL =
                cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                                ixCG_SPLL_FUNC_CNTL);
        data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
                cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                                ixCG_SPLL_FUNC_CNTL_2);
        data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
                cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                                ixCG_SPLL_FUNC_CNTL_3);
        data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
                cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                                ixCG_SPLL_FUNC_CNTL_4);
        data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
                cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                                ixCG_SPLL_SPREAD_SPECTRUM);
        data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
                cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                                ixCG_SPLL_SPREAD_SPECTRUM_2);

        return 0;
}

/**
 * Find out if memory is GDDR5.
 *
 * @param    hwmgr  the address of the powerplay hardware manager.
 * @return   always 0
 */
static int fiji_get_memory_type(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        uint32_t temp;

        temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);

        data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
                        ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
                         MC_SEQ_MISC0_GDDR5_SHIFT));

        return 0;
}

/**
 * Enables Dynamic Power Management by SMC
 *
 * @param    hwmgr  the address of the powerplay hardware manager.
 * @return   always 0
 */
static int fiji_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
{
        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        GENERAL_PWRMGT, STATIC_PM_EN, 1);

        return 0;
}

/**
 * Initialize PowerGating States for different engines
 *
 * @param    hwmgr  the address of the powerplay hardware manager.
 * @return   always 0
 */
static int fiji_init_power_gate_state(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);

        data->uvd_power_gated = false;
        data->vce_power_gated = false;
        data->samu_power_gated = false;
        data->acp_power_gated = false;
        data->pg_acp_init = true;

        return 0;
}

static int fiji_init_sclk_threshold(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        data->low_sclk_interrupt_threshold = 0;

        return 0;
}

static int fiji_setup_asic_task(struct pp_hwmgr *hwmgr)
{
        int tmp_result, result = 0;

        tmp_result = fiji_read_clock_registers(hwmgr);
        PP_ASSERT_WITH_CODE((0 == tmp_result),
                        "Failed to read clock registers!", result = tmp_result);

        tmp_result = fiji_get_memory_type(hwmgr);
        PP_ASSERT_WITH_CODE((0 == tmp_result),
                        "Failed to get memory type!", result = tmp_result);

        tmp_result = fiji_enable_acpi_power_management(hwmgr);
        PP_ASSERT_WITH_CODE((0 == tmp_result),
                        "Failed to enable ACPI power management!", result = tmp_result);

        tmp_result = fiji_init_power_gate_state(hwmgr);
        PP_ASSERT_WITH_CODE((0 == tmp_result),
                        "Failed to init power gate state!", result = tmp_result);

        tmp_result = tonga_get_mc_microcode_version(hwmgr);
        PP_ASSERT_WITH_CODE((0 == tmp_result),
                        "Failed to get MC microcode version!", result = tmp_result);

        tmp_result = fiji_init_sclk_threshold(hwmgr);
        PP_ASSERT_WITH_CODE((0 == tmp_result),
                        "Failed to init sclk threshold!", result = tmp_result);

        return result;
}

/**
* Checks if we want to support voltage control
*
* @param    hwmgr  the address of the powerplay hardware manager.
*/
static bool fiji_voltage_control(const struct pp_hwmgr *hwmgr)
{
        const struct fiji_hwmgr *data =
                        (const struct fiji_hwmgr *)(hwmgr->backend);

        return (FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control);
}

/**
* Enable voltage control
*
* @param    hwmgr  the address of the powerplay hardware manager.
* @return   always 0
*/
static int fiji_enable_voltage_control(struct pp_hwmgr *hwmgr)
{
        /* enable voltage control */
        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);

        return 0;
}

/**
* Remove repeated voltage values and create table with unique values.
*
* @param    hwmgr  the address of the powerplay hardware manager.
* @param    vol_table  the pointer to changing voltage table
* @return    0 in success
*/

static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr,
                struct pp_atomctrl_voltage_table *vol_table)
{
        uint32_t i, j;
        uint16_t vvalue;
        bool found = false;
        struct pp_atomctrl_voltage_table *table;

        PP_ASSERT_WITH_CODE((NULL != vol_table),
                        "Voltage Table empty.", return -EINVAL);
        table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
                        GFP_KERNEL);

        if (NULL == table)
                return -ENOMEM;

        table->mask_low = vol_table->mask_low;
        table->phase_delay = vol_table->phase_delay;

        for (i = 0; i < vol_table->count; i++) {
                vvalue = vol_table->entries[i].value;
                found = false;

                for (j = 0; j < table->count; j++) {
                        if (vvalue == table->entries[j].value) {
                                found = true;
                                break;
                        }
                }

                if (!found) {
                        table->entries[table->count].value = vvalue;
                        table->entries[table->count].smio_low =
                                        vol_table->entries[i].smio_low;
                        table->count++;
                }
        }

        memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
        kfree(table);

        return 0;
}

static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
                phm_ppt_v1_clock_voltage_dependency_table *dep_table)
{
        uint32_t i;
        int result;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct pp_atomctrl_voltage_table *vol_table = &(data->mvdd_voltage_table);

        PP_ASSERT_WITH_CODE((0 != dep_table->count),
                        "Voltage Dependency Table empty.", return -EINVAL);

        vol_table->mask_low = 0;
        vol_table->phase_delay = 0;
        vol_table->count = dep_table->count;

        for (i = 0; i < dep_table->count; i++) {
                vol_table->entries[i].value = dep_table->entries[i].mvdd;
                vol_table->entries[i].smio_low = 0;
        }

        result = fiji_trim_voltage_table(hwmgr, vol_table);
        PP_ASSERT_WITH_CODE((0 == result),
                        "Failed to trim MVDD table.", return result);

        return 0;
}

static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr *hwmgr,
                phm_ppt_v1_clock_voltage_dependency_table *dep_table)
{
        uint32_t i;
        int result;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct pp_atomctrl_voltage_table *vol_table = &(data->vddci_voltage_table);

        PP_ASSERT_WITH_CODE((0 != dep_table->count),
                        "Voltage Dependency Table empty.", return -EINVAL);

        vol_table->mask_low = 0;
        vol_table->phase_delay = 0;
        vol_table->count = dep_table->count;

        for (i = 0; i < dep_table->count; i++) {
                vol_table->entries[i].value = dep_table->entries[i].vddci;
                vol_table->entries[i].smio_low = 0;
        }

        result = fiji_trim_voltage_table(hwmgr, vol_table);
        PP_ASSERT_WITH_CODE((0 == result),
                        "Failed to trim VDDCI table.", return result);

        return 0;
}

static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr *hwmgr,
                phm_ppt_v1_voltage_lookup_table *lookup_table)
{
        int i = 0;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct pp_atomctrl_voltage_table *vol_table = &(data->vddc_voltage_table);

        PP_ASSERT_WITH_CODE((0 != lookup_table->count),
                        "Voltage Lookup Table empty.", return -EINVAL);

        vol_table->mask_low = 0;
        vol_table->phase_delay = 0;

        vol_table->count = lookup_table->count;

        for (i = 0; i < vol_table->count; i++) {
                vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
                vol_table->entries[i].smio_low = 0;
        }

        return 0;
}

/* ---- Voltage Tables ----
 * If the voltage table would be bigger than
 * what will fit into the state table on
 * the SMC keep only the higher entries.
 */
static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr *hwmgr,
                uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table)
{
        unsigned int i, diff;

        if (vol_table->count <= max_vol_steps)
                return;

        diff = vol_table->count - max_vol_steps;

        for (i = 0; i < max_vol_steps; i++)
                vol_table->entries[i] = vol_table->entries[i + diff];

        vol_table->count = max_vol_steps;

        return;
}

/**
* Create Voltage Tables.
*
* @param    hwmgr  the address of the powerplay hardware manager.
* @return   always 0
*/
static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)hwmgr->pptable;
        int result;

        if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
                result = atomctrl_get_voltage_table_v3(hwmgr,
                                VOLTAGE_TYPE_MVDDC,     VOLTAGE_OBJ_GPIO_LUT,
                                &(data->mvdd_voltage_table));
                PP_ASSERT_WITH_CODE((0 == result),
                                "Failed to retrieve MVDD table.",
                                return result);
        } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
                result = fiji_get_svi2_mvdd_voltage_table(hwmgr,
                                table_info->vdd_dep_on_mclk);
                PP_ASSERT_WITH_CODE((0 == result),
                                "Failed to retrieve SVI2 MVDD table from dependancy table.",
                                return result;);
        }

        if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
                result = atomctrl_get_voltage_table_v3(hwmgr,
                                VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
                                &(data->vddci_voltage_table));
                PP_ASSERT_WITH_CODE((0 == result),
                                "Failed to retrieve VDDCI table.",
                                return result);
        } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
                result = fiji_get_svi2_vddci_voltage_table(hwmgr,
                                table_info->vdd_dep_on_mclk);
                PP_ASSERT_WITH_CODE((0 == result),
                                "Failed to retrieve SVI2 VDDCI table from dependancy table.",
                                return result);
        }

        if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
                result = fiji_get_svi2_vdd_voltage_table(hwmgr,
                                table_info->vddc_lookup_table);
                PP_ASSERT_WITH_CODE((0 == result),
                                "Failed to retrieve SVI2 VDDC table from lookup table.",
                                return result);
        }

        PP_ASSERT_WITH_CODE(
                        (data->vddc_voltage_table.count <= (SMU73_MAX_LEVELS_VDDC)),
                        "Too many voltage values for VDDC. Trimming to fit state table.",
                        fiji_trim_voltage_table_to_fit_state_table(hwmgr,
                                        SMU73_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)));

        PP_ASSERT_WITH_CODE(
                        (data->vddci_voltage_table.count <= (SMU73_MAX_LEVELS_VDDCI)),
                        "Too many voltage values for VDDCI. Trimming to fit state table.",
                        fiji_trim_voltage_table_to_fit_state_table(hwmgr,
                                        SMU73_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)));

        PP_ASSERT_WITH_CODE(
                        (data->mvdd_voltage_table.count <= (SMU73_MAX_LEVELS_MVDD)),
                        "Too many voltage values for MVDD. Trimming to fit state table.",
                        fiji_trim_voltage_table_to_fit_state_table(hwmgr,
                                        SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)));

        return 0;
}

static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
{
        /* Program additional LP registers
         * that are no longer programmed by VBIOS
         */
        cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
                        cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
        cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
                        cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
        cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
                        cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
        cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
                        cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
        cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
                        cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
        cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
                        cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
        cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
                        cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));

        return 0;
}

/**
* Programs static screed detection parameters
*
* @param    hwmgr  the address of the powerplay hardware manager.
* @return   always 0
*/
static int fiji_program_static_screen_threshold_parameters(
                struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);

        /* Set static screen threshold unit */
        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
                        data->static_screen_threshold_unit);
        /* Set static screen threshold */
        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
                        data->static_screen_threshold);

        return 0;
}

/**
* Setup display gap for glitch free memory clock switching.
*
* @param    hwmgr  the address of the powerplay hardware manager.
* @return   always  0
*/
static int fiji_enable_display_gap(struct pp_hwmgr *hwmgr)
{
        uint32_t displayGap =
                        cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                                        ixCG_DISPLAY_GAP_CNTL);

        displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
                        DISP_GAP, DISPLAY_GAP_IGNORE);

        displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
                        DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);

        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_DISPLAY_GAP_CNTL, displayGap);

        return 0;
}

/**
* Programs activity state transition voting clients
*
* @param    hwmgr  the address of the powerplay hardware manager.
* @return   always  0
*/
static int fiji_program_voting_clients(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);

        /* Clear reset for voting clients before enabling DPM */
        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);

        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);

        return 0;
}

static int fiji_clear_voting_clients(struct pp_hwmgr *hwmgr)
{
        /* Reset voting clients before disabling DPM */
        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);

        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_0, 0);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_1, 0);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_2, 0);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_3, 0);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_4, 0);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_5, 0);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_6, 0);
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixCG_FREQ_TRAN_VOTING_7, 0);

        return 0;
}

/**
* Get the location of various tables inside the FW image.
*
* @param    hwmgr  the address of the powerplay hardware manager.
* @return   always  0
*/
static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
        uint32_t tmp;
        int result;
        bool error = false;

        result = fiji_read_smc_sram_dword(hwmgr->smumgr,
                        SMU7_FIRMWARE_HEADER_LOCATION +
                        offsetof(SMU73_Firmware_Header, DpmTable),
                        &tmp, data->sram_end);

        if (0 == result)
                data->dpm_table_start = tmp;

        error |= (0 != result);

        result = fiji_read_smc_sram_dword(hwmgr->smumgr,
                        SMU7_FIRMWARE_HEADER_LOCATION +
                        offsetof(SMU73_Firmware_Header, SoftRegisters),
                        &tmp, data->sram_end);

        if (!result) {
                data->soft_regs_start = tmp;
                smu_data->soft_regs_start = tmp;
        }

        error |= (0 != result);

        result = fiji_read_smc_sram_dword(hwmgr->smumgr,
                        SMU7_FIRMWARE_HEADER_LOCATION +
                        offsetof(SMU73_Firmware_Header, mcRegisterTable),
                        &tmp, data->sram_end);

        if (!result)
                data->mc_reg_table_start = tmp;

        result = fiji_read_smc_sram_dword(hwmgr->smumgr,
                        SMU7_FIRMWARE_HEADER_LOCATION +
                        offsetof(SMU73_Firmware_Header, FanTable),
                        &tmp, data->sram_end);

        if (!result)
                data->fan_table_start = tmp;

        error |= (0 != result);

        result = fiji_read_smc_sram_dword(hwmgr->smumgr,
                        SMU7_FIRMWARE_HEADER_LOCATION +
                        offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
                        &tmp, data->sram_end);

        if (!result)
                data->arb_table_start = tmp;

        error |= (0 != result);

        result = fiji_read_smc_sram_dword(hwmgr->smumgr,
                        SMU7_FIRMWARE_HEADER_LOCATION +
                        offsetof(SMU73_Firmware_Header, Version),
                        &tmp, data->sram_end);

        if (!result)
                hwmgr->microcode_version_info.SMC = tmp;

        error |= (0 != result);

        return error ? -1 : 0;
}

/* Copy one arb setting to another and then switch the active set.
 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 */
static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
                uint32_t arb_src, uint32_t arb_dest)
{
        uint32_t mc_arb_dram_timing;
        uint32_t mc_arb_dram_timing2;
        uint32_t burst_time;
        uint32_t mc_cg_config;

        switch (arb_src) {
        case MC_CG_ARB_FREQ_F0:
                mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
                mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
                burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
                break;
        case MC_CG_ARB_FREQ_F1:
                mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
                mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
                burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
                break;
        default:
                return -EINVAL;
        }

        switch (arb_dest) {
        case MC_CG_ARB_FREQ_F0:
                cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
                cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
                PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
                break;
        case MC_CG_ARB_FREQ_F1:
                cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
                cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
                PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
                break;
        default:
                return -EINVAL;
        }

        mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
        mc_cg_config |= 0x0000000F;
        cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
        PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);

        return 0;
}

/**
* Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value
*
* @param    hwmgr  the address of the powerplay hardware manager.
* @return   if success then 0;
*/
static int fiji_reset_to_default(struct pp_hwmgr *hwmgr)
{
        return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
}

/**
* Initial switch from ARB F0->F1
*
* @param    hwmgr  the address of the powerplay hardware manager.
* @return   always 0
* This function is to be called from the SetPowerState table.
*/
static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
{
        return fiji_copy_and_switch_arb_sets(hwmgr,
                        MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
}

static int fiji_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
{
        uint32_t tmp;

        tmp = (cgs_read_ind_register(hwmgr->device,
                        CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
                        0x0000ff00) >> 8;

        if (tmp == MC_CG_ARB_FREQ_F0)
                return 0;

        return fiji_copy_and_switch_arb_sets(hwmgr,
                        tmp, MC_CG_ARB_FREQ_F0);
}

static int fiji_reset_single_dpm_table(struct pp_hwmgr *hwmgr,
                struct fiji_single_dpm_table *dpm_table, uint32_t count)
{
        int i;
        PP_ASSERT_WITH_CODE(count <= MAX_REGULAR_DPM_NUMBER,
                        "Fatal error, can not set up single DPM table entries "
                        "to exceed max number!",);

        dpm_table->count = count;
        for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
                dpm_table->dpm_levels[i].enabled = false;

        return 0;
}

static void fiji_setup_pcie_table_entry(
        struct fiji_single_dpm_table *dpm_table,
        uint32_t index, uint32_t pcie_gen,
        uint32_t pcie_lanes)
{
        dpm_table->dpm_levels[index].value = pcie_gen;
        dpm_table->dpm_levels[index].param1 = pcie_lanes;
        dpm_table->dpm_levels[index].enabled = true;
}

static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
        uint32_t i, max_entry;

        PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
                        data->use_pcie_power_saving_levels), "No pcie performance levels!",
                        return -EINVAL);

        if (data->use_pcie_performance_levels &&
                        !data->use_pcie_power_saving_levels) {
                data->pcie_gen_power_saving = data->pcie_gen_performance;
                data->pcie_lane_power_saving = data->pcie_lane_performance;
        } else if (!data->use_pcie_performance_levels &&
                        data->use_pcie_power_saving_levels) {
                data->pcie_gen_performance = data->pcie_gen_power_saving;
                data->pcie_lane_performance = data->pcie_lane_power_saving;
        }

        fiji_reset_single_dpm_table(hwmgr,
                        &data->dpm_table.pcie_speed_table, SMU73_MAX_LEVELS_LINK);

        if (pcie_table != NULL) {
                /* max_entry is used to make sure we reserve one PCIE level
                 * for boot level (fix for A+A PSPP issue).
                 * If PCIE table from PPTable have ULV entry + 8 entries,
                 * then ignore the last entry.*/
                max_entry = (SMU73_MAX_LEVELS_LINK < pcie_table->count) ?
                                SMU73_MAX_LEVELS_LINK : pcie_table->count;
                for (i = 1; i < max_entry; i++) {
                        fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
                                        get_pcie_gen_support(data->pcie_gen_cap,
                                                        pcie_table->entries[i].gen_speed),
                                        get_pcie_lane_support(data->pcie_lane_cap,
                                                        pcie_table->entries[i].lane_width));
                }
                data->dpm_table.pcie_speed_table.count = max_entry - 1;
        } else {
                /* Hardcode Pcie Table */
                fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
                                get_pcie_gen_support(data->pcie_gen_cap,
                                                PP_Min_PCIEGen),
                                get_pcie_lane_support(data->pcie_lane_cap,
                                                PP_Max_PCIELane));
                fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
                                get_pcie_gen_support(data->pcie_gen_cap,
                                                PP_Min_PCIEGen),
                                get_pcie_lane_support(data->pcie_lane_cap,
                                                PP_Max_PCIELane));
                fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
                                get_pcie_gen_support(data->pcie_gen_cap,
                                                PP_Max_PCIEGen),
                                get_pcie_lane_support(data->pcie_lane_cap,
                                                PP_Max_PCIELane));
                fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
                                get_pcie_gen_support(data->pcie_gen_cap,
                                                PP_Max_PCIEGen),
                                get_pcie_lane_support(data->pcie_lane_cap,
                                                PP_Max_PCIELane));
                fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
                                get_pcie_gen_support(data->pcie_gen_cap,
                                                PP_Max_PCIEGen),
                                get_pcie_lane_support(data->pcie_lane_cap,
                                                PP_Max_PCIELane));
                fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
                                get_pcie_gen_support(data->pcie_gen_cap,
                                                PP_Max_PCIEGen),
                                get_pcie_lane_support(data->pcie_lane_cap,
                                                PP_Max_PCIELane));

                data->dpm_table.pcie_speed_table.count = 6;
        }
        /* Populate last level for boot PCIE level, but do not increment count. */
        fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
                        data->dpm_table.pcie_speed_table.count,
                        get_pcie_gen_support(data->pcie_gen_cap,
                                        PP_Min_PCIEGen),
                        get_pcie_lane_support(data->pcie_lane_cap,
                                        PP_Max_PCIELane));

        return 0;
}

/*
 * This function is to initalize all DPM state tables
 * for SMU7 based on the dependency table.
 * Dynamic state patching function will then trim these
 * state tables to the allowed range based
 * on the power policy or external client requests,
 * such as UVD request, etc.
 */
static int fiji_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        uint32_t i;

        struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
                        table_info->vdd_dep_on_sclk;
        struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
                        table_info->vdd_dep_on_mclk;

        PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
                        "SCLK dependency table is missing. This table is mandatory",
                        return -EINVAL);
        PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
                        "SCLK dependency table has to have is missing. "
                        "This table is mandatory",
                        return -EINVAL);

        PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
                        "MCLK dependency table is missing. This table is mandatory",
                        return -EINVAL);
        PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
                        "MCLK dependency table has to have is missing. "
                        "This table is mandatory",
                        return -EINVAL);

        /* clear the state table to reset everything to default */
        fiji_reset_single_dpm_table(hwmgr,
                        &data->dpm_table.sclk_table, SMU73_MAX_LEVELS_GRAPHICS);
        fiji_reset_single_dpm_table(hwmgr,
                        &data->dpm_table.mclk_table, SMU73_MAX_LEVELS_MEMORY);

        /* Initialize Sclk DPM table based on allow Sclk values */
        data->dpm_table.sclk_table.count = 0;
        for (i = 0; i < dep_sclk_table->count; i++) {
                if (i == 0 || data->dpm_table.sclk_table.dpm_levels
                                [data->dpm_table.sclk_table.count - 1].value !=
                                                dep_sclk_table->entries[i].clk) {
                        data->dpm_table.sclk_table.dpm_levels
                        [data->dpm_table.sclk_table.count].value =
                                        dep_sclk_table->entries[i].clk;
                        data->dpm_table.sclk_table.dpm_levels
                        [data->dpm_table.sclk_table.count].enabled =
                                        (i == 0) ? true : false;
                        data->dpm_table.sclk_table.count++;
                }
        }

        /* Initialize Mclk DPM table based on allow Mclk values */
        data->dpm_table.mclk_table.count = 0;
        for (i=0; i<dep_mclk_table->count; i++) {
                if ( i==0 || data->dpm_table.mclk_table.dpm_levels
                                [data->dpm_table.mclk_table.count - 1].value !=
                                                dep_mclk_table->entries[i].clk) {
                        data->dpm_table.mclk_table.dpm_levels
                        [data->dpm_table.mclk_table.count].value =
                                        dep_mclk_table->entries[i].clk;
                        data->dpm_table.mclk_table.dpm_levels
                        [data->dpm_table.mclk_table.count].enabled =
                                        (i == 0) ? true : false;
                        data->dpm_table.mclk_table.count++;
                }
        }

        /* setup PCIE gen speed levels */
        fiji_setup_default_pcie_table(hwmgr);

        /* save a copy of the default DPM table */
        memcpy(&(data->golden_dpm_table), &(data->dpm_table),
                        sizeof(struct fiji_dpm_table));

        return 0;
}

/**
 * @brief PhwFiji_GetVoltageOrder
 *  Returns index of requested voltage record in lookup(table)
 * @param lookup_table - lookup list to search in
 * @param voltage - voltage to look for
 * @return 0 on success
 */
uint8_t fiji_get_voltage_index(
                struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
{
        uint8_t count = (uint8_t) (lookup_table->count);
        uint8_t i;

        PP_ASSERT_WITH_CODE((NULL != lookup_table),
                        "Lookup Table empty.", return 0);
        PP_ASSERT_WITH_CODE((0 != count),
                        "Lookup Table empty.", return 0);

        for (i = 0; i < lookup_table->count; i++) {
                /* find first voltage equal or bigger than requested */
                if (lookup_table->entries[i].us_vdd >= voltage)
                        return i;
        }
        /* voltage is bigger than max voltage in the table */
        return i - 1;
}

/**
* Preparation of vddc and vddgfx CAC tables for SMC.
*
* @param    hwmgr  the address of the hardware manager
* @param    table  the SMC DPM table structure to be populated
* @return   always 0
*/
static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
                struct SMU73_Discrete_DpmTable *table)
{
        uint32_t count;
        uint8_t index;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        struct phm_ppt_v1_voltage_lookup_table *lookup_table =
                        table_info->vddc_lookup_table;
        /* tables is already swapped, so in order to use the value from it,
         * we need to swap it back.
         * We are populating vddc CAC data to BapmVddc table
         * in split and merged mode
         */
        for( count = 0; count<lookup_table->count; count++) {
                index = fiji_get_voltage_index(lookup_table,
                                data->vddc_voltage_table.entries[count].value);
                table->BapmVddcVidLoSidd[count] = (uint8_t) ((6200 -
                                (lookup_table->entries[index].us_cac_low *
                                                VOLTAGE_SCALE)) / 25);
                table->BapmVddcVidHiSidd[count] = (uint8_t) ((6200 -
                                (lookup_table->entries[index].us_cac_high *
                                                VOLTAGE_SCALE)) / 25);
        }

        return 0;
}

/**
* Preparation of voltage tables for SMC.
*
* @param    hwmgr   the address of the hardware manager
* @param    table   the SMC DPM table structure to be populated
* @return   always  0
*/

int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
                struct SMU73_Discrete_DpmTable *table)
{
        int result;

        result = fiji_populate_cac_table(hwmgr, table);
        PP_ASSERT_WITH_CODE(0 == result,
                        "can not populate CAC voltage tables to SMC",
                        return -EINVAL);

        return 0;
}

static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
                struct SMU73_Discrete_Ulv *state)
{
        int result = 0;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);

        state->CcPwrDynRm = 0;
        state->CcPwrDynRm1 = 0;

        state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
        state->VddcOffsetVid = (uint8_t)( table_info->us_ulv_voltage_offset *
                        VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1 );

        state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;

        if (!result) {
                CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
                CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
                CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
        }
        return result;
}

static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
                struct SMU73_Discrete_DpmTable *table)
{
        return fiji_populate_ulv_level(hwmgr, &table->Ulv);
}

static int32_t fiji_get_dpm_level_enable_mask_value(
                struct fiji_single_dpm_table* dpm_table)
{
        int32_t i;
        int32_t mask = 0;

        for (i = dpm_table->count; i > 0; i--) {
                mask = mask << 1;
                if (dpm_table->dpm_levels[i - 1].enabled)
                        mask |= 0x1;
                else
                        mask &= 0xFFFFFFFE;
        }
        return mask;
}

static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
                struct SMU73_Discrete_DpmTable *table)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct fiji_dpm_table *dpm_table = &data->dpm_table;
        int i;

        /* Index (dpm_table->pcie_speed_table.count)
         * is reserved for PCIE boot level. */
        for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
                table->LinkLevel[i].PcieGenSpeed  =
                                (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
                table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
                                dpm_table->pcie_speed_table.dpm_levels[i].param1);
                table->LinkLevel[i].EnabledForActivity = 1;
                table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
                table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
                table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
        }

        data->smc_state_table.LinkLevelCount =
                        (uint8_t)dpm_table->pcie_speed_table.count;
        data->dpm_level_enable_mask.pcie_dpm_enable_mask =
                        fiji_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);

        return 0;
}

/**
* Calculates the SCLK dividers using the provided engine clock
*
* @param    hwmgr  the address of the hardware manager
* @param    clock  the engine clock to use to populate the structure
* @param    sclk   the SMC SCLK structure to be populated
*/
static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
                uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
{
        const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct pp_atomctrl_clock_dividers_vi dividers;
        uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
        uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
        uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
        uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
        uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
        uint32_t ref_clock;
        uint32_t ref_divider;
        uint32_t fbdiv;
        int result;

        /* get the engine clock dividers for this clock value */
        result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);

        PP_ASSERT_WITH_CODE(result == 0,
                        "Error retrieving Engine Clock dividers from VBIOS.",
                        return result);

        /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
        ref_clock = atomctrl_get_reference_clock(hwmgr);
        ref_divider = 1 + dividers.uc_pll_ref_div;

        /* low 14 bits is fraction and high 12 bits is divider */
        fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;

        /* SPLL_FUNC_CNTL setup */
        spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
                        SPLL_REF_DIV, dividers.uc_pll_ref_div);
        spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
                        SPLL_PDIV_A,  dividers.uc_pll_post_div);

        /* SPLL_FUNC_CNTL_3 setup*/
        spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
                        SPLL_FB_DIV, fbdiv);

        /* set to use fractional accumulation*/
        spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
                        SPLL_DITHEN, 1);

        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                                PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
                struct pp_atomctrl_internal_ss_info ssInfo;

                uint32_t vco_freq = clock * dividers.uc_pll_post_div;
                if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
                                vco_freq, &ssInfo)) {
                        /*
                         * ss_info.speed_spectrum_percentage -- in unit of 0.01%
                         * ss_info.speed_spectrum_rate -- in unit of khz
                         *
                         * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
                         */
                        uint32_t clk_s = ref_clock * 5 /
                                        (ref_divider * ssInfo.speed_spectrum_rate);
                        /* clkv = 2 * D * fbdiv / NS */
                        uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
                                        fbdiv / (clk_s * 10000);

                        cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
                                        CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
                        cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
                                        CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
                        cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
                                        CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
                }
        }

        sclk->SclkFrequency        = clock;
        sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
        sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
        sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
        sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
        sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;

        return 0;
}

static uint16_t fiji_find_closest_vddci(struct pp_hwmgr *hwmgr, uint16_t vddci)
{
        uint32_t  i;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct pp_atomctrl_voltage_table *vddci_table =
                        &(data->vddci_voltage_table);

        for (i = 0; i < vddci_table->count; i++) {
                if (vddci_table->entries[i].value >= vddci)
                        return vddci_table->entries[i].value;
        }

        PP_ASSERT_WITH_CODE(false,
                        "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
                        return vddci_table->entries[i-1].value);
}

static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
                struct phm_ppt_v1_clock_voltage_dependency_table* dep_table,
                uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
{
        uint32_t i;
        uint16_t vddci;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);

        *voltage = *mvdd = 0;

        /* clock - voltage dependency table is empty table */
        if (dep_table->count == 0)
                return -EINVAL;

        for (i = 0; i < dep_table->count; i++) {
                /* find first sclk bigger than request */
                if (dep_table->entries[i].clk >= clock) {
                        *voltage |= (dep_table->entries[i].vddc *
                                        VOLTAGE_SCALE) << VDDC_SHIFT;
                        if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
                                *voltage |= (data->vbios_boot_state.vddci_bootup_value *
                                                VOLTAGE_SCALE) << VDDCI_SHIFT;
                        else if (dep_table->entries[i].vddci)
                                *voltage |= (dep_table->entries[i].vddci *
                                                VOLTAGE_SCALE) << VDDCI_SHIFT;
                        else {
                                vddci = fiji_find_closest_vddci(hwmgr,
                                                (dep_table->entries[i].vddc -
                                                                (uint16_t)data->vddc_vddci_delta));
                                *voltage |= (vddci * VOLTAGE_SCALE) <<  VDDCI_SHIFT;
                        }

                        if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
                                *mvdd = data->vbios_boot_state.mvdd_bootup_value *
                                        VOLTAGE_SCALE;
                        else if (dep_table->entries[i].mvdd)
                                *mvdd = (uint32_t) dep_table->entries[i].mvdd *
                                        VOLTAGE_SCALE;

                        *voltage |= 1 << PHASES_SHIFT;
                        return 0;
                }
        }

        /* sclk is bigger than max sclk in the dependence table */
        *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;

        if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
                *voltage |= (data->vbios_boot_state.vddci_bootup_value *
                                VOLTAGE_SCALE) << VDDCI_SHIFT;
        else if (dep_table->entries[i-1].vddci) {
                vddci = fiji_find_closest_vddci(hwmgr,
                                (dep_table->entries[i].vddc -
                                                (uint16_t)data->vddc_vddci_delta));
                *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
        }

        if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
                *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
        else if (dep_table->entries[i].mvdd)
                *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;

        return 0;
}

static uint8_t fiji_get_sleep_divider_id_from_clock(uint32_t clock,
                uint32_t clock_insr)
{
        uint8_t i;
        uint32_t temp;
        uint32_t min = max(clock_insr, (uint32_t)FIJI_MINIMUM_ENGINE_CLOCK);

        PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
        for (i = FIJI_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
                temp = clock >> i;

                if (temp >= min || i == 0)
                        break;
        }
        return i;
}
/**
* Populates single SMC SCLK structure using the provided engine clock
*
* @param    hwmgr      the address of the hardware manager
* @param    clock the engine clock to use to populate the structure
* @param    sclk        the SMC SCLK structure to be populated
*/

static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
                uint32_t clock, uint16_t sclk_al_threshold,
                struct SMU73_Discrete_GraphicsLevel *level)
{
        int result;
        /* PP_Clocks minClocks; */
        uint32_t threshold, mvdd;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);

        result = fiji_calculate_sclk_params(hwmgr, clock, level);

        /* populate graphics levels */
        result = fiji_get_dependency_volt_by_clk(hwmgr,
                        table_info->vdd_dep_on_sclk, clock,
                        &level->MinVoltage, &mvdd);
        PP_ASSERT_WITH_CODE((0 == result),
                        "can not find VDDC voltage value for "
                        "VDDC engine clock dependency table",
                        return result);

        level->SclkFrequency = clock;
        level->ActivityLevel = sclk_al_threshold;
        level->CcPwrDynRm = 0;
        level->CcPwrDynRm1 = 0;
        level->EnabledForActivity = 0;
        level->EnabledForThrottle = 1;
        level->UpHyst = 10;
        level->DownHyst = 0;
        level->VoltageDownHyst = 0;
        level->PowerThrottle = 0;

        threshold = clock * data->fast_watermark_threshold / 100;


        data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;

        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
                level->DeepSleepDivId = fiji_get_sleep_divider_id_from_clock(clock,
                                                                hwmgr->display_config.min_core_set_clock_in_sr);


        /* Default to slow, highest DPM level will be
         * set to PPSMC_DISPLAY_WATERMARK_LOW later.
         */
        level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;

        CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
        CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
        CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
        CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
        CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
        CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
        CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
        CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
        CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);

        return 0;
}
/**
* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
*
* @param    hwmgr      the address of the hardware manager
*/
static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct fiji_dpm_table *dpm_table = &data->dpm_table;
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
        uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
        int result = 0;
        uint32_t array = data->dpm_table_start +
                        offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
        uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
                        SMU73_MAX_LEVELS_GRAPHICS;
        struct SMU73_Discrete_GraphicsLevel *levels =
                        data->smc_state_table.GraphicsLevel;
        uint32_t i, max_entry;
        uint8_t hightest_pcie_level_enabled = 0,
                        lowest_pcie_level_enabled = 0,
                        mid_pcie_level_enabled = 0,
                        count = 0;

        for (i = 0; i < dpm_table->sclk_table.count; i++) {
                result = fiji_populate_single_graphic_level(hwmgr,
                                dpm_table->sclk_table.dpm_levels[i].value,
                                (uint16_t)data->activity_target[i],
                                &levels[i]);
                if (result)
                        return result;

                /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
                if (i > 1)
                        levels[i].DeepSleepDivId = 0;
        }

        /* Only enable level 0 for now.*/
        levels[0].EnabledForActivity = 1;

        /* set highest level watermark to high */
        levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
                        PPSMC_DISPLAY_WATERMARK_HIGH;

        data->smc_state_table.GraphicsDpmLevelCount =
                        (uint8_t)dpm_table->sclk_table.count;
        data->dpm_level_enable_mask.sclk_dpm_enable_mask =
                        fiji_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);

        if (pcie_table != NULL) {
                PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
                                "There must be 1 or more PCIE levels defined in PPTable.",
                                return -EINVAL);
                max_entry = pcie_entry_cnt - 1;
                for (i = 0; i < dpm_table->sclk_table.count; i++)
                        levels[i].pcieDpmLevel =
                                        (uint8_t) ((i < max_entry)? i : max_entry);
        } else {
                while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
                                ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
                                                (1 << (hightest_pcie_level_enabled + 1))) != 0 ))
                        hightest_pcie_level_enabled++;

                while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
                                ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
                                                (1 << lowest_pcie_level_enabled)) == 0 ))
                        lowest_pcie_level_enabled++;

                while ((count < hightest_pcie_level_enabled) &&
                                ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
                                                (1 << (lowest_pcie_level_enabled + 1 + count))) == 0 ))
                        count++;

                mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1+ count) <
                                hightest_pcie_level_enabled?
                                                (lowest_pcie_level_enabled + 1 + count) :
                                                hightest_pcie_level_enabled;

                /* set pcieDpmLevel to hightest_pcie_level_enabled */
                for(i = 2; i < dpm_table->sclk_table.count; i++)
                        levels[i].pcieDpmLevel = hightest_pcie_level_enabled;

                /* set pcieDpmLevel to lowest_pcie_level_enabled */
                levels[0].pcieDpmLevel = lowest_pcie_level_enabled;

                /* set pcieDpmLevel to mid_pcie_level_enabled */
                levels[1].pcieDpmLevel = mid_pcie_level_enabled;
        }
        /* level count will send to smc once at init smc table and never change */
        result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
                        (uint32_t)array_size, data->sram_end);

        return result;
}

/**
 * MCLK Frequency Ratio
 * SEQ_CG_RESP  Bit[31:24] - 0x0
 * Bit[27:24] \96 DDR3 Frequency ratio
 * 0x0 <= 100MHz,       450 < 0x8 <= 500MHz
 * 100 < 0x1 <= 150MHz,       500 < 0x9 <= 550MHz
 * 150 < 0x2 <= 200MHz,       550 < 0xA <= 600MHz
 * 200 < 0x3 <= 250MHz,       600 < 0xB <= 650MHz
 * 250 < 0x4 <= 300MHz,       650 < 0xC <= 700MHz
 * 300 < 0x5 <= 350MHz,       700 < 0xD <= 750MHz
 * 350 < 0x6 <= 400MHz,       750 < 0xE <= 800MHz
 * 400 < 0x7 <= 450MHz,       800 < 0xF
 */
static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
{
        if (mem_clock <= 10000) return 0x0;
        if (mem_clock <= 15000) return 0x1;
        if (mem_clock <= 20000) return 0x2;
        if (mem_clock <= 25000) return 0x3;
        if (mem_clock <= 30000) return 0x4;
        if (mem_clock <= 35000) return 0x5;
        if (mem_clock <= 40000) return 0x6;
        if (mem_clock <= 45000) return 0x7;
        if (mem_clock <= 50000) return 0x8;
        if (mem_clock <= 55000) return 0x9;
        if (mem_clock <= 60000) return 0xa;
        if (mem_clock <= 65000) return 0xb;
        if (mem_clock <= 70000) return 0xc;
        if (mem_clock <= 75000) return 0xd;
        if (mem_clock <= 80000) return 0xe;
        /* mem_clock > 800MHz */
        return 0xf;
}

/**
* Populates the SMC MCLK structure using the provided memory clock
*
* @param    hwmgr   the address of the hardware manager
* @param    clock   the memory clock to use to populate the structure
* @param    sclk    the SMC SCLK structure to be populated
*/
static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
    uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
{
        struct pp_atomctrl_memory_clock_param mem_param;
        int result;

        result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
        PP_ASSERT_WITH_CODE((0 == result),
                        "Failed to get Memory PLL Dividers.",);

        /* Save the result data to outpupt memory level structure */
        mclk->MclkFrequency   = clock;
        mclk->MclkDivider     = (uint8_t)mem_param.mpll_post_divider;
        mclk->FreqRange       = fiji_get_mclk_frequency_ratio(clock);

        return result;
}

static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
                uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        int result = 0;

        if (table_info->vdd_dep_on_mclk) {
                result = fiji_get_dependency_volt_by_clk(hwmgr,
                                table_info->vdd_dep_on_mclk, clock,
                                &mem_level->MinVoltage, &mem_level->MinMvdd);
                PP_ASSERT_WITH_CODE((0 == result),
                                "can not find MinVddc voltage value from memory "
                                "VDDC voltage dependency table", return result);
        }

        mem_level->EnabledForThrottle = 1;
        mem_level->EnabledForActivity = 0;
        mem_level->UpHyst = 0;
        mem_level->DownHyst = 100;
        mem_level->VoltageDownHyst = 0;
        mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
        mem_level->StutterEnable = false;

        mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;

        /* enable stutter mode if all the follow condition applied
         * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
         * &(data->DisplayTiming.numExistingDisplays));
         */
        data->display_timing.num_existing_displays = 1;

        if ((data->mclk_stutter_mode_threshold) &&
                (clock <= data->mclk_stutter_mode_threshold) &&
                (!data->is_uvd_enabled) &&
                (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
                                STUTTER_ENABLE) & 0x1))
                mem_level->StutterEnable = true;

        result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
        if (!result) {
                CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
                CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
                CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
                CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
        }
        return result;
}

/**
* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
*
* @param    hwmgr      the address of the hardware manager
*/
static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct fiji_dpm_table *dpm_table = &data->dpm_table;
        int result;
        /* populate MCLK dpm table to SMU7 */
        uint32_t array = data->dpm_table_start +
                        offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
        uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
                        SMU73_MAX_LEVELS_MEMORY;
        struct SMU73_Discrete_MemoryLevel *levels =
                        data->smc_state_table.MemoryLevel;
        uint32_t i;

        for (i = 0; i < dpm_table->mclk_table.count; i++) {
                PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
                                "can not populate memory level as memory clock is zero",
                                return -EINVAL);
                result = fiji_populate_single_memory_level(hwmgr,
                                dpm_table->mclk_table.dpm_levels[i].value,
                                &levels[i]);
                if (result)
                        return result;
        }

        /* Only enable level 0 for now. */
        levels[0].EnabledForActivity = 1;

        /* in order to prevent MC activity from stutter mode to push DPM up.
         * the UVD change complements this by putting the MCLK in
         * a higher state by default such that we are not effected by
         * up threshold or and MCLK DPM latency.
         */
        levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
        CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);

        data->smc_state_table.MemoryDpmLevelCount =
                        (uint8_t)dpm_table->mclk_table.count;
        data->dpm_level_enable_mask.mclk_dpm_enable_mask =
                        fiji_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
        /* set highest level watermark to high */
        levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
                        PPSMC_DISPLAY_WATERMARK_HIGH;

        /* level count will send to smc once at init smc table and never change */
        result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
                        (uint32_t)array_size, data->sram_end);

        return result;
}

/**
* Populates the SMC MVDD structure using the provided memory clock.
*
* @param    hwmgr      the address of the hardware manager
* @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
* @param    voltage     the SMC VOLTAGE structure to be populated
*/
int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
                uint32_t mclk, SMIO_Pattern *smio_pat)
{
        const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        uint32_t i = 0;

        if (FIJI_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
                /* find mvdd value which clock is more than request */
                for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
                        if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
                                smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
                                break;
                        }
                }
                PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
                                "MVDD Voltage is outside the supported range.",
                                return -EINVAL);
        } else
                return -EINVAL;

        return 0;
}

static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
                SMU73_Discrete_DpmTable *table)
{
        int result = 0;
        const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        struct pp_atomctrl_clock_dividers_vi dividers;
        SMIO_Pattern vol_level;
        uint32_t mvdd;
        uint16_t us_mvdd;
        uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
        uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;

        table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;

        if (!data->sclk_dpm_key_disabled) {
                /* Get MinVoltage and Frequency from DPM0,
                 * already converted to SMC_UL */
                table->ACPILevel.SclkFrequency =
                                data->dpm_table.sclk_table.dpm_levels[0].value;
                result = fiji_get_dependency_volt_by_clk(hwmgr,
                                table_info->vdd_dep_on_sclk,
                                table->ACPILevel.SclkFrequency,
                                &table->ACPILevel.MinVoltage, &mvdd);
                PP_ASSERT_WITH_CODE((0 == result),
                                "Cannot find ACPI VDDC voltage value "
                                "in Clock Dependency Table",);
        } else {
                table->ACPILevel.SclkFrequency =
                                data->vbios_boot_state.sclk_bootup_value;
                table->ACPILevel.MinVoltage =
                                data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
        }

        /* get the engine clock dividers for this clock value */
        result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
                        table->ACPILevel.SclkFrequency,  &dividers);
        PP_ASSERT_WITH_CODE(result == 0,
                        "Error retrieving Engine Clock dividers from VBIOS.",
                        return result);

        table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
        table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
        table->ACPILevel.DeepSleepDivId = 0;

        spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
                        SPLL_PWRON, 0);
        spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
                        SPLL_RESET, 1);
        spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
                        SCLK_MUX_SEL, 4);

        table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
        table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
        table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
        table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
        table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
        table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
        table->ACPILevel.CcPwrDynRm = 0;
        table->ACPILevel.CcPwrDynRm1 = 0;

        CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
        CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
        CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
        CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
        CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
        CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
        CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
        CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
        CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
        CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
        CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);

        if (!data->mclk_dpm_key_disabled) {
                /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
                table->MemoryACPILevel.MclkFrequency =
                                data->dpm_table.mclk_table.dpm_levels[0].value;
                result = fiji_get_dependency_volt_by_clk(hwmgr,
                                table_info->vdd_dep_on_mclk,
                                table->MemoryACPILevel.MclkFrequency,
                                &table->MemoryACPILevel.MinVoltage, &mvdd);
                PP_ASSERT_WITH_CODE((0 == result),
                                "Cannot find ACPI VDDCI voltage value "
                                "in Clock Dependency Table",);
        } else {
                table->MemoryACPILevel.MclkFrequency =
                                data->vbios_boot_state.mclk_bootup_value;
                table->MemoryACPILevel.MinVoltage =
                                data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
        }

        us_mvdd = 0;
        if ((FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
                        (data->mclk_dpm_key_disabled))
                us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
        else {
                if (!fiji_populate_mvdd_value(hwmgr,
                                data->dpm_table.mclk_table.dpm_levels[0].value,
                                &vol_level))
                        us_mvdd = vol_level.Voltage;
        }

        table->MemoryACPILevel.MinMvdd =
                        PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);

        table->MemoryACPILevel.EnabledForThrottle = 0;
        table->MemoryACPILevel.EnabledForActivity = 0;
        table->MemoryACPILevel.UpHyst = 0;
        table->MemoryACPILevel.DownHyst = 100;
        table->MemoryACPILevel.VoltageDownHyst = 0;
        table->MemoryACPILevel.ActivityLevel =
                        PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);

        table->MemoryACPILevel.StutterEnable = false;
        CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
        CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);

        return result;
}

static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
                SMU73_Discrete_DpmTable *table)
{
        int result = -EINVAL;
        uint8_t count;
        struct pp_atomctrl_clock_dividers_vi dividers;
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
                        table_info->mm_dep_table;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);

        table->VceLevelCount = (uint8_t)(mm_table->count);
        table->VceBootLevel = 0;

        for(count = 0; count < table->VceLevelCount; count++) {
                table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
                table->VceLevel[count].MinVoltage = 0;
                table->VceLevel[count].MinVoltage |=
                                (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
                table->VceLevel[count].MinVoltage |=
                                ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
                                                VOLTAGE_SCALE) << VDDCI_SHIFT;
                table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;

                /*retrieve divider value for VBIOS */
                result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
                                table->VceLevel[count].Frequency, &dividers);
                PP_ASSERT_WITH_CODE((0 == result),
                                "can not find divide id for VCE engine clock",
                                return result);

                table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

                CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
                CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
        }
        return result;
}

static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
                SMU73_Discrete_DpmTable *table)
{
        int result = -EINVAL;
        uint8_t count;
        struct pp_atomctrl_clock_dividers_vi dividers;
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
                        table_info->mm_dep_table;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);

        table->AcpLevelCount = (uint8_t)(mm_table->count);
        table->AcpBootLevel = 0;

        for (count = 0; count < table->AcpLevelCount; count++) {
                table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
                table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
                                VOLTAGE_SCALE) << VDDC_SHIFT;
                table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
                                data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
                table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;

                /* retrieve divider value for VBIOS */
                result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
                                table->AcpLevel[count].Frequency, &dividers);
                PP_ASSERT_WITH_CODE((0 == result),
                                "can not find divide id for engine clock", return result);

                table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

                CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
                CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
        }
        return result;
}

static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
                SMU73_Discrete_DpmTable *table)
{
        int result = -EINVAL;
        uint8_t count;
        struct pp_atomctrl_clock_dividers_vi dividers;
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
                        table_info->mm_dep_table;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);

        table->SamuBootLevel = 0;
        table->SamuLevelCount = (uint8_t)(mm_table->count);

        for (count = 0; count < table->SamuLevelCount; count++) {
                /* not sure whether we need evclk or not */
                table->SamuLevel[count].MinVoltage = 0;
                table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
                table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
                                VOLTAGE_SCALE) << VDDC_SHIFT;
                table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
                                data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
                table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;

                /* retrieve divider value for VBIOS */
                result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
                                table->SamuLevel[count].Frequency, &dividers);
                PP_ASSERT_WITH_CODE((0 == result),
                                "can not find divide id for samu clock", return result);

                table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

                CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
                CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
        }
        return result;
}

static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
                int32_t eng_clock, int32_t mem_clock,
                struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
{
        uint32_t dram_timing;
        uint32_t dram_timing2;
        uint32_t burstTime;
        ULONG state, trrds, trrdl;
        int result;

        result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
                        eng_clock, mem_clock);
        PP_ASSERT_WITH_CODE(result == 0,
                        "Error calling VBIOS to set DRAM_TIMING.", return result);

        dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
        dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
        burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);

        state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
        trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
        trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);

        arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
        arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
        arb_regs->McArbBurstTime   = (uint8_t)burstTime;
        arb_regs->TRRDS            = (uint8_t)trrds;
        arb_regs->TRRDL            = (uint8_t)trrdl;

        return 0;
}

static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
        uint32_t i, j;
        int result = 0;

        for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
                for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
                        result = fiji_populate_memory_timing_parameters(hwmgr,
                                        data->dpm_table.sclk_table.dpm_levels[i].value,
                                        data->dpm_table.mclk_table.dpm_levels[j].value,
                                        &arb_regs.entries[i][j]);
                        if (result)
                                break;
                }
        }

        if (!result)
                result = fiji_copy_bytes_to_smc(
                                hwmgr->smumgr,
                                data->arb_table_start,
                                (uint8_t *)&arb_regs,
                                sizeof(SMU73_Discrete_MCArbDramTimingTable),
                                data->sram_end);
        return result;
}

static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
                struct SMU73_Discrete_DpmTable *table)
{
        int result = -EINVAL;
        uint8_t count;
        struct pp_atomctrl_clock_dividers_vi dividers;
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
                        table_info->mm_dep_table;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);

        table->UvdLevelCount = (uint8_t)(mm_table->count);
        table->UvdBootLevel = 0;

        for (count = 0; count < table->UvdLevelCount; count++) {
                table->UvdLevel[count].MinVoltage = 0;
                table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
                table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
                table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
                                VOLTAGE_SCALE) << VDDC_SHIFT;
                table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
                                data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
                table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;

                /* retrieve divider value for VBIOS */
                result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
                                table->UvdLevel[count].VclkFrequency, &dividers);
                PP_ASSERT_WITH_CODE((0 == result),
                                "can not find divide id for Vclk clock", return result);

                table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

                result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
                                table->UvdLevel[count].DclkFrequency, &dividers);
                PP_ASSERT_WITH_CODE((0 == result),
                                "can not find divide id for Dclk clock", return result);

                table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

                CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
                CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
                CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);

        }
        return result;
}

static int fiji_find_boot_level(struct fiji_single_dpm_table *table,
                uint32_t value, uint32_t *boot_level)
{
        int result = -EINVAL;
        uint32_t i;

        for (i = 0; i < table->count; i++) {
                if (value == table->dpm_levels[i].value) {
                        *boot_level = i;
                        result = 0;
                }
        }
        return result;
}

static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
                struct SMU73_Discrete_DpmTable *table)
{
        int result = 0;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);

        table->GraphicsBootLevel = 0;
        table->MemoryBootLevel = 0;

        /* find boot level from dpm table */
        result = fiji_find_boot_level(&(data->dpm_table.sclk_table),
                        data->vbios_boot_state.sclk_bootup_value,
                        (uint32_t *)&(table->GraphicsBootLevel));

        result = fiji_find_boot_level(&(data->dpm_table.mclk_table),
                        data->vbios_boot_state.mclk_bootup_value,
                        (uint32_t *)&(table->MemoryBootLevel));

        table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
                        VOLTAGE_SCALE;
        table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
                        VOLTAGE_SCALE;
        table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
                        VOLTAGE_SCALE;

        CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
        CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
        CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);

        return 0;
}

static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        uint8_t count, level;

        count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
        for (level = 0; level < count; level++) {
                if(table_info->vdd_dep_on_sclk->entries[level].clk >=
                                data->vbios_boot_state.sclk_bootup_value) {
                        data->smc_state_table.GraphicsBootLevel = level;
                        break;
                }
        }

        count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
        for (level = 0; level < count; level++) {
                if(table_info->vdd_dep_on_mclk->entries[level].clk >=
                                data->vbios_boot_state.mclk_bootup_value) {
                        data->smc_state_table.MemoryBootLevel = level;
                        break;
                }
        }

        return 0;
}

static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
{
        uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
                        volt_with_cks, value;
        uint16_t clock_freq_u16;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
                        volt_offset = 0;
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
                        table_info->vdd_dep_on_sclk;

        stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;

        /* Read SMU_Eefuse to read and calculate RO and determine
         * if the part is SS or FF. if RO >= 1660MHz, part is FF.
         */
        efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixSMU_EFUSE_0 + (146 * 4));
        efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixSMU_EFUSE_0 + (148 * 4));
        efuse &= 0xFF000000;
        efuse = efuse >> 24;
        efuse2 &= 0xF;

        if (efuse2 == 1)
                ro = (2300 - 1350) * efuse / 255 + 1350;
        else
                ro = (2500 - 1000) * efuse / 255 + 1000;

        if (ro >= 1660)
                type = 0;
        else
                type = 1;

        /* Populate Stretch amount */
        data->smc_state_table.ClockStretcherAmount = stretch_amount;

        /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
        for (i = 0; i < sclk_table->count; i++) {
                data->smc_state_table.Sclk_CKS_masterEn0_7 |=
                                sclk_table->entries[i].cks_enable << i;
                volt_without_cks = (uint32_t)((14041 *
                        (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
                        (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
                volt_with_cks = (uint32_t)((13946 *
                        (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
                        (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
                if (volt_without_cks >= volt_with_cks)
                        volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
                                        sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
                data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
        }

        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
                        STRETCH_ENABLE, 0x0);
        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
                        masterReset, 0x1);
        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
                        staticEnable, 0x1);
        PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
                        masterReset, 0x0);

        /* Populate CKS Lookup Table */
        if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
                stretch_amount2 = 0;
        else if (stretch_amount == 3 || stretch_amount == 4)
                stretch_amount2 = 1;
        else {
                phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
                                PHM_PlatformCaps_ClockStretcher);
                PP_ASSERT_WITH_CODE(false,
                                "Stretch Amount in PPTable not supported\n",
                                return -EINVAL);
        }

        value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixPWR_CKS_CNTL);
        value &= 0xFFC2FF87;
        data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
                        fiji_clock_stretcher_lookup_table[stretch_amount2][0];
        data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
                        fiji_clock_stretcher_lookup_table[stretch_amount2][1];
        clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
                        GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].
                        SclkFrequency) / 100);
        if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
                        clock_freq_u16 &&
            fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
                        clock_freq_u16) {
                /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
                value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
                /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
                value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
                /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
                value |= (fiji_clock_stretch_amount_conversion
                                [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
                                 [stretch_amount]) << 3;
        }
        CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
                        CKS_LOOKUPTableEntry[0].minFreq);
        CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
                        CKS_LOOKUPTableEntry[0].maxFreq);
        data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
                        fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
        data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
                        (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;

        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixPWR_CKS_CNTL, value);

        /* Populate DDT Lookup Table */
        for (i = 0; i < 4; i++) {
                /* Assign the minimum and maximum VID stored
                 * in the last row of Clock Stretcher Voltage Table.
                 */
                data->smc_state_table.ClockStretcherDataTable.
                ClockStretcherDataTableEntry[i].minVID =
                                (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
                data->smc_state_table.ClockStretcherDataTable.
                ClockStretcherDataTableEntry[i].maxVID =
                                (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
                /* Loop through each SCLK and check the frequency
                 * to see if it lies within the frequency for clock stretcher.
                 */
                for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
                        cks_setting = 0;
                        clock_freq = PP_SMC_TO_HOST_UL(
                                        data->smc_state_table.GraphicsLevel[j].SclkFrequency);
                        /* Check the allowed frequency against the sclk level[j].
                         *  Sclk's endianness has already been converted,
                         *  and it's in 10Khz unit,
                         *  as opposed to Data table, which is in Mhz unit.
                         */
                        if (clock_freq >=
                                        (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
                                cks_setting |= 0x2;
                                if (clock_freq <
                                                (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
                                        cks_setting |= 0x1;
                        }
                        data->smc_state_table.ClockStretcherDataTable.
                        ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
                }
                CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.
                                ClockStretcherDataTable.
                                ClockStretcherDataTableEntry[i].setting);
        }

        value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
        value &= 0xFFFFFFFE;
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);

        return 0;
}

/**
* Populates the SMC VRConfig field in DPM table.
*
* @param    hwmgr   the address of the hardware manager
* @param    table   the SMC DPM table structure to be populated
* @return   always 0
*/
static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
                struct SMU73_Discrete_DpmTable *table)
{
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        uint16_t config;

        config = VR_MERGED_WITH_VDDC;
        table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);

        /* Set Vddc Voltage Controller */
        if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
                config = VR_SVI2_PLANE_1;
                table->VRConfig |= config;
        } else {
                PP_ASSERT_WITH_CODE(false,
                                "VDDC should be on SVI2 control in merged mode!",);
        }
        /* Set Vddci Voltage Controller */
        if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
                config = VR_SVI2_PLANE_2;  /* only in merged mode */
                table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
        } else if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
                config = VR_SMIO_PATTERN_1;
                table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
        } else {
                config = VR_STATIC_VOLTAGE;
                table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
        }
        /* Set Mvdd Voltage Controller */
        if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
                config = VR_SVI2_PLANE_2;
                table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
        } else if(FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
                config = VR_SMIO_PATTERN_2;
                table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
        } else {
                config = VR_STATIC_VOLTAGE;
                table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
        }

        return 0;
}

/**
* Initializes the SMC table and uploads it
*
* @param    hwmgr  the address of the powerplay hardware manager.
* @param    pInput  the pointer to input data (PowerState)
* @return   always 0
*/
static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
{
        int result;
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
        struct SMU73_Discrete_DpmTable *table = &(data->smc_state_table);
        const struct fiji_ulv_parm *ulv = &(data->ulv);
        uint8_t i;
        struct pp_atomctrl_gpio_pin_assignment gpio_pin;

        result = fiji_setup_default_dpm_tables(hwmgr);
        PP_ASSERT_WITH_CODE(0 == result,
                        "Failed to setup default DPM tables!", return result);

        if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
                fiji_populate_smc_voltage_tables(hwmgr, table);

        table->SystemFlags = 0;

        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_AutomaticDCTransition))
                table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_StepVddc))
                table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

        if (data->is_memory_gddr5)
                table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

        if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
                result = fiji_populate_ulv_state(hwmgr, table);
                PP_ASSERT_WITH_CODE(0 == result,