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27#ifndef __NOUVEAU_DMA_H__
28#define __NOUVEAU_DMA_H__
29
30#include "nouveau_bo.h"
31#include "nouveau_chan.h"
32
33int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
34void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *,
35 int delta, int length);
36
37
38
39
40
41
42
43
44
45
46
47#define NOUVEAU_DMA_SKIPS (128 / 4)
48
49
50enum {
51 NvSubCtxSurf2D = 0,
52 NvSubSw = 1,
53 NvSubImageBlit = 2,
54 NvSubGdiRect = 3,
55
56 NvSub2D = 3,
57 NvSubCopy = 4,
58 FermiSw = 5,
59};
60
61
62enum {
63 NvDmaFB = 0x80000002,
64 NvDmaTT = 0x80000003,
65 NvNotify0 = 0x80000006,
66 NvSema = 0x8000000f,
67 NvEvoSema0 = 0x80000010,
68 NvEvoSema1 = 0x80000011,
69};
70
71#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039
72#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000
73#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050
74#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100
75#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
76#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000
77#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001
78#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180
79#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184
80#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
81
82#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
83#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200
84#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c
85#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238
86#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c
87
88static __must_check inline int
89RING_SPACE(struct nouveau_channel *chan, int size)
90{
91 int ret;
92
93 ret = nouveau_dma_wait(chan, 1, size);
94 if (ret)
95 return ret;
96
97 chan->dma.free -= size;
98 return 0;
99}
100
101static inline void
102OUT_RING(struct nouveau_channel *chan, int data)
103{
104 nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data);
105}
106
107extern void
108OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords);
109
110static inline void
111BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size)
112{
113 OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd);
114}
115
116static inline void
117BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size)
118{
119 OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd);
120}
121
122static inline void
123BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size)
124{
125 OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2));
126}
127
128static inline void
129BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size)
130{
131 OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2));
132}
133
134static inline void
135BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data)
136{
137 OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2));
138}
139
140#define WRITE_PUT(val) do { \
141 mb(); \
142 nouveau_bo_rd32(chan->push.buffer, 0); \
143 nvif_wr32(&chan->user, chan->user_put, ((val) << 2) + chan->push.vma.offset); \
144} while (0)
145
146static inline void
147FIRE_RING(struct nouveau_channel *chan)
148{
149 if (chan->dma.cur == chan->dma.put)
150 return;
151 chan->accel_done = true;
152
153 if (chan->dma.ib_max) {
154 nv50_dma_push(chan, chan->push.buffer, chan->dma.put << 2,
155 (chan->dma.cur - chan->dma.put) << 2);
156 } else {
157 WRITE_PUT(chan->dma.cur);
158 }
159
160 chan->dma.put = chan->dma.cur;
161}
162
163static inline void
164WIND_RING(struct nouveau_channel *chan)
165{
166 chan->dma.cur = chan->dma.put;
167}
168
169
170#define NV01_SUBCHAN_OBJECT 0x00000000
171#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
172#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
173#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
174#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
175#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
176#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
177#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
178#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
179#define NV84_SUBCHAN_UEVENT 0x00000020
180#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
181#define NV10_SUBCHAN_REF_CNT 0x00000050
182#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
183#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
184#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
185#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
186#define NV40_SUBCHAN_YIELD 0x00000080
187
188
189#define NV_SW_DMA_VBLSEM 0x0000018c
190#define NV_SW_VBLSEM_OFFSET 0x00000400
191#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
192#define NV_SW_VBLSEM_RELEASE 0x00000408
193#define NV_SW_PAGE_FLIP 0x00000500
194
195#endif
196