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28#include "vmwgfx_kms.h"
29#include "device_include/svga3d_surfacedefs.h"
30#include <drm/drm_plane_helper.h>
31
32#define vmw_crtc_to_stdu(x) \
33 container_of(x, struct vmw_screen_target_display_unit, base.crtc)
34#define vmw_encoder_to_stdu(x) \
35 container_of(x, struct vmw_screen_target_display_unit, base.encoder)
36#define vmw_connector_to_stdu(x) \
37 container_of(x, struct vmw_screen_target_display_unit, base.connector)
38
39
40
41enum stdu_content_type {
42 SAME_AS_DISPLAY = 0,
43 SEPARATE_SURFACE,
44 SEPARATE_DMA
45};
46
47
48
49
50
51
52
53
54
55
56
57
58
59struct vmw_stdu_dirty {
60 struct vmw_kms_dirty base;
61 SVGA3dTransferType transfer;
62 s32 left, right, top, bottom;
63 u32 pitch;
64 union {
65 struct vmw_dma_buffer *buf;
66 u32 sid;
67 };
68};
69
70
71
72
73
74struct vmw_stdu_update {
75 SVGA3dCmdHeader header;
76 SVGA3dCmdUpdateGBScreenTarget body;
77};
78
79struct vmw_stdu_dma {
80 SVGA3dCmdHeader header;
81 SVGA3dCmdSurfaceDMA body;
82};
83
84struct vmw_stdu_surface_copy {
85 SVGA3dCmdHeader header;
86 SVGA3dCmdSurfaceCopy body;
87};
88
89
90
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96
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98
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100
101
102struct vmw_screen_target_display_unit {
103 struct vmw_display_unit base;
104
105 struct vmw_surface *display_srf;
106 enum stdu_content_type content_fb_type;
107
108 bool defined;
109};
110
111
112
113static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu);
114
115
116
117
118
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120
121
122
123
124
125
126
127
128
129
130
131static void vmw_stdu_unpin_display(struct vmw_screen_target_display_unit *stdu)
132{
133 if (stdu->display_srf) {
134 struct vmw_resource *res = &stdu->display_srf->res;
135
136 vmw_resource_unpin(res);
137 vmw_surface_unreference(&stdu->display_srf);
138 }
139}
140
141
142
143
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149
150
151
152
153static void vmw_stdu_crtc_destroy(struct drm_crtc *crtc)
154{
155 vmw_stdu_destroy(vmw_crtc_to_stdu(crtc));
156}
157
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160
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171
172
173static int vmw_stdu_define_st(struct vmw_private *dev_priv,
174 struct vmw_screen_target_display_unit *stdu,
175 struct drm_display_mode *mode,
176 int crtc_x, int crtc_y)
177{
178 struct {
179 SVGA3dCmdHeader header;
180 SVGA3dCmdDefineGBScreenTarget body;
181 } *cmd;
182
183 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
184
185 if (unlikely(cmd == NULL)) {
186 DRM_ERROR("Out of FIFO space defining Screen Target\n");
187 return -ENOMEM;
188 }
189
190 cmd->header.id = SVGA_3D_CMD_DEFINE_GB_SCREENTARGET;
191 cmd->header.size = sizeof(cmd->body);
192
193 cmd->body.stid = stdu->base.unit;
194 cmd->body.width = mode->hdisplay;
195 cmd->body.height = mode->vdisplay;
196 cmd->body.flags = (0 == cmd->body.stid) ? SVGA_STFLAG_PRIMARY : 0;
197 cmd->body.dpi = 0;
198 if (stdu->base.is_implicit) {
199 cmd->body.xRoot = crtc_x;
200 cmd->body.yRoot = crtc_y;
201 } else {
202 cmd->body.xRoot = stdu->base.gui_x;
203 cmd->body.yRoot = stdu->base.gui_y;
204 }
205 stdu->base.set_gui_x = cmd->body.xRoot;
206 stdu->base.set_gui_y = cmd->body.yRoot;
207
208 vmw_fifo_commit(dev_priv, sizeof(*cmd));
209
210 stdu->defined = true;
211
212 return 0;
213}
214
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224
225
226static int vmw_stdu_bind_st(struct vmw_private *dev_priv,
227 struct vmw_screen_target_display_unit *stdu,
228 struct vmw_resource *res)
229{
230 SVGA3dSurfaceImageId image;
231
232 struct {
233 SVGA3dCmdHeader header;
234 SVGA3dCmdBindGBScreenTarget body;
235 } *cmd;
236
237
238 if (!stdu->defined) {
239 DRM_ERROR("No screen target defined\n");
240 return -EINVAL;
241 }
242
243
244 memset(&image, 0, sizeof(image));
245 image.sid = res ? res->id : SVGA3D_INVALID_ID;
246
247 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
248
249 if (unlikely(cmd == NULL)) {
250 DRM_ERROR("Out of FIFO space binding a screen target\n");
251 return -ENOMEM;
252 }
253
254 cmd->header.id = SVGA_3D_CMD_BIND_GB_SCREENTARGET;
255 cmd->header.size = sizeof(cmd->body);
256
257 cmd->body.stid = stdu->base.unit;
258 cmd->body.image = image;
259
260 vmw_fifo_commit(dev_priv, sizeof(*cmd));
261
262 return 0;
263}
264
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275
276static void vmw_stdu_populate_update(void *cmd, int unit,
277 s32 left, s32 right, s32 top, s32 bottom)
278{
279 struct vmw_stdu_update *update = cmd;
280
281 update->header.id = SVGA_3D_CMD_UPDATE_GB_SCREENTARGET;
282 update->header.size = sizeof(update->body);
283
284 update->body.stid = unit;
285 update->body.rect.x = left;
286 update->body.rect.y = top;
287 update->body.rect.w = right - left;
288 update->body.rect.h = bottom - top;
289}
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302
303
304static int vmw_stdu_update_st(struct vmw_private *dev_priv,
305 struct vmw_screen_target_display_unit *stdu)
306{
307 struct vmw_stdu_update *cmd;
308 struct drm_crtc *crtc = &stdu->base.crtc;
309
310 if (!stdu->defined) {
311 DRM_ERROR("No screen target defined");
312 return -EINVAL;
313 }
314
315 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
316
317 if (unlikely(cmd == NULL)) {
318 DRM_ERROR("Out of FIFO space updating a Screen Target\n");
319 return -ENOMEM;
320 }
321
322 vmw_stdu_populate_update(cmd, stdu->base.unit, 0, crtc->mode.hdisplay,
323 0, crtc->mode.vdisplay);
324
325 vmw_fifo_commit(dev_priv, sizeof(*cmd));
326
327 return 0;
328}
329
330
331
332
333
334
335
336
337
338static int vmw_stdu_destroy_st(struct vmw_private *dev_priv,
339 struct vmw_screen_target_display_unit *stdu)
340{
341 int ret;
342
343 struct {
344 SVGA3dCmdHeader header;
345 SVGA3dCmdDestroyGBScreenTarget body;
346 } *cmd;
347
348
349
350 if (unlikely(!stdu->defined))
351 return 0;
352
353 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
354
355 if (unlikely(cmd == NULL)) {
356 DRM_ERROR("Out of FIFO space, screen target not destroyed\n");
357 return -ENOMEM;
358 }
359
360 cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SCREENTARGET;
361 cmd->header.size = sizeof(cmd->body);
362
363 cmd->body.stid = stdu->base.unit;
364
365 vmw_fifo_commit(dev_priv, sizeof(*cmd));
366
367
368 ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
369 if (unlikely(ret != 0))
370 DRM_ERROR("Failed to sync with HW");
371
372 stdu->defined = false;
373
374 return ret;
375}
376
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380
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386
387
388static int vmw_stdu_bind_fb(struct vmw_private *dev_priv,
389 struct drm_crtc *crtc,
390 struct drm_display_mode *mode,
391 struct drm_framebuffer *new_fb)
392{
393 struct vmw_screen_target_display_unit *stdu = vmw_crtc_to_stdu(crtc);
394 struct vmw_framebuffer *vfb = vmw_framebuffer_to_vfb(new_fb);
395 struct vmw_surface *new_display_srf = NULL;
396 enum stdu_content_type new_content_type;
397 struct vmw_framebuffer_surface *new_vfbs;
398 int ret;
399
400 WARN_ON_ONCE(!stdu->defined);
401
402 new_vfbs = (vfb->dmabuf) ? NULL : vmw_framebuffer_to_vfbs(new_fb);
403
404 if (new_vfbs && new_vfbs->surface->base_size.width == mode->hdisplay &&
405 new_vfbs->surface->base_size.height == mode->vdisplay)
406 new_content_type = SAME_AS_DISPLAY;
407 else if (vfb->dmabuf)
408 new_content_type = SEPARATE_DMA;
409 else
410 new_content_type = SEPARATE_SURFACE;
411
412 if (new_content_type != SAME_AS_DISPLAY &&
413 !stdu->display_srf) {
414 struct vmw_surface content_srf;
415 struct drm_vmw_size display_base_size = {0};
416
417 display_base_size.width = mode->hdisplay;
418 display_base_size.height = mode->vdisplay;
419 display_base_size.depth = 1;
420
421
422
423
424
425 if (new_content_type == SEPARATE_DMA) {
426
427 switch (new_fb->bits_per_pixel) {
428 case 32:
429 content_srf.format = SVGA3D_X8R8G8B8;
430 break;
431
432 case 16:
433 content_srf.format = SVGA3D_R5G6B5;
434 break;
435
436 case 8:
437 content_srf.format = SVGA3D_P8;
438 break;
439
440 default:
441 DRM_ERROR("Invalid format\n");
442 return -EINVAL;
443 }
444
445 content_srf.flags = 0;
446 content_srf.mip_levels[0] = 1;
447 content_srf.multisample_count = 0;
448 } else {
449 content_srf = *new_vfbs->surface;
450 }
451
452
453 ret = vmw_surface_gb_priv_define(crtc->dev,
454 0,
455 content_srf.flags,
456 content_srf.format,
457 true,
458 content_srf.mip_levels[0],
459 content_srf.multisample_count,
460 0,
461 display_base_size,
462 &new_display_srf);
463 if (unlikely(ret != 0)) {
464 DRM_ERROR("Could not allocate screen target surface.\n");
465 return ret;
466 }
467 } else if (new_content_type == SAME_AS_DISPLAY) {
468 new_display_srf = vmw_surface_reference(new_vfbs->surface);
469 }
470
471 if (new_display_srf) {
472
473 ret = vmw_resource_pin(&new_display_srf->res, false);
474 if (ret)
475 goto out_srf_unref;
476
477 ret = vmw_stdu_bind_st(dev_priv, stdu, &new_display_srf->res);
478 if (ret)
479 goto out_srf_unpin;
480
481
482 vmw_stdu_unpin_display(stdu);
483
484
485 stdu->display_srf = new_display_srf;
486 new_display_srf = NULL;
487 }
488
489 crtc->primary->fb = new_fb;
490 stdu->content_fb_type = new_content_type;
491 return 0;
492
493out_srf_unpin:
494 vmw_resource_unpin(&new_display_srf->res);
495out_srf_unref:
496 vmw_surface_unreference(&new_display_srf);
497 return ret;
498}
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510
511
512static int vmw_stdu_crtc_set_config(struct drm_mode_set *set)
513{
514 struct vmw_private *dev_priv;
515 struct vmw_framebuffer *vfb;
516 struct vmw_screen_target_display_unit *stdu;
517 struct drm_display_mode *mode;
518 struct drm_framebuffer *new_fb;
519 struct drm_crtc *crtc;
520 struct drm_encoder *encoder;
521 struct drm_connector *connector;
522 bool turning_off;
523 int ret;
524
525
526 if (!set || !set->crtc)
527 return -EINVAL;
528
529 crtc = set->crtc;
530 stdu = vmw_crtc_to_stdu(crtc);
531 mode = set->mode;
532 new_fb = set->fb;
533 dev_priv = vmw_priv(crtc->dev);
534 turning_off = set->num_connectors == 0 || !mode || !new_fb;
535 vfb = (new_fb) ? vmw_framebuffer_to_vfb(new_fb) : NULL;
536
537 if (set->num_connectors > 1) {
538 DRM_ERROR("Too many connectors\n");
539 return -EINVAL;
540 }
541
542 if (set->num_connectors == 1 &&
543 set->connectors[0] != &stdu->base.connector) {
544 DRM_ERROR("Connectors don't match %p %p\n",
545 set->connectors[0], &stdu->base.connector);
546 return -EINVAL;
547 }
548
549 if (!turning_off && (set->x + mode->hdisplay > new_fb->width ||
550 set->y + mode->vdisplay > new_fb->height)) {
551 DRM_ERROR("Set outside of framebuffer\n");
552 return -EINVAL;
553 }
554
555
556 mutex_lock(&dev_priv->global_kms_state_mutex);
557 if (!turning_off && stdu->base.is_implicit && dev_priv->implicit_fb &&
558 !(dev_priv->num_implicit == 1 && stdu->base.active_implicit)
559 && dev_priv->implicit_fb != vfb) {
560 mutex_unlock(&dev_priv->global_kms_state_mutex);
561 DRM_ERROR("Multiple implicit framebuffers not supported.\n");
562 return -EINVAL;
563 }
564 mutex_unlock(&dev_priv->global_kms_state_mutex);
565
566
567 connector = &stdu->base.connector;
568 encoder = &stdu->base.encoder;
569
570 if (stdu->defined) {
571 ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
572 if (ret)
573 return ret;
574
575 vmw_stdu_unpin_display(stdu);
576 (void) vmw_stdu_update_st(dev_priv, stdu);
577 vmw_kms_del_active(dev_priv, &stdu->base);
578
579 ret = vmw_stdu_destroy_st(dev_priv, stdu);
580 if (ret)
581 return ret;
582
583 crtc->primary->fb = NULL;
584 crtc->enabled = false;
585 encoder->crtc = NULL;
586 connector->encoder = NULL;
587 stdu->content_fb_type = SAME_AS_DISPLAY;
588 crtc->x = set->x;
589 crtc->y = set->y;
590 }
591
592 if (turning_off)
593 return 0;
594
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609 vmw_svga_enable(dev_priv);
610 ret = vmw_stdu_define_st(dev_priv, stdu, mode, set->x, set->y);
611 if (ret)
612 return ret;
613
614 crtc->x = set->x;
615 crtc->y = set->y;
616 crtc->mode = *mode;
617
618 ret = vmw_stdu_bind_fb(dev_priv, crtc, mode, new_fb);
619 if (ret)
620 return ret;
621
622 vmw_kms_add_active(dev_priv, &stdu->base, vfb);
623 crtc->enabled = true;
624 connector->encoder = encoder;
625 encoder->crtc = crtc;
626
627 return 0;
628}
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649static int vmw_stdu_crtc_page_flip(struct drm_crtc *crtc,
650 struct drm_framebuffer *new_fb,
651 struct drm_pending_vblank_event *event,
652 uint32_t flags)
653
654{
655 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
656 struct vmw_screen_target_display_unit *stdu;
657 struct drm_vmw_rect vclips;
658 struct vmw_framebuffer *vfb = vmw_framebuffer_to_vfb(new_fb);
659 int ret;
660
661 dev_priv = vmw_priv(crtc->dev);
662 stdu = vmw_crtc_to_stdu(crtc);
663
664 if (!stdu->defined || !vmw_kms_crtc_flippable(dev_priv, crtc))
665 return -EINVAL;
666
667 ret = vmw_stdu_bind_fb(dev_priv, crtc, &crtc->mode, new_fb);
668 if (ret)
669 return ret;
670
671 if (stdu->base.is_implicit)
672 vmw_kms_update_implicit_fb(dev_priv, crtc);
673
674 vclips.x = crtc->x;
675 vclips.y = crtc->y;
676 vclips.w = crtc->mode.hdisplay;
677 vclips.h = crtc->mode.vdisplay;
678 if (vfb->dmabuf)
679 ret = vmw_kms_stdu_dma(dev_priv, NULL, vfb, NULL, NULL, &vclips,
680 1, 1, true, false);
681 else
682 ret = vmw_kms_stdu_surface_dirty(dev_priv, vfb, NULL, &vclips,
683 NULL, 0, 0, 1, 1, NULL);
684 if (ret)
685 return ret;
686
687 if (event) {
688 struct vmw_fence_obj *fence = NULL;
689 struct drm_file *file_priv = event->base.file_priv;
690
691 vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);
692 if (!fence)
693 return -ENOMEM;
694
695 ret = vmw_event_fence_action_queue(file_priv, fence,
696 &event->base,
697 &event->event.tv_sec,
698 &event->event.tv_usec,
699 true);
700 vmw_fence_obj_unreference(&fence);
701 } else {
702 vmw_fifo_flush(dev_priv, false);
703 }
704
705 return 0;
706}
707
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715
716
717static void vmw_stdu_dmabuf_clip(struct vmw_kms_dirty *dirty)
718{
719 struct vmw_stdu_dirty *ddirty =
720 container_of(dirty, struct vmw_stdu_dirty, base);
721 struct vmw_stdu_dma *cmd = dirty->cmd;
722 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
723
724 blit += dirty->num_hits;
725 blit->srcx = dirty->fb_x;
726 blit->srcy = dirty->fb_y;
727 blit->x = dirty->unit_x1;
728 blit->y = dirty->unit_y1;
729 blit->d = 1;
730 blit->w = dirty->unit_x2 - dirty->unit_x1;
731 blit->h = dirty->unit_y2 - dirty->unit_y1;
732 dirty->num_hits++;
733
734 if (ddirty->transfer != SVGA3D_WRITE_HOST_VRAM)
735 return;
736
737
738 ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1);
739 ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1);
740 ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2);
741 ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2);
742}
743
744
745
746
747
748
749
750
751
752static void vmw_stdu_dmabuf_fifo_commit(struct vmw_kms_dirty *dirty)
753{
754 struct vmw_stdu_dirty *ddirty =
755 container_of(dirty, struct vmw_stdu_dirty, base);
756 struct vmw_screen_target_display_unit *stdu =
757 container_of(dirty->unit, typeof(*stdu), base);
758 struct vmw_stdu_dma *cmd = dirty->cmd;
759 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
760 SVGA3dCmdSurfaceDMASuffix *suffix =
761 (SVGA3dCmdSurfaceDMASuffix *) &blit[dirty->num_hits];
762 size_t blit_size = sizeof(*blit) * dirty->num_hits + sizeof(*suffix);
763
764 if (!dirty->num_hits) {
765 vmw_fifo_commit(dirty->dev_priv, 0);
766 return;
767 }
768
769 cmd->header.id = SVGA_3D_CMD_SURFACE_DMA;
770 cmd->header.size = sizeof(cmd->body) + blit_size;
771 vmw_bo_get_guest_ptr(&ddirty->buf->base, &cmd->body.guest.ptr);
772 cmd->body.guest.pitch = ddirty->pitch;
773 cmd->body.host.sid = stdu->display_srf->res.id;
774 cmd->body.host.face = 0;
775 cmd->body.host.mipmap = 0;
776 cmd->body.transfer = ddirty->transfer;
777 suffix->suffixSize = sizeof(*suffix);
778 suffix->maximumOffset = ddirty->buf->base.num_pages * PAGE_SIZE;
779
780 if (ddirty->transfer == SVGA3D_WRITE_HOST_VRAM) {
781 blit_size += sizeof(struct vmw_stdu_update);
782
783 vmw_stdu_populate_update(&suffix[1], stdu->base.unit,
784 ddirty->left, ddirty->right,
785 ddirty->top, ddirty->bottom);
786 }
787
788 vmw_fifo_commit(dirty->dev_priv, sizeof(*cmd) + blit_size);
789
790 ddirty->left = ddirty->top = S32_MAX;
791 ddirty->right = ddirty->bottom = S32_MIN;
792}
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817int vmw_kms_stdu_dma(struct vmw_private *dev_priv,
818 struct drm_file *file_priv,
819 struct vmw_framebuffer *vfb,
820 struct drm_vmw_fence_rep __user *user_fence_rep,
821 struct drm_clip_rect *clips,
822 struct drm_vmw_rect *vclips,
823 uint32_t num_clips,
824 int increment,
825 bool to_surface,
826 bool interruptible)
827{
828 struct vmw_dma_buffer *buf =
829 container_of(vfb, struct vmw_framebuffer_dmabuf, base)->buffer;
830 struct vmw_stdu_dirty ddirty;
831 int ret;
832
833 ret = vmw_kms_helper_buffer_prepare(dev_priv, buf, interruptible,
834 false);
835 if (ret)
836 return ret;
837
838 ddirty.transfer = (to_surface) ? SVGA3D_WRITE_HOST_VRAM :
839 SVGA3D_READ_HOST_VRAM;
840 ddirty.left = ddirty.top = S32_MAX;
841 ddirty.right = ddirty.bottom = S32_MIN;
842 ddirty.pitch = vfb->base.pitches[0];
843 ddirty.buf = buf;
844 ddirty.base.fifo_commit = vmw_stdu_dmabuf_fifo_commit;
845 ddirty.base.clip = vmw_stdu_dmabuf_clip;
846 ddirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_dma) +
847 num_clips * sizeof(SVGA3dCopyBox) +
848 sizeof(SVGA3dCmdSurfaceDMASuffix);
849 if (to_surface)
850 ddirty.base.fifo_reserve_size += sizeof(struct vmw_stdu_update);
851
852 ret = vmw_kms_helper_dirty(dev_priv, vfb, clips, vclips,
853 0, 0, num_clips, increment, &ddirty.base);
854 vmw_kms_helper_buffer_finish(dev_priv, file_priv, buf, NULL,
855 user_fence_rep);
856
857 return ret;
858}
859
860
861
862
863
864
865
866
867
868static void vmw_kms_stdu_surface_clip(struct vmw_kms_dirty *dirty)
869{
870 struct vmw_stdu_dirty *sdirty =
871 container_of(dirty, struct vmw_stdu_dirty, base);
872 struct vmw_stdu_surface_copy *cmd = dirty->cmd;
873 struct vmw_screen_target_display_unit *stdu =
874 container_of(dirty->unit, typeof(*stdu), base);
875
876 if (sdirty->sid != stdu->display_srf->res.id) {
877 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
878
879 blit += dirty->num_hits;
880 blit->srcx = dirty->fb_x;
881 blit->srcy = dirty->fb_y;
882 blit->x = dirty->unit_x1;
883 blit->y = dirty->unit_y1;
884 blit->d = 1;
885 blit->w = dirty->unit_x2 - dirty->unit_x1;
886 blit->h = dirty->unit_y2 - dirty->unit_y1;
887 }
888
889 dirty->num_hits++;
890
891
892 sdirty->left = min_t(s32, sdirty->left, dirty->unit_x1);
893 sdirty->top = min_t(s32, sdirty->top, dirty->unit_y1);
894 sdirty->right = max_t(s32, sdirty->right, dirty->unit_x2);
895 sdirty->bottom = max_t(s32, sdirty->bottom, dirty->unit_y2);
896}
897
898
899
900
901
902
903
904
905
906
907static void vmw_kms_stdu_surface_fifo_commit(struct vmw_kms_dirty *dirty)
908{
909 struct vmw_stdu_dirty *sdirty =
910 container_of(dirty, struct vmw_stdu_dirty, base);
911 struct vmw_screen_target_display_unit *stdu =
912 container_of(dirty->unit, typeof(*stdu), base);
913 struct vmw_stdu_surface_copy *cmd = dirty->cmd;
914 struct vmw_stdu_update *update;
915 size_t blit_size = sizeof(SVGA3dCopyBox) * dirty->num_hits;
916 size_t commit_size;
917
918 if (!dirty->num_hits) {
919 vmw_fifo_commit(dirty->dev_priv, 0);
920 return;
921 }
922
923 if (sdirty->sid != stdu->display_srf->res.id) {
924 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
925
926 cmd->header.id = SVGA_3D_CMD_SURFACE_COPY;
927 cmd->header.size = sizeof(cmd->body) + blit_size;
928 cmd->body.src.sid = sdirty->sid;
929 cmd->body.dest.sid = stdu->display_srf->res.id;
930 update = (struct vmw_stdu_update *) &blit[dirty->num_hits];
931 commit_size = sizeof(*cmd) + blit_size + sizeof(*update);
932 } else {
933 update = dirty->cmd;
934 commit_size = sizeof(*update);
935 }
936
937 vmw_stdu_populate_update(update, stdu->base.unit, sdirty->left,
938 sdirty->right, sdirty->top, sdirty->bottom);
939
940 vmw_fifo_commit(dirty->dev_priv, commit_size);
941
942 sdirty->left = sdirty->top = S32_MAX;
943 sdirty->right = sdirty->bottom = S32_MIN;
944}
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv,
968 struct vmw_framebuffer *framebuffer,
969 struct drm_clip_rect *clips,
970 struct drm_vmw_rect *vclips,
971 struct vmw_resource *srf,
972 s32 dest_x,
973 s32 dest_y,
974 unsigned num_clips, int inc,
975 struct vmw_fence_obj **out_fence)
976{
977 struct vmw_framebuffer_surface *vfbs =
978 container_of(framebuffer, typeof(*vfbs), base);
979 struct vmw_stdu_dirty sdirty;
980 int ret;
981
982 if (!srf)
983 srf = &vfbs->surface->res;
984
985 ret = vmw_kms_helper_resource_prepare(srf, true);
986 if (ret)
987 return ret;
988
989 if (vfbs->is_dmabuf_proxy) {
990 ret = vmw_kms_update_proxy(srf, clips, num_clips, inc);
991 if (ret)
992 goto out_finish;
993 }
994
995 sdirty.base.fifo_commit = vmw_kms_stdu_surface_fifo_commit;
996 sdirty.base.clip = vmw_kms_stdu_surface_clip;
997 sdirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_surface_copy) +
998 sizeof(SVGA3dCopyBox) * num_clips +
999 sizeof(struct vmw_stdu_update);
1000 sdirty.sid = srf->id;
1001 sdirty.left = sdirty.top = S32_MAX;
1002 sdirty.right = sdirty.bottom = S32_MIN;
1003
1004 ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
1005 dest_x, dest_y, num_clips, inc,
1006 &sdirty.base);
1007out_finish:
1008 vmw_kms_helper_resource_finish(srf, out_fence);
1009
1010 return ret;
1011}
1012
1013
1014
1015
1016
1017static const struct drm_crtc_funcs vmw_stdu_crtc_funcs = {
1018 .cursor_set2 = vmw_du_crtc_cursor_set2,
1019 .cursor_move = vmw_du_crtc_cursor_move,
1020 .gamma_set = vmw_du_crtc_gamma_set,
1021 .destroy = vmw_stdu_crtc_destroy,
1022 .set_config = vmw_stdu_crtc_set_config,
1023 .page_flip = vmw_stdu_crtc_page_flip,
1024};
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042static void vmw_stdu_encoder_destroy(struct drm_encoder *encoder)
1043{
1044 vmw_stdu_destroy(vmw_encoder_to_stdu(encoder));
1045}
1046
1047static const struct drm_encoder_funcs vmw_stdu_encoder_funcs = {
1048 .destroy = vmw_stdu_encoder_destroy,
1049};
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067static void vmw_stdu_connector_destroy(struct drm_connector *connector)
1068{
1069 vmw_stdu_destroy(vmw_connector_to_stdu(connector));
1070}
1071
1072
1073
1074static const struct drm_connector_funcs vmw_stdu_connector_funcs = {
1075 .dpms = vmw_du_connector_dpms,
1076 .detect = vmw_du_connector_detect,
1077 .fill_modes = vmw_du_connector_fill_modes,
1078 .set_property = vmw_du_connector_set_property,
1079 .destroy = vmw_stdu_connector_destroy,
1080};
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094static int vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit)
1095{
1096 struct vmw_screen_target_display_unit *stdu;
1097 struct drm_device *dev = dev_priv->dev;
1098 struct drm_connector *connector;
1099 struct drm_encoder *encoder;
1100 struct drm_crtc *crtc;
1101
1102
1103 stdu = kzalloc(sizeof(*stdu), GFP_KERNEL);
1104 if (!stdu)
1105 return -ENOMEM;
1106
1107 stdu->base.unit = unit;
1108 crtc = &stdu->base.crtc;
1109 encoder = &stdu->base.encoder;
1110 connector = &stdu->base.connector;
1111
1112 stdu->base.pref_active = (unit == 0);
1113 stdu->base.pref_width = dev_priv->initial_width;
1114 stdu->base.pref_height = dev_priv->initial_height;
1115 stdu->base.is_implicit = false;
1116
1117 drm_connector_init(dev, connector, &vmw_stdu_connector_funcs,
1118 DRM_MODE_CONNECTOR_VIRTUAL);
1119 connector->status = vmw_du_connector_detect(connector, false);
1120
1121 drm_encoder_init(dev, encoder, &vmw_stdu_encoder_funcs,
1122 DRM_MODE_ENCODER_VIRTUAL, NULL);
1123 drm_mode_connector_attach_encoder(connector, encoder);
1124 encoder->possible_crtcs = (1 << unit);
1125 encoder->possible_clones = 0;
1126
1127 (void) drm_connector_register(connector);
1128
1129 drm_crtc_init(dev, crtc, &vmw_stdu_crtc_funcs);
1130
1131 drm_mode_crtc_set_gamma_size(crtc, 256);
1132
1133 drm_object_attach_property(&connector->base,
1134 dev->mode_config.dirty_info_property,
1135 1);
1136 drm_object_attach_property(&connector->base,
1137 dev_priv->hotplug_mode_update_property, 1);
1138 drm_object_attach_property(&connector->base,
1139 dev->mode_config.suggested_x_property, 0);
1140 drm_object_attach_property(&connector->base,
1141 dev->mode_config.suggested_y_property, 0);
1142 if (dev_priv->implicit_placement_property)
1143 drm_object_attach_property
1144 (&connector->base,
1145 dev_priv->implicit_placement_property,
1146 stdu->base.is_implicit);
1147 return 0;
1148}
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu)
1160{
1161 vmw_stdu_unpin_display(stdu);
1162
1163 vmw_du_cleanup(&stdu->base);
1164 kfree(stdu);
1165}
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188int vmw_kms_stdu_init_display(struct vmw_private *dev_priv)
1189{
1190 struct drm_device *dev = dev_priv->dev;
1191 int i, ret;
1192
1193
1194
1195 if (!VMWGFX_ENABLE_SCREEN_TARGET_OTABLE)
1196 return -ENOSYS;
1197
1198 if (!(dev_priv->capabilities & SVGA_CAP_GBOBJECTS))
1199 return -ENOSYS;
1200
1201 ret = drm_vblank_init(dev, VMWGFX_NUM_DISPLAY_UNITS);
1202 if (unlikely(ret != 0))
1203 return ret;
1204
1205 ret = drm_mode_create_dirty_info_property(dev);
1206 if (unlikely(ret != 0))
1207 goto err_vblank_cleanup;
1208
1209 dev_priv->active_display_unit = vmw_du_screen_target;
1210
1211 vmw_kms_create_implicit_placement_property(dev_priv, false);
1212
1213 for (i = 0; i < VMWGFX_NUM_DISPLAY_UNITS; ++i) {
1214 ret = vmw_stdu_init(dev_priv, i);
1215
1216 if (unlikely(ret != 0)) {
1217 DRM_ERROR("Failed to initialize STDU %d", i);
1218 goto err_vblank_cleanup;
1219 }
1220 }
1221
1222 DRM_INFO("Screen Target Display device initialized\n");
1223
1224 return 0;
1225
1226err_vblank_cleanup:
1227 drm_vblank_cleanup(dev);
1228 return ret;
1229}
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243int vmw_kms_stdu_close_display(struct vmw_private *dev_priv)
1244{
1245 struct drm_device *dev = dev_priv->dev;
1246
1247 drm_vblank_cleanup(dev);
1248
1249 return 0;
1250}
1251