linux/drivers/i2c/busses/i2c-i801.c
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   1/*
   2    Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3    Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4    <mdsxyz123@yahoo.com>
   5    Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6    Copyright (C) 2010         Intel Corporation,
   7                               David Woodhouse <dwmw2@infradead.org>
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18*/
  19
  20/*
  21 * Supports the following Intel I/O Controller Hubs (ICH):
  22 *
  23 *                                      I/O                     Block   I2C
  24 *                                      region  SMBus   Block   proc.   block
  25 * Chip name                    PCI ID  size    PEC     buffer  call    read
  26 * ---------------------------------------------------------------------------
  27 * 82801AA (ICH)                0x2413  16      no      no      no      no
  28 * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29 * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30 * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31 * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32 * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33 * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34 * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35 * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36 * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37 * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38 * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39 * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40 * ICH10                        0x3a30  32      hard    yes     yes     yes
  41 * ICH10                        0x3a60  32      hard    yes     yes     yes
  42 * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43 * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44 * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45 * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46 * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47 * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48 * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49 * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50 * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51 * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52 * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53 * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54 * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55 * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56 * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57 * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58 * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59 * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60 * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61 * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  62 * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  63 * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  64 * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  65 * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  66 * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  67 *
  68 * Features supported by this driver:
  69 * Software PEC                         no
  70 * Hardware PEC                         yes
  71 * Block buffer                         yes
  72 * Block process call transaction       no
  73 * I2C block read transaction           yes (doesn't use the block buffer)
  74 * Slave mode                           no
  75 * SMBus Host Notify                    yes
  76 * Interrupt processing                 yes
  77 *
  78 * See the file Documentation/i2c/busses/i2c-i801 for details.
  79 */
  80
  81#include <linux/interrupt.h>
  82#include <linux/module.h>
  83#include <linux/pci.h>
  84#include <linux/kernel.h>
  85#include <linux/stddef.h>
  86#include <linux/delay.h>
  87#include <linux/ioport.h>
  88#include <linux/init.h>
  89#include <linux/i2c.h>
  90#include <linux/i2c-smbus.h>
  91#include <linux/acpi.h>
  92#include <linux/io.h>
  93#include <linux/dmi.h>
  94#include <linux/slab.h>
  95#include <linux/wait.h>
  96#include <linux/err.h>
  97#include <linux/platform_device.h>
  98#include <linux/platform_data/itco_wdt.h>
  99#include <linux/pm_runtime.h>
 100
 101#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 102#include <linux/gpio.h>
 103#include <linux/i2c-mux-gpio.h>
 104#endif
 105
 106/* I801 SMBus address offsets */
 107#define SMBHSTSTS(p)    (0 + (p)->smba)
 108#define SMBHSTCNT(p)    (2 + (p)->smba)
 109#define SMBHSTCMD(p)    (3 + (p)->smba)
 110#define SMBHSTADD(p)    (4 + (p)->smba)
 111#define SMBHSTDAT0(p)   (5 + (p)->smba)
 112#define SMBHSTDAT1(p)   (6 + (p)->smba)
 113#define SMBBLKDAT(p)    (7 + (p)->smba)
 114#define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 115#define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 116#define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 117#define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 118#define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 119#define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 120#define SMBNTFDDAT(p)   (22 + (p)->smba)        /* ICH3 and later */
 121
 122/* PCI Address Constants */
 123#define SMBBAR          4
 124#define SMBPCICTL       0x004
 125#define SMBPCISTS       0x006
 126#define SMBHSTCFG       0x040
 127#define TCOBASE         0x050
 128#define TCOCTL          0x054
 129
 130#define ACPIBASE                0x040
 131#define ACPIBASE_SMI_OFF        0x030
 132#define ACPICTRL                0x044
 133#define ACPICTRL_EN             0x080
 134
 135#define SBREG_BAR               0x10
 136#define SBREG_SMBCTRL           0xc6000c
 137
 138/* Host status bits for SMBPCISTS */
 139#define SMBPCISTS_INTS          0x08
 140
 141/* Control bits for SMBPCICTL */
 142#define SMBPCICTL_INTDIS        0x0400
 143
 144/* Host configuration bits for SMBHSTCFG */
 145#define SMBHSTCFG_HST_EN        1
 146#define SMBHSTCFG_SMB_SMI_EN    2
 147#define SMBHSTCFG_I2C_EN        4
 148
 149/* TCO configuration bits for TCOCTL */
 150#define TCOCTL_EN               0x0100
 151
 152/* Auxiliary status register bits, ICH4+ only */
 153#define SMBAUXSTS_CRCE          1
 154#define SMBAUXSTS_STCO          2
 155
 156/* Auxiliary control register bits, ICH4+ only */
 157#define SMBAUXCTL_CRC           1
 158#define SMBAUXCTL_E32B          2
 159
 160/* Other settings */
 161#define MAX_RETRIES             400
 162
 163/* I801 command constants */
 164#define I801_QUICK              0x00
 165#define I801_BYTE               0x04
 166#define I801_BYTE_DATA          0x08
 167#define I801_WORD_DATA          0x0C
 168#define I801_PROC_CALL          0x10    /* unimplemented */
 169#define I801_BLOCK_DATA         0x14
 170#define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 171
 172/* I801 Host Control register bits */
 173#define SMBHSTCNT_INTREN        0x01
 174#define SMBHSTCNT_KILL          0x02
 175#define SMBHSTCNT_LAST_BYTE     0x20
 176#define SMBHSTCNT_START         0x40
 177#define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 178
 179/* I801 Hosts Status register bits */
 180#define SMBHSTSTS_BYTE_DONE     0x80
 181#define SMBHSTSTS_INUSE_STS     0x40
 182#define SMBHSTSTS_SMBALERT_STS  0x20
 183#define SMBHSTSTS_FAILED        0x10
 184#define SMBHSTSTS_BUS_ERR       0x08
 185#define SMBHSTSTS_DEV_ERR       0x04
 186#define SMBHSTSTS_INTR          0x02
 187#define SMBHSTSTS_HOST_BUSY     0x01
 188
 189/* Host Notify Status registers bits */
 190#define SMBSLVSTS_HST_NTFY_STS  1
 191
 192/* Host Notify Command registers bits */
 193#define SMBSLVCMD_HST_NTFY_INTREN       0x01
 194
 195#define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 196                                 SMBHSTSTS_DEV_ERR)
 197
 198#define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 199                                 STATUS_ERROR_FLAGS)
 200
 201/* Older devices have their ID defined in <linux/pci_ids.h> */
 202#define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 203#define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 204#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 205#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 206/* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 207#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 208#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 209#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 210#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 211#define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 212#define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 213#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 214#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 215#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 216#define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 217#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 218#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 219#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 220#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 221#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 222#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 223#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 224#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 225#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 226#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 227#define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 228#define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 229
 230struct i801_mux_config {
 231        char *gpio_chip;
 232        unsigned values[3];
 233        int n_values;
 234        unsigned classes[3];
 235        unsigned gpios[2];              /* Relative to gpio_chip->base */
 236        int n_gpios;
 237};
 238
 239struct i801_priv {
 240        struct i2c_adapter adapter;
 241        unsigned long smba;
 242        unsigned char original_hstcfg;
 243        struct pci_dev *pci_dev;
 244        unsigned int features;
 245
 246        /* isr processing */
 247        wait_queue_head_t waitq;
 248        u8 status;
 249
 250        /* Command state used by isr for byte-by-byte block transactions */
 251        u8 cmd;
 252        bool is_read;
 253        int count;
 254        int len;
 255        u8 *data;
 256
 257#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 258        const struct i801_mux_config *mux_drvdata;
 259        struct platform_device *mux_pdev;
 260#endif
 261        struct platform_device *tco_pdev;
 262
 263        /*
 264         * If set to true the host controller registers are reserved for
 265         * ACPI AML use. Protected by acpi_lock.
 266         */
 267        bool acpi_reserved;
 268        struct mutex acpi_lock;
 269        struct smbus_host_notify *host_notify;
 270};
 271
 272#define SMBHSTNTFY_SIZE         8
 273
 274#define FEATURE_SMBUS_PEC       (1 << 0)
 275#define FEATURE_BLOCK_BUFFER    (1 << 1)
 276#define FEATURE_BLOCK_PROC      (1 << 2)
 277#define FEATURE_I2C_BLOCK_READ  (1 << 3)
 278#define FEATURE_IRQ             (1 << 4)
 279#define FEATURE_HOST_NOTIFY     (1 << 5)
 280/* Not really a feature, but it's convenient to handle it as such */
 281#define FEATURE_IDF             (1 << 15)
 282#define FEATURE_TCO             (1 << 16)
 283
 284static const char *i801_feature_names[] = {
 285        "SMBus PEC",
 286        "Block buffer",
 287        "Block process call",
 288        "I2C block read",
 289        "Interrupt",
 290        "SMBus Host Notify",
 291};
 292
 293static unsigned int disable_features;
 294module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 295MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 296        "\t\t  0x01  disable SMBus PEC\n"
 297        "\t\t  0x02  disable the block buffer\n"
 298        "\t\t  0x08  disable the I2C block read functionality\n"
 299        "\t\t  0x10  don't use interrupts\n"
 300        "\t\t  0x20  disable SMBus Host Notify ");
 301
 302/* Make sure the SMBus host is ready to start transmitting.
 303   Return 0 if it is, -EBUSY if it is not. */
 304static int i801_check_pre(struct i801_priv *priv)
 305{
 306        int status;
 307
 308        status = inb_p(SMBHSTSTS(priv));
 309        if (status & SMBHSTSTS_HOST_BUSY) {
 310                dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 311                return -EBUSY;
 312        }
 313
 314        status &= STATUS_FLAGS;
 315        if (status) {
 316                dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 317                        status);
 318                outb_p(status, SMBHSTSTS(priv));
 319                status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 320                if (status) {
 321                        dev_err(&priv->pci_dev->dev,
 322                                "Failed clearing status flags (%02x)\n",
 323                                status);
 324                        return -EBUSY;
 325                }
 326        }
 327
 328        /*
 329         * Clear CRC status if needed.
 330         * During normal operation, i801_check_post() takes care
 331         * of it after every operation.  We do it here only in case
 332         * the hardware was already in this state when the driver
 333         * started.
 334         */
 335        if (priv->features & FEATURE_SMBUS_PEC) {
 336                status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 337                if (status) {
 338                        dev_dbg(&priv->pci_dev->dev,
 339                                "Clearing aux status flags (%02x)\n", status);
 340                        outb_p(status, SMBAUXSTS(priv));
 341                        status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 342                        if (status) {
 343                                dev_err(&priv->pci_dev->dev,
 344                                        "Failed clearing aux status flags (%02x)\n",
 345                                        status);
 346                                return -EBUSY;
 347                        }
 348                }
 349        }
 350
 351        return 0;
 352}
 353
 354/*
 355 * Convert the status register to an error code, and clear it.
 356 * Note that status only contains the bits we want to clear, not the
 357 * actual register value.
 358 */
 359static int i801_check_post(struct i801_priv *priv, int status)
 360{
 361        int result = 0;
 362
 363        /*
 364         * If the SMBus is still busy, we give up
 365         * Note: This timeout condition only happens when using polling
 366         * transactions.  For interrupt operation, NAK/timeout is indicated by
 367         * DEV_ERR.
 368         */
 369        if (unlikely(status < 0)) {
 370                dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 371                /* try to stop the current command */
 372                dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 373                outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 374                       SMBHSTCNT(priv));
 375                usleep_range(1000, 2000);
 376                outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 377                       SMBHSTCNT(priv));
 378
 379                /* Check if it worked */
 380                status = inb_p(SMBHSTSTS(priv));
 381                if ((status & SMBHSTSTS_HOST_BUSY) ||
 382                    !(status & SMBHSTSTS_FAILED))
 383                        dev_err(&priv->pci_dev->dev,
 384                                "Failed terminating the transaction\n");
 385                outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 386                return -ETIMEDOUT;
 387        }
 388
 389        if (status & SMBHSTSTS_FAILED) {
 390                result = -EIO;
 391                dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 392        }
 393        if (status & SMBHSTSTS_DEV_ERR) {
 394                /*
 395                 * This may be a PEC error, check and clear it.
 396                 *
 397                 * AUXSTS is handled differently from HSTSTS.
 398                 * For HSTSTS, i801_isr() or i801_wait_intr()
 399                 * has already cleared the error bits in hardware,
 400                 * and we are passed a copy of the original value
 401                 * in "status".
 402                 * For AUXSTS, the hardware register is left
 403                 * for us to handle here.
 404                 * This is asymmetric, slightly iffy, but safe,
 405                 * since all this code is serialized and the CRCE
 406                 * bit is harmless as long as it's cleared before
 407                 * the next operation.
 408                 */
 409                if ((priv->features & FEATURE_SMBUS_PEC) &&
 410                    (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 411                        outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 412                        result = -EBADMSG;
 413                        dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 414                } else {
 415                        result = -ENXIO;
 416                        dev_dbg(&priv->pci_dev->dev, "No response\n");
 417                }
 418        }
 419        if (status & SMBHSTSTS_BUS_ERR) {
 420                result = -EAGAIN;
 421                dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 422        }
 423
 424        /* Clear status flags except BYTE_DONE, to be cleared by caller */
 425        outb_p(status, SMBHSTSTS(priv));
 426
 427        return result;
 428}
 429
 430/* Wait for BUSY being cleared and either INTR or an error flag being set */
 431static int i801_wait_intr(struct i801_priv *priv)
 432{
 433        int timeout = 0;
 434        int status;
 435
 436        /* We will always wait for a fraction of a second! */
 437        do {
 438                usleep_range(250, 500);
 439                status = inb_p(SMBHSTSTS(priv));
 440        } while (((status & SMBHSTSTS_HOST_BUSY) ||
 441                  !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 442                 (timeout++ < MAX_RETRIES));
 443
 444        if (timeout > MAX_RETRIES) {
 445                dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 446                return -ETIMEDOUT;
 447        }
 448        return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 449}
 450
 451/* Wait for either BYTE_DONE or an error flag being set */
 452static int i801_wait_byte_done(struct i801_priv *priv)
 453{
 454        int timeout = 0;
 455        int status;
 456
 457        /* We will always wait for a fraction of a second! */
 458        do {
 459                usleep_range(250, 500);
 460                status = inb_p(SMBHSTSTS(priv));
 461        } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 462                 (timeout++ < MAX_RETRIES));
 463
 464        if (timeout > MAX_RETRIES) {
 465                dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 466                return -ETIMEDOUT;
 467        }
 468        return status & STATUS_ERROR_FLAGS;
 469}
 470
 471static int i801_transaction(struct i801_priv *priv, int xact)
 472{
 473        int status;
 474        int result;
 475        const struct i2c_adapter *adap = &priv->adapter;
 476
 477        result = i801_check_pre(priv);
 478        if (result < 0)
 479                return result;
 480
 481        if (priv->features & FEATURE_IRQ) {
 482                outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 483                       SMBHSTCNT(priv));
 484                result = wait_event_timeout(priv->waitq,
 485                                            (status = priv->status),
 486                                            adap->timeout);
 487                if (!result) {
 488                        status = -ETIMEDOUT;
 489                        dev_warn(&priv->pci_dev->dev,
 490                                 "Timeout waiting for interrupt!\n");
 491                }
 492                priv->status = 0;
 493                return i801_check_post(priv, status);
 494        }
 495
 496        /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 497         * SMBSCMD are passed in xact */
 498        outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 499
 500        status = i801_wait_intr(priv);
 501        return i801_check_post(priv, status);
 502}
 503
 504static int i801_block_transaction_by_block(struct i801_priv *priv,
 505                                           union i2c_smbus_data *data,
 506                                           char read_write, int hwpec)
 507{
 508        int i, len;
 509        int status;
 510
 511        inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 512
 513        /* Use 32-byte buffer to process this transaction */
 514        if (read_write == I2C_SMBUS_WRITE) {
 515                len = data->block[0];
 516                outb_p(len, SMBHSTDAT0(priv));
 517                for (i = 0; i < len; i++)
 518                        outb_p(data->block[i+1], SMBBLKDAT(priv));
 519        }
 520
 521        status = i801_transaction(priv, I801_BLOCK_DATA |
 522                                  (hwpec ? SMBHSTCNT_PEC_EN : 0));
 523        if (status)
 524                return status;
 525
 526        if (read_write == I2C_SMBUS_READ) {
 527                len = inb_p(SMBHSTDAT0(priv));
 528                if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 529                        return -EPROTO;
 530
 531                data->block[0] = len;
 532                for (i = 0; i < len; i++)
 533                        data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 534        }
 535        return 0;
 536}
 537
 538static void i801_isr_byte_done(struct i801_priv *priv)
 539{
 540        if (priv->is_read) {
 541                /* For SMBus block reads, length is received with first byte */
 542                if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 543                    (priv->count == 0)) {
 544                        priv->len = inb_p(SMBHSTDAT0(priv));
 545                        if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 546                                dev_err(&priv->pci_dev->dev,
 547                                        "Illegal SMBus block read size %d\n",
 548                                        priv->len);
 549                                /* FIXME: Recover */
 550                                priv->len = I2C_SMBUS_BLOCK_MAX;
 551                        } else {
 552                                dev_dbg(&priv->pci_dev->dev,
 553                                        "SMBus block read size is %d\n",
 554                                        priv->len);
 555                        }
 556                        priv->data[-1] = priv->len;
 557                }
 558
 559                /* Read next byte */
 560                if (priv->count < priv->len)
 561                        priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 562                else
 563                        dev_dbg(&priv->pci_dev->dev,
 564                                "Discarding extra byte on block read\n");
 565
 566                /* Set LAST_BYTE for last byte of read transaction */
 567                if (priv->count == priv->len - 1)
 568                        outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 569                               SMBHSTCNT(priv));
 570        } else if (priv->count < priv->len - 1) {
 571                /* Write next byte, except for IRQ after last byte */
 572                outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 573        }
 574
 575        /* Clear BYTE_DONE to continue with next byte */
 576        outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 577}
 578
 579static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 580{
 581        unsigned short addr;
 582        unsigned int data;
 583
 584        addr = inb_p(SMBNTFDADD(priv)) >> 1;
 585        data = inw_p(SMBNTFDDAT(priv));
 586
 587        i2c_handle_smbus_host_notify(priv->host_notify, addr, data);
 588
 589        /* clear Host Notify bit and return */
 590        outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 591        return IRQ_HANDLED;
 592}
 593
 594/*
 595 * There are three kinds of interrupts:
 596 *
 597 * 1) i801 signals transaction completion with one of these interrupts:
 598 *      INTR - Success
 599 *      DEV_ERR - Invalid command, NAK or communication timeout
 600 *      BUS_ERR - SMI# transaction collision
 601 *      FAILED - transaction was canceled due to a KILL request
 602 *    When any of these occur, update ->status and wake up the waitq.
 603 *    ->status must be cleared before kicking off the next transaction.
 604 *
 605 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 606 *    occurs for each byte of a byte-by-byte to prepare the next byte.
 607 *
 608 * 3) Host Notify interrupts
 609 */
 610static irqreturn_t i801_isr(int irq, void *dev_id)
 611{
 612        struct i801_priv *priv = dev_id;
 613        u16 pcists;
 614        u8 status;
 615
 616        /* Confirm this is our interrupt */
 617        pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 618        if (!(pcists & SMBPCISTS_INTS))
 619                return IRQ_NONE;
 620
 621        if (priv->features & FEATURE_HOST_NOTIFY) {
 622                status = inb_p(SMBSLVSTS(priv));
 623                if (status & SMBSLVSTS_HST_NTFY_STS)
 624                        return i801_host_notify_isr(priv);
 625        }
 626
 627        status = inb_p(SMBHSTSTS(priv));
 628        if (status & SMBHSTSTS_BYTE_DONE)
 629                i801_isr_byte_done(priv);
 630
 631        /*
 632         * Clear irq sources and report transaction result.
 633         * ->status must be cleared before the next transaction is started.
 634         */
 635        status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 636        if (status) {
 637                outb_p(status, SMBHSTSTS(priv));
 638                priv->status = status;
 639                wake_up(&priv->waitq);
 640        }
 641
 642        return IRQ_HANDLED;
 643}
 644
 645/*
 646 * For "byte-by-byte" block transactions:
 647 *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 648 *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 649 */
 650static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 651                                               union i2c_smbus_data *data,
 652                                               char read_write, int command,
 653                                               int hwpec)
 654{
 655        int i, len;
 656        int smbcmd;
 657        int status;
 658        int result;
 659        const struct i2c_adapter *adap = &priv->adapter;
 660
 661        result = i801_check_pre(priv);
 662        if (result < 0)
 663                return result;
 664
 665        len = data->block[0];
 666
 667        if (read_write == I2C_SMBUS_WRITE) {
 668                outb_p(len, SMBHSTDAT0(priv));
 669                outb_p(data->block[1], SMBBLKDAT(priv));
 670        }
 671
 672        if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 673            read_write == I2C_SMBUS_READ)
 674                smbcmd = I801_I2C_BLOCK_DATA;
 675        else
 676                smbcmd = I801_BLOCK_DATA;
 677
 678        if (priv->features & FEATURE_IRQ) {
 679                priv->is_read = (read_write == I2C_SMBUS_READ);
 680                if (len == 1 && priv->is_read)
 681                        smbcmd |= SMBHSTCNT_LAST_BYTE;
 682                priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 683                priv->len = len;
 684                priv->count = 0;
 685                priv->data = &data->block[1];
 686
 687                outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 688                result = wait_event_timeout(priv->waitq,
 689                                            (status = priv->status),
 690                                            adap->timeout);
 691                if (!result) {
 692                        status = -ETIMEDOUT;
 693                        dev_warn(&priv->pci_dev->dev,
 694                                 "Timeout waiting for interrupt!\n");
 695                }
 696                priv->status = 0;
 697                return i801_check_post(priv, status);
 698        }
 699
 700        for (i = 1; i <= len; i++) {
 701                if (i == len && read_write == I2C_SMBUS_READ)
 702                        smbcmd |= SMBHSTCNT_LAST_BYTE;
 703                outb_p(smbcmd, SMBHSTCNT(priv));
 704
 705                if (i == 1)
 706                        outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 707                               SMBHSTCNT(priv));
 708
 709                status = i801_wait_byte_done(priv);
 710                if (status)
 711                        goto exit;
 712
 713                if (i == 1 && read_write == I2C_SMBUS_READ
 714                 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 715                        len = inb_p(SMBHSTDAT0(priv));
 716                        if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 717                                dev_err(&priv->pci_dev->dev,
 718                                        "Illegal SMBus block read size %d\n",
 719                                        len);
 720                                /* Recover */
 721                                while (inb_p(SMBHSTSTS(priv)) &
 722                                       SMBHSTSTS_HOST_BUSY)
 723                                        outb_p(SMBHSTSTS_BYTE_DONE,
 724                                               SMBHSTSTS(priv));
 725                                outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 726                                return -EPROTO;
 727                        }
 728                        data->block[0] = len;
 729                }
 730
 731                /* Retrieve/store value in SMBBLKDAT */
 732                if (read_write == I2C_SMBUS_READ)
 733                        data->block[i] = inb_p(SMBBLKDAT(priv));
 734                if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 735                        outb_p(data->block[i+1], SMBBLKDAT(priv));
 736
 737                /* signals SMBBLKDAT ready */
 738                outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 739        }
 740
 741        status = i801_wait_intr(priv);
 742exit:
 743        return i801_check_post(priv, status);
 744}
 745
 746static int i801_set_block_buffer_mode(struct i801_priv *priv)
 747{
 748        outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 749        if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 750                return -EIO;
 751        return 0;
 752}
 753
 754/* Block transaction function */
 755static int i801_block_transaction(struct i801_priv *priv,
 756                                  union i2c_smbus_data *data, char read_write,
 757                                  int command, int hwpec)
 758{
 759        int result = 0;
 760        unsigned char hostc;
 761
 762        if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 763                if (read_write == I2C_SMBUS_WRITE) {
 764                        /* set I2C_EN bit in configuration register */
 765                        pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 766                        pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 767                                              hostc | SMBHSTCFG_I2C_EN);
 768                } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 769                        dev_err(&priv->pci_dev->dev,
 770                                "I2C block read is unsupported!\n");
 771                        return -EOPNOTSUPP;
 772                }
 773        }
 774
 775        if (read_write == I2C_SMBUS_WRITE
 776         || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 777                if (data->block[0] < 1)
 778                        data->block[0] = 1;
 779                if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 780                        data->block[0] = I2C_SMBUS_BLOCK_MAX;
 781        } else {
 782                data->block[0] = 32;    /* max for SMBus block reads */
 783        }
 784
 785        /* Experience has shown that the block buffer can only be used for
 786           SMBus (not I2C) block transactions, even though the datasheet
 787           doesn't mention this limitation. */
 788        if ((priv->features & FEATURE_BLOCK_BUFFER)
 789         && command != I2C_SMBUS_I2C_BLOCK_DATA
 790         && i801_set_block_buffer_mode(priv) == 0)
 791                result = i801_block_transaction_by_block(priv, data,
 792                                                         read_write, hwpec);
 793        else
 794                result = i801_block_transaction_byte_by_byte(priv, data,
 795                                                             read_write,
 796                                                             command, hwpec);
 797
 798        if (command == I2C_SMBUS_I2C_BLOCK_DATA
 799         && read_write == I2C_SMBUS_WRITE) {
 800                /* restore saved configuration register value */
 801                pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 802        }
 803        return result;
 804}
 805
 806/* Return negative errno on error. */
 807static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 808                       unsigned short flags, char read_write, u8 command,
 809                       int size, union i2c_smbus_data *data)
 810{
 811        int hwpec;
 812        int block = 0;
 813        int ret = 0, xact = 0;
 814        struct i801_priv *priv = i2c_get_adapdata(adap);
 815
 816        mutex_lock(&priv->acpi_lock);
 817        if (priv->acpi_reserved) {
 818                mutex_unlock(&priv->acpi_lock);
 819                return -EBUSY;
 820        }
 821
 822        pm_runtime_get_sync(&priv->pci_dev->dev);
 823
 824        hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 825                && size != I2C_SMBUS_QUICK
 826                && size != I2C_SMBUS_I2C_BLOCK_DATA;
 827
 828        switch (size) {
 829        case I2C_SMBUS_QUICK:
 830                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 831                       SMBHSTADD(priv));
 832                xact = I801_QUICK;
 833                break;
 834        case I2C_SMBUS_BYTE:
 835                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 836                       SMBHSTADD(priv));
 837                if (read_write == I2C_SMBUS_WRITE)
 838                        outb_p(command, SMBHSTCMD(priv));
 839                xact = I801_BYTE;
 840                break;
 841        case I2C_SMBUS_BYTE_DATA:
 842                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 843                       SMBHSTADD(priv));
 844                outb_p(command, SMBHSTCMD(priv));
 845                if (read_write == I2C_SMBUS_WRITE)
 846                        outb_p(data->byte, SMBHSTDAT0(priv));
 847                xact = I801_BYTE_DATA;
 848                break;
 849        case I2C_SMBUS_WORD_DATA:
 850                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 851                       SMBHSTADD(priv));
 852                outb_p(command, SMBHSTCMD(priv));
 853                if (read_write == I2C_SMBUS_WRITE) {
 854                        outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 855                        outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 856                }
 857                xact = I801_WORD_DATA;
 858                break;
 859        case I2C_SMBUS_BLOCK_DATA:
 860                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 861                       SMBHSTADD(priv));
 862                outb_p(command, SMBHSTCMD(priv));
 863                block = 1;
 864                break;
 865        case I2C_SMBUS_I2C_BLOCK_DATA:
 866                /* NB: page 240 of ICH5 datasheet shows that the R/#W
 867                 * bit should be cleared here, even when reading */
 868                outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 869                if (read_write == I2C_SMBUS_READ) {
 870                        /* NB: page 240 of ICH5 datasheet also shows
 871                         * that DATA1 is the cmd field when reading */
 872                        outb_p(command, SMBHSTDAT1(priv));
 873                } else
 874                        outb_p(command, SMBHSTCMD(priv));
 875                block = 1;
 876                break;
 877        default:
 878                dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 879                        size);
 880                ret = -EOPNOTSUPP;
 881                goto out;
 882        }
 883
 884        if (hwpec)      /* enable/disable hardware PEC */
 885                outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 886        else
 887                outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 888                       SMBAUXCTL(priv));
 889
 890        if (block)
 891                ret = i801_block_transaction(priv, data, read_write, size,
 892                                             hwpec);
 893        else
 894                ret = i801_transaction(priv, xact);
 895
 896        /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 897           time, so we forcibly disable it after every transaction. Turn off
 898           E32B for the same reason. */
 899        if (hwpec || block)
 900                outb_p(inb_p(SMBAUXCTL(priv)) &
 901                       ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 902
 903        if (block)
 904                goto out;
 905        if (ret)
 906                goto out;
 907        if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 908                goto out;
 909
 910        switch (xact & 0x7f) {
 911        case I801_BYTE: /* Result put in SMBHSTDAT0 */
 912        case I801_BYTE_DATA:
 913                data->byte = inb_p(SMBHSTDAT0(priv));
 914                break;
 915        case I801_WORD_DATA:
 916                data->word = inb_p(SMBHSTDAT0(priv)) +
 917                             (inb_p(SMBHSTDAT1(priv)) << 8);
 918                break;
 919        }
 920
 921out:
 922        pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 923        pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 924        mutex_unlock(&priv->acpi_lock);
 925        return ret;
 926}
 927
 928
 929static u32 i801_func(struct i2c_adapter *adapter)
 930{
 931        struct i801_priv *priv = i2c_get_adapdata(adapter);
 932
 933        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 934               I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 935               I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 936               ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 937               ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 938                I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 939               ((priv->features & FEATURE_HOST_NOTIFY) ?
 940                I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 941}
 942
 943static int i801_enable_host_notify(struct i2c_adapter *adapter)
 944{
 945        struct i801_priv *priv = i2c_get_adapdata(adapter);
 946
 947        if (!(priv->features & FEATURE_HOST_NOTIFY))
 948                return -ENOTSUPP;
 949
 950        if (!priv->host_notify)
 951                priv->host_notify = i2c_setup_smbus_host_notify(adapter);
 952        if (!priv->host_notify)
 953                return -ENOMEM;
 954
 955        outb_p(SMBSLVCMD_HST_NTFY_INTREN, SMBSLVCMD(priv));
 956        /* clear Host Notify bit to allow a new notification */
 957        outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 958
 959        return 0;
 960}
 961
 962static const struct i2c_algorithm smbus_algorithm = {
 963        .smbus_xfer     = i801_access,
 964        .functionality  = i801_func,
 965};
 966
 967static const struct pci_device_id i801_ids[] = {
 968        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 969        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 970        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 971        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 972        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 973        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 974        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 975        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 976        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 977        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 978        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 979        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 980        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 981        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 982        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 983        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 984        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 985        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 986        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 987        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 988        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 989        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 990        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 991        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 992        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 993        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 994        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 995        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 996        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 997        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 998        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 999        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1000        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1001        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1002        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1003        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1004        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1005        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1006        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1007        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1008        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1009        { 0, }
1010};
1011
1012MODULE_DEVICE_TABLE(pci, i801_ids);
1013
1014#if defined CONFIG_X86 && defined CONFIG_DMI
1015static unsigned char apanel_addr;
1016
1017/* Scan the system ROM for the signature "FJKEYINF" */
1018static __init const void __iomem *bios_signature(const void __iomem *bios)
1019{
1020        ssize_t offset;
1021        const unsigned char signature[] = "FJKEYINF";
1022
1023        for (offset = 0; offset < 0x10000; offset += 0x10) {
1024                if (check_signature(bios + offset, signature,
1025                                    sizeof(signature)-1))
1026                        return bios + offset;
1027        }
1028        return NULL;
1029}
1030
1031static void __init input_apanel_init(void)
1032{
1033        void __iomem *bios;
1034        const void __iomem *p;
1035
1036        bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1037        p = bios_signature(bios);
1038        if (p) {
1039                /* just use the first address */
1040                apanel_addr = readb(p + 8 + 3) >> 1;
1041        }
1042        iounmap(bios);
1043}
1044
1045struct dmi_onboard_device_info {
1046        const char *name;
1047        u8 type;
1048        unsigned short i2c_addr;
1049        const char *i2c_type;
1050};
1051
1052static const struct dmi_onboard_device_info dmi_devices[] = {
1053        { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1054        { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1055        { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1056};
1057
1058static void dmi_check_onboard_device(u8 type, const char *name,
1059                                     struct i2c_adapter *adap)
1060{
1061        int i;
1062        struct i2c_board_info info;
1063
1064        for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1065                /* & ~0x80, ignore enabled/disabled bit */
1066                if ((type & ~0x80) != dmi_devices[i].type)
1067                        continue;
1068                if (strcasecmp(name, dmi_devices[i].name))
1069                        continue;
1070
1071                memset(&info, 0, sizeof(struct i2c_board_info));
1072                info.addr = dmi_devices[i].i2c_addr;
1073                strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1074                i2c_new_device(adap, &info);
1075                break;
1076        }
1077}
1078
1079/* We use our own function to check for onboard devices instead of
1080   dmi_find_device() as some buggy BIOS's have the devices we are interested
1081   in marked as disabled */
1082static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1083{
1084        int i, count;
1085
1086        if (dm->type != 10)
1087                return;
1088
1089        count = (dm->length - sizeof(struct dmi_header)) / 2;
1090        for (i = 0; i < count; i++) {
1091                const u8 *d = (char *)(dm + 1) + (i * 2);
1092                const char *name = ((char *) dm) + dm->length;
1093                u8 type = d[0];
1094                u8 s = d[1];
1095
1096                if (!s)
1097                        continue;
1098                s--;
1099                while (s > 0 && name[0]) {
1100                        name += strlen(name) + 1;
1101                        s--;
1102                }
1103                if (name[0] == 0) /* Bogus string reference */
1104                        continue;
1105
1106                dmi_check_onboard_device(type, name, adap);
1107        }
1108}
1109
1110/* Register optional slaves */
1111static void i801_probe_optional_slaves(struct i801_priv *priv)
1112{
1113        /* Only register slaves on main SMBus channel */
1114        if (priv->features & FEATURE_IDF)
1115                return;
1116
1117        if (apanel_addr) {
1118                struct i2c_board_info info;
1119
1120                memset(&info, 0, sizeof(struct i2c_board_info));
1121                info.addr = apanel_addr;
1122                strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1123                i2c_new_device(&priv->adapter, &info);
1124        }
1125
1126        if (dmi_name_in_vendors("FUJITSU"))
1127                dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1128}
1129#else
1130static void __init input_apanel_init(void) {}
1131static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1132#endif  /* CONFIG_X86 && CONFIG_DMI */
1133
1134#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1135static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1136        .gpio_chip = "gpio_ich",
1137        .values = { 0x02, 0x03 },
1138        .n_values = 2,
1139        .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1140        .gpios = { 52, 53 },
1141        .n_gpios = 2,
1142};
1143
1144static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1145        .gpio_chip = "gpio_ich",
1146        .values = { 0x02, 0x03, 0x01 },
1147        .n_values = 3,
1148        .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1149        .gpios = { 52, 53 },
1150        .n_gpios = 2,
1151};
1152
1153static const struct dmi_system_id mux_dmi_table[] = {
1154        {
1155                .matches = {
1156                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1157                        DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1158                },
1159                .driver_data = &i801_mux_config_asus_z8_d12,
1160        },
1161        {
1162                .matches = {
1163                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1164                        DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1165                },
1166                .driver_data = &i801_mux_config_asus_z8_d12,
1167        },
1168        {
1169                .matches = {
1170                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1171                        DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1172                },
1173                .driver_data = &i801_mux_config_asus_z8_d12,
1174        },
1175        {
1176                .matches = {
1177                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1178                        DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1179                },
1180                .driver_data = &i801_mux_config_asus_z8_d12,
1181        },
1182        {
1183                .matches = {
1184                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1185                        DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1186                },
1187                .driver_data = &i801_mux_config_asus_z8_d12,
1188        },
1189        {
1190                .matches = {
1191                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1192                        DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1193                },
1194                .driver_data = &i801_mux_config_asus_z8_d12,
1195        },
1196        {
1197                .matches = {
1198                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1199                        DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1200                },
1201                .driver_data = &i801_mux_config_asus_z8_d18,
1202        },
1203        {
1204                .matches = {
1205                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1206                        DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1207                },
1208                .driver_data = &i801_mux_config_asus_z8_d18,
1209        },
1210        {
1211                .matches = {
1212                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1213                        DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1214                },
1215                .driver_data = &i801_mux_config_asus_z8_d12,
1216        },
1217        { }
1218};
1219
1220/* Setup multiplexing if needed */
1221static int i801_add_mux(struct i801_priv *priv)
1222{
1223        struct device *dev = &priv->adapter.dev;
1224        const struct i801_mux_config *mux_config;
1225        struct i2c_mux_gpio_platform_data gpio_data;
1226        int err;
1227
1228        if (!priv->mux_drvdata)
1229                return 0;
1230        mux_config = priv->mux_drvdata;
1231
1232        /* Prepare the platform data */
1233        memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1234        gpio_data.parent = priv->adapter.nr;
1235        gpio_data.values = mux_config->values;
1236        gpio_data.n_values = mux_config->n_values;
1237        gpio_data.classes = mux_config->classes;
1238        gpio_data.gpio_chip = mux_config->gpio_chip;
1239        gpio_data.gpios = mux_config->gpios;
1240        gpio_data.n_gpios = mux_config->n_gpios;
1241        gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1242
1243        /* Register the mux device */
1244        priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1245                                PLATFORM_DEVID_AUTO, &gpio_data,
1246                                sizeof(struct i2c_mux_gpio_platform_data));
1247        if (IS_ERR(priv->mux_pdev)) {
1248                err = PTR_ERR(priv->mux_pdev);
1249                priv->mux_pdev = NULL;
1250                dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1251                return err;
1252        }
1253
1254        return 0;
1255}
1256
1257static void i801_del_mux(struct i801_priv *priv)
1258{
1259        if (priv->mux_pdev)
1260                platform_device_unregister(priv->mux_pdev);
1261}
1262
1263static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1264{
1265        const struct dmi_system_id *id;
1266        const struct i801_mux_config *mux_config;
1267        unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1268        int i;
1269
1270        id = dmi_first_match(mux_dmi_table);
1271        if (id) {
1272                /* Remove branch classes from trunk */
1273                mux_config = id->driver_data;
1274                for (i = 0; i < mux_config->n_values; i++)
1275                        class &= ~mux_config->classes[i];
1276
1277                /* Remember for later */
1278                priv->mux_drvdata = mux_config;
1279        }
1280
1281        return class;
1282}
1283#else
1284static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1285static inline void i801_del_mux(struct i801_priv *priv) { }
1286
1287static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1288{
1289        return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1290}
1291#endif
1292
1293static const struct itco_wdt_platform_data tco_platform_data = {
1294        .name = "Intel PCH",
1295        .version = 4,
1296};
1297
1298static DEFINE_SPINLOCK(p2sb_spinlock);
1299
1300static void i801_add_tco(struct i801_priv *priv)
1301{
1302        struct pci_dev *pci_dev = priv->pci_dev;
1303        struct resource tco_res[3], *res;
1304        struct platform_device *pdev;
1305        unsigned int devfn;
1306        u32 tco_base, tco_ctl;
1307        u32 base_addr, ctrl_val;
1308        u64 base64_addr;
1309
1310        if (!(priv->features & FEATURE_TCO))
1311                return;
1312
1313        pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1314        pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1315        if (!(tco_ctl & TCOCTL_EN))
1316                return;
1317
1318        memset(tco_res, 0, sizeof(tco_res));
1319
1320        res = &tco_res[ICH_RES_IO_TCO];
1321        res->start = tco_base & ~1;
1322        res->end = res->start + 32 - 1;
1323        res->flags = IORESOURCE_IO;
1324
1325        /*
1326         * Power Management registers.
1327         */
1328        devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1329        pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1330
1331        res = &tco_res[ICH_RES_IO_SMI];
1332        res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1333        res->end = res->start + 3;
1334        res->flags = IORESOURCE_IO;
1335
1336        /*
1337         * Enable the ACPI I/O space.
1338         */
1339        pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1340        ctrl_val |= ACPICTRL_EN;
1341        pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1342
1343        /*
1344         * We must access the NO_REBOOT bit over the Primary to Sideband
1345         * bridge (P2SB). The BIOS prevents the P2SB device from being
1346         * enumerated by the PCI subsystem, so we need to unhide/hide it
1347         * to lookup the P2SB BAR.
1348         */
1349        spin_lock(&p2sb_spinlock);
1350
1351        devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1352
1353        /* Unhide the P2SB device */
1354        pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1355
1356        pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1357        base64_addr = base_addr & 0xfffffff0;
1358
1359        pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1360        base64_addr |= (u64)base_addr << 32;
1361
1362        /* Hide the P2SB device */
1363        pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1364        spin_unlock(&p2sb_spinlock);
1365
1366        res = &tco_res[ICH_RES_MEM_OFF];
1367        res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1368        res->end = res->start + 3;
1369        res->flags = IORESOURCE_MEM;
1370
1371        pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1372                                                 tco_res, 3, &tco_platform_data,
1373                                                 sizeof(tco_platform_data));
1374        if (IS_ERR(pdev)) {
1375                dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1376                return;
1377        }
1378
1379        priv->tco_pdev = pdev;
1380}
1381
1382#ifdef CONFIG_ACPI
1383static acpi_status
1384i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1385                     u64 *value, void *handler_context, void *region_context)
1386{
1387        struct i801_priv *priv = handler_context;
1388        struct pci_dev *pdev = priv->pci_dev;
1389        acpi_status status;
1390
1391        /*
1392         * Once BIOS AML code touches the OpRegion we warn and inhibit any
1393         * further access from the driver itself. This device is now owned
1394         * by the system firmware.
1395         */
1396        mutex_lock(&priv->acpi_lock);
1397
1398        if (!priv->acpi_reserved) {
1399                priv->acpi_reserved = true;
1400
1401                dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1402                dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1403
1404                /*
1405                 * BIOS is accessing the host controller so prevent it from
1406                 * suspending automatically from now on.
1407                 */
1408                pm_runtime_get_sync(&pdev->dev);
1409        }
1410
1411        if ((function & ACPI_IO_MASK) == ACPI_READ)
1412                status = acpi_os_read_port(address, (u32 *)value, bits);
1413        else
1414                status = acpi_os_write_port(address, (u32)*value, bits);
1415
1416        mutex_unlock(&priv->acpi_lock);
1417
1418        return status;
1419}
1420
1421static int i801_acpi_probe(struct i801_priv *priv)
1422{
1423        struct acpi_device *adev;
1424        acpi_status status;
1425
1426        adev = ACPI_COMPANION(&priv->pci_dev->dev);
1427        if (adev) {
1428                status = acpi_install_address_space_handler(adev->handle,
1429                                ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1430                                NULL, priv);
1431                if (ACPI_SUCCESS(status))
1432                        return 0;
1433        }
1434
1435        return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1436}
1437
1438static void i801_acpi_remove(struct i801_priv *priv)
1439{
1440        struct acpi_device *adev;
1441
1442        adev = ACPI_COMPANION(&priv->pci_dev->dev);
1443        if (!adev)
1444                return;
1445
1446        acpi_remove_address_space_handler(adev->handle,
1447                ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1448
1449        mutex_lock(&priv->acpi_lock);
1450        if (priv->acpi_reserved)
1451                pm_runtime_put(&priv->pci_dev->dev);
1452        mutex_unlock(&priv->acpi_lock);
1453}
1454#else
1455static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1456static inline void i801_acpi_remove(struct i801_priv *priv) { }
1457#endif
1458
1459static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1460{
1461        unsigned char temp;
1462        int err, i;
1463        struct i801_priv *priv;
1464
1465        priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1466        if (!priv)
1467                return -ENOMEM;
1468
1469        i2c_set_adapdata(&priv->adapter, priv);
1470        priv->adapter.owner = THIS_MODULE;
1471        priv->adapter.class = i801_get_adapter_class(priv);
1472        priv->adapter.algo = &smbus_algorithm;
1473        priv->adapter.dev.parent = &dev->dev;
1474        ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1475        priv->adapter.retries = 3;
1476        mutex_init(&priv->acpi_lock);
1477
1478        priv->pci_dev = dev;
1479        switch (dev->device) {
1480        case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1481        case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1482        case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1483        case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1484        case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1485                priv->features |= FEATURE_I2C_BLOCK_READ;
1486                priv->features |= FEATURE_IRQ;
1487                priv->features |= FEATURE_SMBUS_PEC;
1488                priv->features |= FEATURE_BLOCK_BUFFER;
1489                priv->features |= FEATURE_TCO;
1490                priv->features |= FEATURE_HOST_NOTIFY;
1491                break;
1492
1493        case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1494        case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1495        case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1496        case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1497        case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1498        case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1499                priv->features |= FEATURE_IDF;
1500                /* fall through */
1501        default:
1502                priv->features |= FEATURE_I2C_BLOCK_READ;
1503                priv->features |= FEATURE_IRQ;
1504                /* fall through */
1505        case PCI_DEVICE_ID_INTEL_82801DB_3:
1506                priv->features |= FEATURE_SMBUS_PEC;
1507                priv->features |= FEATURE_BLOCK_BUFFER;
1508                /* fall through */
1509        case PCI_DEVICE_ID_INTEL_82801CA_3:
1510                priv->features |= FEATURE_HOST_NOTIFY;
1511                /* fall through */
1512        case PCI_DEVICE_ID_INTEL_82801BA_2:
1513        case PCI_DEVICE_ID_INTEL_82801AB_3:
1514        case PCI_DEVICE_ID_INTEL_82801AA_3:
1515                break;
1516        }
1517
1518        /* Disable features on user request */
1519        for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1520                if (priv->features & disable_features & (1 << i))
1521                        dev_notice(&dev->dev, "%s disabled by user\n",
1522                                   i801_feature_names[i]);
1523        }
1524        priv->features &= ~disable_features;
1525
1526        err = pcim_enable_device(dev);
1527        if (err) {
1528                dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1529                        err);
1530                return err;
1531        }
1532        pcim_pin_device(dev);
1533
1534        /* Determine the address of the SMBus area */
1535        priv->smba = pci_resource_start(dev, SMBBAR);
1536        if (!priv->smba) {
1537                dev_err(&dev->dev,
1538                        "SMBus base address uninitialized, upgrade BIOS\n");
1539                return -ENODEV;
1540        }
1541
1542        if (i801_acpi_probe(priv))
1543                return -ENODEV;
1544
1545        err = pcim_iomap_regions(dev, 1 << SMBBAR,
1546                                 dev_driver_string(&dev->dev));
1547        if (err) {
1548                dev_err(&dev->dev,
1549                        "Failed to request SMBus region 0x%lx-0x%Lx\n",
1550                        priv->smba,
1551                        (unsigned long long)pci_resource_end(dev, SMBBAR));
1552                i801_acpi_remove(priv);
1553                return err;
1554        }
1555
1556        pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1557        priv->original_hstcfg = temp;
1558        temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1559        if (!(temp & SMBHSTCFG_HST_EN)) {
1560                dev_info(&dev->dev, "Enabling SMBus device\n");
1561                temp |= SMBHSTCFG_HST_EN;
1562        }
1563        pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1564
1565        if (temp & SMBHSTCFG_SMB_SMI_EN) {
1566                dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1567                /* Disable SMBus interrupt feature if SMBus using SMI# */
1568                priv->features &= ~FEATURE_IRQ;
1569        }
1570
1571        /* Clear special mode bits */
1572        if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1573                outb_p(inb_p(SMBAUXCTL(priv)) &
1574                       ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1575
1576        /* Default timeout in interrupt mode: 200 ms */
1577        priv->adapter.timeout = HZ / 5;
1578
1579        if (priv->features & FEATURE_IRQ) {
1580                u16 pcictl, pcists;
1581
1582                /* Complain if an interrupt is already pending */
1583                pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1584                if (pcists & SMBPCISTS_INTS)
1585                        dev_warn(&dev->dev, "An interrupt is pending!\n");
1586
1587                /* Check if interrupts have been disabled */
1588                pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1589                if (pcictl & SMBPCICTL_INTDIS) {
1590                        dev_info(&dev->dev, "Interrupts are disabled\n");
1591                        priv->features &= ~FEATURE_IRQ;
1592                }
1593        }
1594
1595        if (priv->features & FEATURE_IRQ) {
1596                init_waitqueue_head(&priv->waitq);
1597
1598                err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1599                                       IRQF_SHARED,
1600                                       dev_driver_string(&dev->dev), priv);
1601                if (err) {
1602                        dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1603                                dev->irq, err);
1604                        priv->features &= ~FEATURE_IRQ;
1605                }
1606        }
1607        dev_info(&dev->dev, "SMBus using %s\n",
1608                 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1609
1610        i801_add_tco(priv);
1611
1612        snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1613                "SMBus I801 adapter at %04lx", priv->smba);
1614        err = i2c_add_adapter(&priv->adapter);
1615        if (err) {
1616                dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1617                i801_acpi_remove(priv);
1618                return err;
1619        }
1620
1621        /*
1622         * Enable Host Notify for chips that supports it.
1623         * It is done after i2c_add_adapter() so that we are sure the work queue
1624         * is not used if i2c_add_adapter() fails.
1625         */
1626        err = i801_enable_host_notify(&priv->adapter);
1627        if (err && err != -ENOTSUPP)
1628                dev_warn(&dev->dev, "Unable to enable SMBus Host Notify\n");
1629
1630        i801_probe_optional_slaves(priv);
1631        /* We ignore errors - multiplexing is optional */
1632        i801_add_mux(priv);
1633
1634        pci_set_drvdata(dev, priv);
1635
1636        pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1637        pm_runtime_use_autosuspend(&dev->dev);
1638        pm_runtime_put_autosuspend(&dev->dev);
1639        pm_runtime_allow(&dev->dev);
1640
1641        return 0;
1642}
1643
1644static void i801_remove(struct pci_dev *dev)
1645{
1646        struct i801_priv *priv = pci_get_drvdata(dev);
1647
1648        pm_runtime_forbid(&dev->dev);
1649        pm_runtime_get_noresume(&dev->dev);
1650
1651        i801_del_mux(priv);
1652        i2c_del_adapter(&priv->adapter);
1653        i801_acpi_remove(priv);
1654        pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1655
1656        platform_device_unregister(priv->tco_pdev);
1657
1658        /*
1659         * do not call pci_disable_device(dev) since it can cause hard hangs on
1660         * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1661         */
1662}
1663
1664#ifdef CONFIG_PM
1665static int i801_suspend(struct device *dev)
1666{
1667        struct pci_dev *pci_dev = to_pci_dev(dev);
1668        struct i801_priv *priv = pci_get_drvdata(pci_dev);
1669
1670        pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1671        return 0;
1672}
1673
1674static int i801_resume(struct device *dev)
1675{
1676        struct pci_dev *pci_dev = to_pci_dev(dev);
1677        struct i801_priv *priv = pci_get_drvdata(pci_dev);
1678        int err;
1679
1680        err = i801_enable_host_notify(&priv->adapter);
1681        if (err && err != -ENOTSUPP)
1682                dev_warn(dev, "Unable to enable SMBus Host Notify\n");
1683
1684        return 0;
1685}
1686#endif
1687
1688static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend,
1689                            i801_resume, NULL);
1690
1691static struct pci_driver i801_driver = {
1692        .name           = "i801_smbus",
1693        .id_table       = i801_ids,
1694        .probe          = i801_probe,
1695        .remove         = i801_remove,
1696        .driver         = {
1697                .pm     = &i801_pm_ops,
1698        },
1699};
1700
1701static int __init i2c_i801_init(void)
1702{
1703        if (dmi_name_in_vendors("FUJITSU"))
1704                input_apanel_init();
1705        return pci_register_driver(&i801_driver);
1706}
1707
1708static void __exit i2c_i801_exit(void)
1709{
1710        pci_unregister_driver(&i801_driver);
1711}
1712
1713MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1714MODULE_DESCRIPTION("I801 SMBus driver");
1715MODULE_LICENSE("GPL");
1716
1717module_init(i2c_i801_init);
1718module_exit(i2c_i801_exit);
1719