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23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/err.h>
26#include <linux/module.h>
27#include <linux/list.h>
28#include <linux/smp.h>
29#include <linux/cpu.h>
30#include <linux/cpu_pm.h>
31#include <linux/cpumask.h>
32#include <linux/io.h>
33#include <linux/of.h>
34#include <linux/of_address.h>
35#include <linux/of_irq.h>
36#include <linux/acpi.h>
37#include <linux/irqdomain.h>
38#include <linux/interrupt.h>
39#include <linux/percpu.h>
40#include <linux/slab.h>
41#include <linux/irqchip.h>
42#include <linux/irqchip/chained_irq.h>
43#include <linux/irqchip/arm-gic.h>
44
45#include <asm/cputype.h>
46#include <asm/irq.h>
47#include <asm/exception.h>
48#include <asm/smp_plat.h>
49#include <asm/virt.h>
50
51#include "irq-gic-common.h"
52
53#ifdef CONFIG_ARM64
54#include <asm/cpufeature.h>
55
56static void gic_check_cpu_features(void)
57{
58 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
59 TAINT_CPU_OUT_OF_SPEC,
60 "GICv3 system registers enabled, broken firmware!\n");
61}
62#else
63#define gic_check_cpu_features() do { } while(0)
64#endif
65
66union gic_base {
67 void __iomem *common_base;
68 void __percpu * __iomem *percpu_base;
69};
70
71struct gic_chip_data {
72 struct irq_chip chip;
73 union gic_base dist_base;
74 union gic_base cpu_base;
75 void __iomem *raw_dist_base;
76 void __iomem *raw_cpu_base;
77 u32 percpu_offset;
78#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
79 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
80 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
81 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
82 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
83 u32 __percpu *saved_ppi_enable;
84 u32 __percpu *saved_ppi_active;
85 u32 __percpu *saved_ppi_conf;
86#endif
87 struct irq_domain *domain;
88 unsigned int gic_irqs;
89#ifdef CONFIG_GIC_NON_BANKED
90 void __iomem *(*get_base)(union gic_base *);
91#endif
92};
93
94static DEFINE_RAW_SPINLOCK(irq_controller_lock);
95
96
97
98
99
100
101#define NR_GIC_CPU_IF 8
102static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
103
104static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
105
106static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
107
108static struct gic_kvm_info gic_v2_kvm_info;
109
110#ifdef CONFIG_GIC_NON_BANKED
111static void __iomem *gic_get_percpu_base(union gic_base *base)
112{
113 return raw_cpu_read(*base->percpu_base);
114}
115
116static void __iomem *gic_get_common_base(union gic_base *base)
117{
118 return base->common_base;
119}
120
121static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
122{
123 return data->get_base(&data->dist_base);
124}
125
126static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
127{
128 return data->get_base(&data->cpu_base);
129}
130
131static inline void gic_set_base_accessor(struct gic_chip_data *data,
132 void __iomem *(*f)(union gic_base *))
133{
134 data->get_base = f;
135}
136#else
137#define gic_data_dist_base(d) ((d)->dist_base.common_base)
138#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
139#define gic_set_base_accessor(d, f)
140#endif
141
142static inline void __iomem *gic_dist_base(struct irq_data *d)
143{
144 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
145 return gic_data_dist_base(gic_data);
146}
147
148static inline void __iomem *gic_cpu_base(struct irq_data *d)
149{
150 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
151 return gic_data_cpu_base(gic_data);
152}
153
154static inline unsigned int gic_irq(struct irq_data *d)
155{
156 return d->hwirq;
157}
158
159static inline bool cascading_gic_irq(struct irq_data *d)
160{
161 void *data = irq_data_get_irq_handler_data(d);
162
163
164
165
166
167 return data != NULL;
168}
169
170
171
172
173static void gic_poke_irq(struct irq_data *d, u32 offset)
174{
175 u32 mask = 1 << (gic_irq(d) % 32);
176 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
177}
178
179static int gic_peek_irq(struct irq_data *d, u32 offset)
180{
181 u32 mask = 1 << (gic_irq(d) % 32);
182 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
183}
184
185static void gic_mask_irq(struct irq_data *d)
186{
187 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
188}
189
190static void gic_eoimode1_mask_irq(struct irq_data *d)
191{
192 gic_mask_irq(d);
193
194
195
196
197
198
199
200
201 if (irqd_is_forwarded_to_vcpu(d))
202 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
203}
204
205static void gic_unmask_irq(struct irq_data *d)
206{
207 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
208}
209
210static void gic_eoi_irq(struct irq_data *d)
211{
212 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
213}
214
215static void gic_eoimode1_eoi_irq(struct irq_data *d)
216{
217
218 if (irqd_is_forwarded_to_vcpu(d))
219 return;
220
221 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
222}
223
224static int gic_irq_set_irqchip_state(struct irq_data *d,
225 enum irqchip_irq_state which, bool val)
226{
227 u32 reg;
228
229 switch (which) {
230 case IRQCHIP_STATE_PENDING:
231 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
232 break;
233
234 case IRQCHIP_STATE_ACTIVE:
235 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
236 break;
237
238 case IRQCHIP_STATE_MASKED:
239 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
240 break;
241
242 default:
243 return -EINVAL;
244 }
245
246 gic_poke_irq(d, reg);
247 return 0;
248}
249
250static int gic_irq_get_irqchip_state(struct irq_data *d,
251 enum irqchip_irq_state which, bool *val)
252{
253 switch (which) {
254 case IRQCHIP_STATE_PENDING:
255 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
256 break;
257
258 case IRQCHIP_STATE_ACTIVE:
259 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
260 break;
261
262 case IRQCHIP_STATE_MASKED:
263 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
264 break;
265
266 default:
267 return -EINVAL;
268 }
269
270 return 0;
271}
272
273static int gic_set_type(struct irq_data *d, unsigned int type)
274{
275 void __iomem *base = gic_dist_base(d);
276 unsigned int gicirq = gic_irq(d);
277
278
279 if (gicirq < 16)
280 return -EINVAL;
281
282
283 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
284 type != IRQ_TYPE_EDGE_RISING)
285 return -EINVAL;
286
287 return gic_configure_irq(gicirq, type, base, NULL);
288}
289
290static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
291{
292
293 if (cascading_gic_irq(d))
294 return -EINVAL;
295
296 if (vcpu)
297 irqd_set_forwarded_to_vcpu(d);
298 else
299 irqd_clr_forwarded_to_vcpu(d);
300 return 0;
301}
302
303#ifdef CONFIG_SMP
304static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
305 bool force)
306{
307 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
308 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
309 u32 val, mask, bit;
310 unsigned long flags;
311
312 if (!force)
313 cpu = cpumask_any_and(mask_val, cpu_online_mask);
314 else
315 cpu = cpumask_first(mask_val);
316
317 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
318 return -EINVAL;
319
320 raw_spin_lock_irqsave(&irq_controller_lock, flags);
321 mask = 0xff << shift;
322 bit = gic_cpu_map[cpu] << shift;
323 val = readl_relaxed(reg) & ~mask;
324 writel_relaxed(val | bit, reg);
325 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
326
327 return IRQ_SET_MASK_OK_DONE;
328}
329#endif
330
331static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
332{
333 u32 irqstat, irqnr;
334 struct gic_chip_data *gic = &gic_data[0];
335 void __iomem *cpu_base = gic_data_cpu_base(gic);
336
337 do {
338 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
339 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
340
341 if (likely(irqnr > 15 && irqnr < 1020)) {
342 if (static_key_true(&supports_deactivate))
343 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
344 handle_domain_irq(gic->domain, irqnr, regs);
345 continue;
346 }
347 if (irqnr < 16) {
348 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
349 if (static_key_true(&supports_deactivate))
350 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
351#ifdef CONFIG_SMP
352
353
354
355
356
357
358
359 smp_rmb();
360 handle_IPI(irqnr, regs);
361#endif
362 continue;
363 }
364 break;
365 } while (1);
366}
367
368static void gic_handle_cascade_irq(struct irq_desc *desc)
369{
370 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
371 struct irq_chip *chip = irq_desc_get_chip(desc);
372 unsigned int cascade_irq, gic_irq;
373 unsigned long status;
374
375 chained_irq_enter(chip, desc);
376
377 raw_spin_lock(&irq_controller_lock);
378 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
379 raw_spin_unlock(&irq_controller_lock);
380
381 gic_irq = (status & GICC_IAR_INT_ID_MASK);
382 if (gic_irq == GICC_INT_SPURIOUS)
383 goto out;
384
385 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
386 if (unlikely(gic_irq < 32 || gic_irq > 1020))
387 handle_bad_irq(desc);
388 else
389 generic_handle_irq(cascade_irq);
390
391 out:
392 chained_irq_exit(chip, desc);
393}
394
395static struct irq_chip gic_chip = {
396 .irq_mask = gic_mask_irq,
397 .irq_unmask = gic_unmask_irq,
398 .irq_eoi = gic_eoi_irq,
399 .irq_set_type = gic_set_type,
400 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
401 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
402 .flags = IRQCHIP_SET_TYPE_MASKED |
403 IRQCHIP_SKIP_SET_WAKE |
404 IRQCHIP_MASK_ON_SUSPEND,
405};
406
407void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
408{
409 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
410 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
411 &gic_data[gic_nr]);
412}
413
414static u8 gic_get_cpumask(struct gic_chip_data *gic)
415{
416 void __iomem *base = gic_data_dist_base(gic);
417 u32 mask, i;
418
419 for (i = mask = 0; i < 32; i += 4) {
420 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
421 mask |= mask >> 16;
422 mask |= mask >> 8;
423 if (mask)
424 break;
425 }
426
427 if (!mask && num_possible_cpus() > 1)
428 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
429
430 return mask;
431}
432
433static void gic_cpu_if_up(struct gic_chip_data *gic)
434{
435 void __iomem *cpu_base = gic_data_cpu_base(gic);
436 u32 bypass = 0;
437 u32 mode = 0;
438
439 if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
440 mode = GIC_CPU_CTRL_EOImodeNS;
441
442
443
444
445 bypass = readl(cpu_base + GIC_CPU_CTRL);
446 bypass &= GICC_DIS_BYPASS_MASK;
447
448 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
449}
450
451
452static void gic_dist_init(struct gic_chip_data *gic)
453{
454 unsigned int i;
455 u32 cpumask;
456 unsigned int gic_irqs = gic->gic_irqs;
457 void __iomem *base = gic_data_dist_base(gic);
458
459 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
460
461
462
463
464 cpumask = gic_get_cpumask(gic);
465 cpumask |= cpumask << 8;
466 cpumask |= cpumask << 16;
467 for (i = 32; i < gic_irqs; i += 4)
468 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
469
470 gic_dist_config(base, gic_irqs, NULL);
471
472 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
473}
474
475static int gic_cpu_init(struct gic_chip_data *gic)
476{
477 void __iomem *dist_base = gic_data_dist_base(gic);
478 void __iomem *base = gic_data_cpu_base(gic);
479 unsigned int cpu_mask, cpu = smp_processor_id();
480 int i;
481
482
483
484
485
486
487 if (gic == &gic_data[0]) {
488
489
490
491 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
492 return -EINVAL;
493
494 gic_check_cpu_features();
495 cpu_mask = gic_get_cpumask(gic);
496 gic_cpu_map[cpu] = cpu_mask;
497
498
499
500
501
502 for (i = 0; i < NR_GIC_CPU_IF; i++)
503 if (i != cpu)
504 gic_cpu_map[i] &= ~cpu_mask;
505 }
506
507 gic_cpu_config(dist_base, NULL);
508
509 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
510 gic_cpu_if_up(gic);
511
512 return 0;
513}
514
515int gic_cpu_if_down(unsigned int gic_nr)
516{
517 void __iomem *cpu_base;
518 u32 val = 0;
519
520 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
521 return -EINVAL;
522
523 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
524 val = readl(cpu_base + GIC_CPU_CTRL);
525 val &= ~GICC_ENABLE;
526 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
527
528 return 0;
529}
530
531#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
532
533
534
535
536
537
538void gic_dist_save(struct gic_chip_data *gic)
539{
540 unsigned int gic_irqs;
541 void __iomem *dist_base;
542 int i;
543
544 if (WARN_ON(!gic))
545 return;
546
547 gic_irqs = gic->gic_irqs;
548 dist_base = gic_data_dist_base(gic);
549
550 if (!dist_base)
551 return;
552
553 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
554 gic->saved_spi_conf[i] =
555 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
556
557 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
558 gic->saved_spi_target[i] =
559 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
560
561 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
562 gic->saved_spi_enable[i] =
563 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
564
565 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
566 gic->saved_spi_active[i] =
567 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
568}
569
570
571
572
573
574
575
576
577void gic_dist_restore(struct gic_chip_data *gic)
578{
579 unsigned int gic_irqs;
580 unsigned int i;
581 void __iomem *dist_base;
582
583 if (WARN_ON(!gic))
584 return;
585
586 gic_irqs = gic->gic_irqs;
587 dist_base = gic_data_dist_base(gic);
588
589 if (!dist_base)
590 return;
591
592 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
593
594 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
595 writel_relaxed(gic->saved_spi_conf[i],
596 dist_base + GIC_DIST_CONFIG + i * 4);
597
598 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
599 writel_relaxed(GICD_INT_DEF_PRI_X4,
600 dist_base + GIC_DIST_PRI + i * 4);
601
602 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
603 writel_relaxed(gic->saved_spi_target[i],
604 dist_base + GIC_DIST_TARGET + i * 4);
605
606 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
607 writel_relaxed(GICD_INT_EN_CLR_X32,
608 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
609 writel_relaxed(gic->saved_spi_enable[i],
610 dist_base + GIC_DIST_ENABLE_SET + i * 4);
611 }
612
613 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
614 writel_relaxed(GICD_INT_EN_CLR_X32,
615 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
616 writel_relaxed(gic->saved_spi_active[i],
617 dist_base + GIC_DIST_ACTIVE_SET + i * 4);
618 }
619
620 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
621}
622
623void gic_cpu_save(struct gic_chip_data *gic)
624{
625 int i;
626 u32 *ptr;
627 void __iomem *dist_base;
628 void __iomem *cpu_base;
629
630 if (WARN_ON(!gic))
631 return;
632
633 dist_base = gic_data_dist_base(gic);
634 cpu_base = gic_data_cpu_base(gic);
635
636 if (!dist_base || !cpu_base)
637 return;
638
639 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
640 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
641 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
642
643 ptr = raw_cpu_ptr(gic->saved_ppi_active);
644 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
645 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
646
647 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
648 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
649 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
650
651}
652
653void gic_cpu_restore(struct gic_chip_data *gic)
654{
655 int i;
656 u32 *ptr;
657 void __iomem *dist_base;
658 void __iomem *cpu_base;
659
660 if (WARN_ON(!gic))
661 return;
662
663 dist_base = gic_data_dist_base(gic);
664 cpu_base = gic_data_cpu_base(gic);
665
666 if (!dist_base || !cpu_base)
667 return;
668
669 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
670 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
671 writel_relaxed(GICD_INT_EN_CLR_X32,
672 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
673 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
674 }
675
676 ptr = raw_cpu_ptr(gic->saved_ppi_active);
677 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
678 writel_relaxed(GICD_INT_EN_CLR_X32,
679 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
680 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
681 }
682
683 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
684 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
685 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
686
687 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
688 writel_relaxed(GICD_INT_DEF_PRI_X4,
689 dist_base + GIC_DIST_PRI + i * 4);
690
691 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
692 gic_cpu_if_up(gic);
693}
694
695static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
696{
697 int i;
698
699 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
700#ifdef CONFIG_GIC_NON_BANKED
701
702 if (!gic_data[i].get_base)
703 continue;
704#endif
705 switch (cmd) {
706 case CPU_PM_ENTER:
707 gic_cpu_save(&gic_data[i]);
708 break;
709 case CPU_PM_ENTER_FAILED:
710 case CPU_PM_EXIT:
711 gic_cpu_restore(&gic_data[i]);
712 break;
713 case CPU_CLUSTER_PM_ENTER:
714 gic_dist_save(&gic_data[i]);
715 break;
716 case CPU_CLUSTER_PM_ENTER_FAILED:
717 case CPU_CLUSTER_PM_EXIT:
718 gic_dist_restore(&gic_data[i]);
719 break;
720 }
721 }
722
723 return NOTIFY_OK;
724}
725
726static struct notifier_block gic_notifier_block = {
727 .notifier_call = gic_notifier,
728};
729
730static int gic_pm_init(struct gic_chip_data *gic)
731{
732 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
733 sizeof(u32));
734 if (WARN_ON(!gic->saved_ppi_enable))
735 return -ENOMEM;
736
737 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
738 sizeof(u32));
739 if (WARN_ON(!gic->saved_ppi_active))
740 goto free_ppi_enable;
741
742 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
743 sizeof(u32));
744 if (WARN_ON(!gic->saved_ppi_conf))
745 goto free_ppi_active;
746
747 if (gic == &gic_data[0])
748 cpu_pm_register_notifier(&gic_notifier_block);
749
750 return 0;
751
752free_ppi_active:
753 free_percpu(gic->saved_ppi_active);
754free_ppi_enable:
755 free_percpu(gic->saved_ppi_enable);
756
757 return -ENOMEM;
758}
759#else
760static int gic_pm_init(struct gic_chip_data *gic)
761{
762 return 0;
763}
764#endif
765
766#ifdef CONFIG_SMP
767static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
768{
769 int cpu;
770 unsigned long flags, map = 0;
771
772 if (unlikely(nr_cpu_ids == 1)) {
773
774 writel_relaxed(2 << 24 | irq,
775 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
776 return;
777 }
778
779 raw_spin_lock_irqsave(&irq_controller_lock, flags);
780
781
782 for_each_cpu(cpu, mask)
783 map |= gic_cpu_map[cpu];
784
785
786
787
788
789 dmb(ishst);
790
791
792 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
793
794 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
795}
796#endif
797
798#ifdef CONFIG_BL_SWITCHER
799
800
801
802
803
804
805void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
806{
807 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
808 cpu_id = 1 << cpu_id;
809
810 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
811}
812
813
814
815
816
817
818
819
820
821
822int gic_get_cpu_id(unsigned int cpu)
823{
824 unsigned int cpu_bit;
825
826 if (cpu >= NR_GIC_CPU_IF)
827 return -1;
828 cpu_bit = gic_cpu_map[cpu];
829 if (cpu_bit & (cpu_bit - 1))
830 return -1;
831 return __ffs(cpu_bit);
832}
833
834
835
836
837
838
839
840
841
842
843
844void gic_migrate_target(unsigned int new_cpu_id)
845{
846 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
847 void __iomem *dist_base;
848 int i, ror_val, cpu = smp_processor_id();
849 u32 val, cur_target_mask, active_mask;
850
851 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
852
853 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
854 if (!dist_base)
855 return;
856 gic_irqs = gic_data[gic_nr].gic_irqs;
857
858 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
859 cur_target_mask = 0x01010101 << cur_cpu_id;
860 ror_val = (cur_cpu_id - new_cpu_id) & 31;
861
862 raw_spin_lock(&irq_controller_lock);
863
864
865 gic_cpu_map[cpu] = 1 << new_cpu_id;
866
867
868
869
870
871
872 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
873 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
874 active_mask = val & cur_target_mask;
875 if (active_mask) {
876 val &= ~active_mask;
877 val |= ror32(active_mask, ror_val);
878 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
879 }
880 }
881
882 raw_spin_unlock(&irq_controller_lock);
883
884
885
886
887
888
889
890
891
892
893
894 for (i = 0; i < 16; i += 4) {
895 int j;
896 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
897 if (!val)
898 continue;
899 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
900 for (j = i; j < i + 4; j++) {
901 if (val & 0xff)
902 writel_relaxed((1 << (new_cpu_id + 16)) | j,
903 dist_base + GIC_DIST_SOFTINT);
904 val >>= 8;
905 }
906 }
907}
908
909
910
911
912
913
914
915static unsigned long gic_dist_physaddr;
916
917unsigned long gic_get_sgir_physaddr(void)
918{
919 if (!gic_dist_physaddr)
920 return 0;
921 return gic_dist_physaddr + GIC_DIST_SOFTINT;
922}
923
924void __init gic_init_physaddr(struct device_node *node)
925{
926 struct resource res;
927 if (of_address_to_resource(node, 0, &res) == 0) {
928 gic_dist_physaddr = res.start;
929 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
930 }
931}
932
933#else
934#define gic_init_physaddr(node) do { } while (0)
935#endif
936
937static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
938 irq_hw_number_t hw)
939{
940 struct gic_chip_data *gic = d->host_data;
941
942 if (hw < 32) {
943 irq_set_percpu_devid(irq);
944 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
945 handle_percpu_devid_irq, NULL, NULL);
946 irq_set_status_flags(irq, IRQ_NOAUTOEN);
947 } else {
948 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
949 handle_fasteoi_irq, NULL, NULL);
950 irq_set_probe(irq);
951 }
952 return 0;
953}
954
955static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
956{
957}
958
959static int gic_irq_domain_translate(struct irq_domain *d,
960 struct irq_fwspec *fwspec,
961 unsigned long *hwirq,
962 unsigned int *type)
963{
964 if (is_of_node(fwspec->fwnode)) {
965 if (fwspec->param_count < 3)
966 return -EINVAL;
967
968
969 *hwirq = fwspec->param[1] + 16;
970
971
972
973
974
975 if (!fwspec->param[0])
976 *hwirq += 16;
977
978 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
979 return 0;
980 }
981
982 if (is_fwnode_irqchip(fwspec->fwnode)) {
983 if(fwspec->param_count != 2)
984 return -EINVAL;
985
986 *hwirq = fwspec->param[0];
987 *type = fwspec->param[1];
988 return 0;
989 }
990
991 return -EINVAL;
992}
993
994static int gic_starting_cpu(unsigned int cpu)
995{
996 gic_cpu_init(&gic_data[0]);
997 return 0;
998}
999
1000static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1001 unsigned int nr_irqs, void *arg)
1002{
1003 int i, ret;
1004 irq_hw_number_t hwirq;
1005 unsigned int type = IRQ_TYPE_NONE;
1006 struct irq_fwspec *fwspec = arg;
1007
1008 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1009 if (ret)
1010 return ret;
1011
1012 for (i = 0; i < nr_irqs; i++)
1013 gic_irq_domain_map(domain, virq + i, hwirq + i);
1014
1015 return 0;
1016}
1017
1018static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1019 .translate = gic_irq_domain_translate,
1020 .alloc = gic_irq_domain_alloc,
1021 .free = irq_domain_free_irqs_top,
1022};
1023
1024static const struct irq_domain_ops gic_irq_domain_ops = {
1025 .map = gic_irq_domain_map,
1026 .unmap = gic_irq_domain_unmap,
1027};
1028
1029static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1030 const char *name, bool use_eoimode1)
1031{
1032
1033 gic->chip = gic_chip;
1034 gic->chip.name = name;
1035 gic->chip.parent_device = dev;
1036
1037 if (use_eoimode1) {
1038 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1039 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1040 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1041 }
1042
1043#ifdef CONFIG_SMP
1044 if (gic == &gic_data[0])
1045 gic->chip.irq_set_affinity = gic_set_affinity;
1046#endif
1047}
1048
1049static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
1050 struct fwnode_handle *handle)
1051{
1052 irq_hw_number_t hwirq_base;
1053 int gic_irqs, irq_base, ret;
1054
1055 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1056
1057 unsigned int cpu;
1058
1059 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1060 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1061 if (WARN_ON(!gic->dist_base.percpu_base ||
1062 !gic->cpu_base.percpu_base)) {
1063 ret = -ENOMEM;
1064 goto error;
1065 }
1066
1067 for_each_possible_cpu(cpu) {
1068 u32 mpidr = cpu_logical_map(cpu);
1069 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1070 unsigned long offset = gic->percpu_offset * core_id;
1071 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1072 gic->raw_dist_base + offset;
1073 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1074 gic->raw_cpu_base + offset;
1075 }
1076
1077 gic_set_base_accessor(gic, gic_get_percpu_base);
1078 } else {
1079
1080 WARN(gic->percpu_offset,
1081 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1082 gic->percpu_offset);
1083 gic->dist_base.common_base = gic->raw_dist_base;
1084 gic->cpu_base.common_base = gic->raw_cpu_base;
1085 gic_set_base_accessor(gic, gic_get_common_base);
1086 }
1087
1088
1089
1090
1091
1092 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1093 gic_irqs = (gic_irqs + 1) * 32;
1094 if (gic_irqs > 1020)
1095 gic_irqs = 1020;
1096 gic->gic_irqs = gic_irqs;
1097
1098 if (handle) {
1099 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1100 &gic_irq_domain_hierarchy_ops,
1101 gic);
1102 } else {
1103
1104
1105
1106
1107 if (gic == &gic_data[0] && (irq_start & 31) > 0) {
1108 hwirq_base = 16;
1109 if (irq_start != -1)
1110 irq_start = (irq_start & ~31) + 16;
1111 } else {
1112 hwirq_base = 32;
1113 }
1114
1115 gic_irqs -= hwirq_base;
1116
1117 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1118 numa_node_id());
1119 if (irq_base < 0) {
1120 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1121 irq_start);
1122 irq_base = irq_start;
1123 }
1124
1125 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1126 hwirq_base, &gic_irq_domain_ops, gic);
1127 }
1128
1129 if (WARN_ON(!gic->domain)) {
1130 ret = -ENODEV;
1131 goto error;
1132 }
1133
1134 gic_dist_init(gic);
1135 ret = gic_cpu_init(gic);
1136 if (ret)
1137 goto error;
1138
1139 ret = gic_pm_init(gic);
1140 if (ret)
1141 goto error;
1142
1143 return 0;
1144
1145error:
1146 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1147 free_percpu(gic->dist_base.percpu_base);
1148 free_percpu(gic->cpu_base.percpu_base);
1149 }
1150
1151 return ret;
1152}
1153
1154static int __init __gic_init_bases(struct gic_chip_data *gic,
1155 int irq_start,
1156 struct fwnode_handle *handle)
1157{
1158 char *name;
1159 int i, ret;
1160
1161 if (WARN_ON(!gic || gic->domain))
1162 return -EINVAL;
1163
1164 if (gic == &gic_data[0]) {
1165
1166
1167
1168
1169
1170 for (i = 0; i < NR_GIC_CPU_IF; i++)
1171 gic_cpu_map[i] = 0xff;
1172#ifdef CONFIG_SMP
1173 set_smp_cross_call(gic_raise_softirq);
1174#endif
1175 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1176 "AP_IRQ_GIC_STARTING",
1177 gic_starting_cpu, NULL);
1178 set_handle_irq(gic_handle_irq);
1179 if (static_key_true(&supports_deactivate))
1180 pr_info("GIC: Using split EOI/Deactivate mode\n");
1181 }
1182
1183 if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) {
1184 name = kasprintf(GFP_KERNEL, "GICv2");
1185 gic_init_chip(gic, NULL, name, true);
1186 } else {
1187 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1188 gic_init_chip(gic, NULL, name, false);
1189 }
1190
1191 ret = gic_init_bases(gic, irq_start, handle);
1192 if (ret)
1193 kfree(name);
1194
1195 return ret;
1196}
1197
1198void __init gic_init(unsigned int gic_nr, int irq_start,
1199 void __iomem *dist_base, void __iomem *cpu_base)
1200{
1201 struct gic_chip_data *gic;
1202
1203 if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR))
1204 return;
1205
1206
1207
1208
1209
1210 static_key_slow_dec(&supports_deactivate);
1211
1212 gic = &gic_data[gic_nr];
1213 gic->raw_dist_base = dist_base;
1214 gic->raw_cpu_base = cpu_base;
1215
1216 __gic_init_bases(gic, irq_start, NULL);
1217}
1218
1219static void gic_teardown(struct gic_chip_data *gic)
1220{
1221 if (WARN_ON(!gic))
1222 return;
1223
1224 if (gic->raw_dist_base)
1225 iounmap(gic->raw_dist_base);
1226 if (gic->raw_cpu_base)
1227 iounmap(gic->raw_cpu_base);
1228}
1229
1230#ifdef CONFIG_OF
1231static int gic_cnt __initdata;
1232
1233static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1234{
1235 struct resource cpuif_res;
1236
1237 of_address_to_resource(node, 1, &cpuif_res);
1238
1239 if (!is_hyp_mode_available())
1240 return false;
1241 if (resource_size(&cpuif_res) < SZ_8K)
1242 return false;
1243 if (resource_size(&cpuif_res) == SZ_128K) {
1244 u32 val_low, val_high;
1245
1246
1247
1248
1249
1250
1251 val_low = readl_relaxed(*base + GIC_CPU_IDENT);
1252 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
1253 if ((val_low & 0xffff0fff) != 0x0202043B ||
1254 val_low != val_high)
1255 return false;
1256
1257
1258
1259
1260
1261
1262 *base += 0xf000;
1263 cpuif_res.start += 0xf000;
1264 pr_warn("GIC: Adjusting CPU interface base to %pa",
1265 &cpuif_res.start);
1266 }
1267
1268 return true;
1269}
1270
1271static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1272{
1273 if (!gic || !node)
1274 return -EINVAL;
1275
1276 gic->raw_dist_base = of_iomap(node, 0);
1277 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1278 goto error;
1279
1280 gic->raw_cpu_base = of_iomap(node, 1);
1281 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1282 goto error;
1283
1284 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1285 gic->percpu_offset = 0;
1286
1287 return 0;
1288
1289error:
1290 gic_teardown(gic);
1291
1292 return -ENOMEM;
1293}
1294
1295int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1296{
1297 int ret;
1298
1299 if (!dev || !dev->of_node || !gic || !irq)
1300 return -EINVAL;
1301
1302 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1303 if (!*gic)
1304 return -ENOMEM;
1305
1306 gic_init_chip(*gic, dev, dev->of_node->name, false);
1307
1308 ret = gic_of_setup(*gic, dev->of_node);
1309 if (ret)
1310 return ret;
1311
1312 ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode);
1313 if (ret) {
1314 gic_teardown(*gic);
1315 return ret;
1316 }
1317
1318 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1319
1320 return 0;
1321}
1322
1323static void __init gic_of_setup_kvm_info(struct device_node *node)
1324{
1325 int ret;
1326 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1327 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1328
1329 gic_v2_kvm_info.type = GIC_V2;
1330
1331 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1332 if (!gic_v2_kvm_info.maint_irq)
1333 return;
1334
1335 ret = of_address_to_resource(node, 2, vctrl_res);
1336 if (ret)
1337 return;
1338
1339 ret = of_address_to_resource(node, 3, vcpu_res);
1340 if (ret)
1341 return;
1342
1343 gic_set_kvm_info(&gic_v2_kvm_info);
1344}
1345
1346int __init
1347gic_of_init(struct device_node *node, struct device_node *parent)
1348{
1349 struct gic_chip_data *gic;
1350 int irq, ret;
1351
1352 if (WARN_ON(!node))
1353 return -ENODEV;
1354
1355 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1356 return -EINVAL;
1357
1358 gic = &gic_data[gic_cnt];
1359
1360 ret = gic_of_setup(gic, node);
1361 if (ret)
1362 return ret;
1363
1364
1365
1366
1367
1368 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1369 static_key_slow_dec(&supports_deactivate);
1370
1371 ret = __gic_init_bases(gic, -1, &node->fwnode);
1372 if (ret) {
1373 gic_teardown(gic);
1374 return ret;
1375 }
1376
1377 if (!gic_cnt) {
1378 gic_init_physaddr(node);
1379 gic_of_setup_kvm_info(node);
1380 }
1381
1382 if (parent) {
1383 irq = irq_of_parse_and_map(node, 0);
1384 gic_cascade_irq(gic_cnt, irq);
1385 }
1386
1387 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1388 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1389
1390 gic_cnt++;
1391 return 0;
1392}
1393IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1394IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1395IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1396IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1397IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1398IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1399IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1400IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1401IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1402#else
1403int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1404{
1405 return -ENOTSUPP;
1406}
1407#endif
1408
1409#ifdef CONFIG_ACPI
1410static struct
1411{
1412 phys_addr_t cpu_phys_base;
1413 u32 maint_irq;
1414 int maint_irq_mode;
1415 phys_addr_t vctrl_base;
1416 phys_addr_t vcpu_base;
1417} acpi_data __initdata;
1418
1419static int __init
1420gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1421 const unsigned long end)
1422{
1423 struct acpi_madt_generic_interrupt *processor;
1424 phys_addr_t gic_cpu_base;
1425 static int cpu_base_assigned;
1426
1427 processor = (struct acpi_madt_generic_interrupt *)header;
1428
1429 if (BAD_MADT_GICC_ENTRY(processor, end))
1430 return -EINVAL;
1431
1432
1433
1434
1435
1436 gic_cpu_base = processor->base_address;
1437 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1438 return -EINVAL;
1439
1440 acpi_data.cpu_phys_base = gic_cpu_base;
1441 acpi_data.maint_irq = processor->vgic_interrupt;
1442 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1443 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1444 acpi_data.vctrl_base = processor->gich_base_address;
1445 acpi_data.vcpu_base = processor->gicv_base_address;
1446
1447 cpu_base_assigned = 1;
1448 return 0;
1449}
1450
1451
1452static int __init acpi_dummy_func(struct acpi_subtable_header *header,
1453 const unsigned long end)
1454{
1455 return 0;
1456}
1457
1458static bool __init acpi_gic_redist_is_present(void)
1459{
1460 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1461 acpi_dummy_func, 0) > 0;
1462}
1463
1464static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1465 struct acpi_probe_entry *ape)
1466{
1467 struct acpi_madt_generic_distributor *dist;
1468 dist = (struct acpi_madt_generic_distributor *)header;
1469
1470 return (dist->version == ape->driver_data &&
1471 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1472 !acpi_gic_redist_is_present()));
1473}
1474
1475#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1476#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
1477#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1478#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1479
1480static void __init gic_acpi_setup_kvm_info(void)
1481{
1482 int irq;
1483 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1484 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1485
1486 gic_v2_kvm_info.type = GIC_V2;
1487
1488 if (!acpi_data.vctrl_base)
1489 return;
1490
1491 vctrl_res->flags = IORESOURCE_MEM;
1492 vctrl_res->start = acpi_data.vctrl_base;
1493 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1494
1495 if (!acpi_data.vcpu_base)
1496 return;
1497
1498 vcpu_res->flags = IORESOURCE_MEM;
1499 vcpu_res->start = acpi_data.vcpu_base;
1500 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1501
1502 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1503 acpi_data.maint_irq_mode,
1504 ACPI_ACTIVE_HIGH);
1505 if (irq <= 0)
1506 return;
1507
1508 gic_v2_kvm_info.maint_irq = irq;
1509
1510 gic_set_kvm_info(&gic_v2_kvm_info);
1511}
1512
1513static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
1514 const unsigned long end)
1515{
1516 struct acpi_madt_generic_distributor *dist;
1517 struct fwnode_handle *domain_handle;
1518 struct gic_chip_data *gic = &gic_data[0];
1519 int count, ret;
1520
1521
1522 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1523 gic_acpi_parse_madt_cpu, 0);
1524 if (count <= 0) {
1525 pr_err("No valid GICC entries exist\n");
1526 return -EINVAL;
1527 }
1528
1529 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1530 if (!gic->raw_cpu_base) {
1531 pr_err("Unable to map GICC registers\n");
1532 return -ENOMEM;
1533 }
1534
1535 dist = (struct acpi_madt_generic_distributor *)header;
1536 gic->raw_dist_base = ioremap(dist->base_address,
1537 ACPI_GICV2_DIST_MEM_SIZE);
1538 if (!gic->raw_dist_base) {
1539 pr_err("Unable to map GICD registers\n");
1540 gic_teardown(gic);
1541 return -ENOMEM;
1542 }
1543
1544
1545
1546
1547
1548
1549 if (!is_hyp_mode_available())
1550 static_key_slow_dec(&supports_deactivate);
1551
1552
1553
1554
1555 domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base);
1556 if (!domain_handle) {
1557 pr_err("Unable to allocate domain handle\n");
1558 gic_teardown(gic);
1559 return -ENOMEM;
1560 }
1561
1562 ret = __gic_init_bases(gic, -1, domain_handle);
1563 if (ret) {
1564 pr_err("Failed to initialise GIC\n");
1565 irq_domain_free_fwnode(domain_handle);
1566 gic_teardown(gic);
1567 return ret;
1568 }
1569
1570 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1571
1572 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1573 gicv2m_init(NULL, gic_data[0].domain);
1574
1575 gic_acpi_setup_kvm_info();
1576
1577 return 0;
1578}
1579IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1580 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1581 gic_v2_acpi_init);
1582IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1583 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1584 gic_v2_acpi_init);
1585#endif
1586