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27#include <linux/delay.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/string.h>
33#include <linux/slab.h>
34
35#include "dvb_frontend.h"
36#include "mt312_priv.h"
37#include "mt312.h"
38
39
40#define MAX_XFER_SIZE 64
41
42struct mt312_state {
43 struct i2c_adapter *i2c;
44
45 const struct mt312_config *config;
46 struct dvb_frontend frontend;
47
48 u8 id;
49 unsigned long xtal;
50 u8 freq_mult;
51};
52
53static int debug;
54#define dprintk(args...) \
55 do { \
56 if (debug) \
57 printk(KERN_DEBUG "mt312: " args); \
58 } while (0)
59
60#define MT312_PLL_CLK 10000000UL
61#define MT312_PLL_CLK_10_111 10111000UL
62
63static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
64 u8 *buf, const size_t count)
65{
66 int ret;
67 struct i2c_msg msg[2];
68 u8 regbuf[1] = { reg };
69
70 msg[0].addr = state->config->demod_address;
71 msg[0].flags = 0;
72 msg[0].buf = regbuf;
73 msg[0].len = 1;
74 msg[1].addr = state->config->demod_address;
75 msg[1].flags = I2C_M_RD;
76 msg[1].buf = buf;
77 msg[1].len = count;
78
79 ret = i2c_transfer(state->i2c, msg, 2);
80
81 if (ret != 2) {
82 printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret);
83 return -EREMOTEIO;
84 }
85
86 if (debug) {
87 int i;
88 dprintk("R(%d):", reg & 0x7f);
89 for (i = 0; i < count; i++)
90 printk(KERN_CONT " %02x", buf[i]);
91 printk("\n");
92 }
93
94 return 0;
95}
96
97static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
98 const u8 *src, const size_t count)
99{
100 int ret;
101 u8 buf[MAX_XFER_SIZE];
102 struct i2c_msg msg;
103
104 if (1 + count > sizeof(buf)) {
105 printk(KERN_WARNING
106 "mt312: write: len=%zu is too big!\n", count);
107 return -EINVAL;
108 }
109
110 if (debug) {
111 int i;
112 dprintk("W(%d):", reg & 0x7f);
113 for (i = 0; i < count; i++)
114 printk(KERN_CONT " %02x", src[i]);
115 printk("\n");
116 }
117
118 buf[0] = reg;
119 memcpy(&buf[1], src, count);
120
121 msg.addr = state->config->demod_address;
122 msg.flags = 0;
123 msg.buf = buf;
124 msg.len = count + 1;
125
126 ret = i2c_transfer(state->i2c, &msg, 1);
127
128 if (ret != 1) {
129 dprintk("%s: ret == %d\n", __func__, ret);
130 return -EREMOTEIO;
131 }
132
133 return 0;
134}
135
136static inline int mt312_readreg(struct mt312_state *state,
137 const enum mt312_reg_addr reg, u8 *val)
138{
139 return mt312_read(state, reg, val, 1);
140}
141
142static inline int mt312_writereg(struct mt312_state *state,
143 const enum mt312_reg_addr reg, const u8 val)
144{
145 return mt312_write(state, reg, &val, 1);
146}
147
148static inline u32 mt312_div(u32 a, u32 b)
149{
150 return (a + (b / 2)) / b;
151}
152
153static int mt312_reset(struct mt312_state *state, const u8 full)
154{
155 return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
156}
157
158static int mt312_get_inversion(struct mt312_state *state,
159 enum fe_spectral_inversion *i)
160{
161 int ret;
162 u8 vit_mode;
163
164 ret = mt312_readreg(state, VIT_MODE, &vit_mode);
165 if (ret < 0)
166 return ret;
167
168 if (vit_mode & 0x80)
169 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
170
171 return 0;
172}
173
174static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
175{
176 int ret;
177 u8 sym_rate_h;
178 u8 dec_ratio;
179 u16 sym_rat_op;
180 u16 monitor;
181 u8 buf[2];
182
183 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
184 if (ret < 0)
185 return ret;
186
187 if (sym_rate_h & 0x80) {
188
189 ret = mt312_writereg(state, MON_CTRL, 0x03);
190 if (ret < 0)
191 return ret;
192
193 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
194 if (ret < 0)
195 return ret;
196
197 monitor = (buf[0] << 8) | buf[1];
198
199 dprintk("sr(auto) = %u\n",
200 mt312_div(monitor * 15625, 4));
201 } else {
202 ret = mt312_writereg(state, MON_CTRL, 0x05);
203 if (ret < 0)
204 return ret;
205
206 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
207 if (ret < 0)
208 return ret;
209
210 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
211
212 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
213 if (ret < 0)
214 return ret;
215
216 sym_rat_op = (buf[0] << 8) | buf[1];
217
218 dprintk("sym_rat_op=%d dec_ratio=%d\n",
219 sym_rat_op, dec_ratio);
220 dprintk("*sr(manual) = %lu\n",
221 (((state->xtal * 8192) / (sym_rat_op + 8192)) *
222 2) - dec_ratio);
223 }
224
225 return 0;
226}
227
228static int mt312_get_code_rate(struct mt312_state *state, enum fe_code_rate *cr)
229{
230 const enum fe_code_rate fec_tab[8] =
231 { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
232 FEC_AUTO, FEC_AUTO };
233
234 int ret;
235 u8 fec_status;
236
237 ret = mt312_readreg(state, FEC_STATUS, &fec_status);
238 if (ret < 0)
239 return ret;
240
241 *cr = fec_tab[(fec_status >> 4) & 0x07];
242
243 return 0;
244}
245
246static int mt312_initfe(struct dvb_frontend *fe)
247{
248 struct mt312_state *state = fe->demodulator_priv;
249 int ret;
250 u8 buf[2];
251
252
253 ret = mt312_writereg(state, CONFIG,
254 (state->freq_mult == 6 ? 0x88 : 0x8c));
255 if (ret < 0)
256 return ret;
257
258
259 udelay(150);
260
261
262 ret = mt312_reset(state, 1);
263 if (ret < 0)
264 return ret;
265
266
267
268 {
269 u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
270 0x01, 0x00, 0x00, 0x00 };
271
272 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
273 if (ret < 0)
274 return ret;
275 }
276
277 switch (state->id) {
278 case ID_ZL10313:
279
280 ret = mt312_writereg(state, GPP_CTRL, 0x80);
281 if (ret < 0)
282 return ret;
283
284
285 buf[0] = 0x80;
286 buf[1] = 0xB0;
287 ret = mt312_write(state, HW_CTRL, buf, 2);
288 if (ret < 0)
289 return ret;
290
291
292 ret = mt312_writereg(state, HW_CTRL, 0x00);
293 if (ret < 0)
294 return ret;
295
296 ret = mt312_writereg(state, MPEG_CTRL, 0x00);
297 if (ret < 0)
298 return ret;
299
300 break;
301 }
302
303
304 buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000);
305
306
307 buf[1] = mt312_div(state->xtal, 22000 * 4);
308
309 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
310 if (ret < 0)
311 return ret;
312
313 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
314 if (ret < 0)
315 return ret;
316
317
318 switch (state->id) {
319 case ID_ZL10313:
320 buf[0] = 0x33;
321 break;
322 default:
323 buf[0] = 0x53;
324 break;
325 }
326
327 ret = mt312_writereg(state, OP_CTRL, buf[0]);
328 if (ret < 0)
329 return ret;
330
331
332 buf[0] = 0x8c;
333 buf[1] = 0x98;
334
335 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
336 if (ret < 0)
337 return ret;
338
339 ret = mt312_writereg(state, CS_SW_LIM, 0x69);
340 if (ret < 0)
341 return ret;
342
343 return 0;
344}
345
346static int mt312_send_master_cmd(struct dvb_frontend *fe,
347 struct dvb_diseqc_master_cmd *c)
348{
349 struct mt312_state *state = fe->demodulator_priv;
350 int ret;
351 u8 diseqc_mode;
352
353 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
354 return -EINVAL;
355
356 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
357 if (ret < 0)
358 return ret;
359
360 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
361 if (ret < 0)
362 return ret;
363
364 ret = mt312_writereg(state, DISEQC_MODE,
365 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
366 | 0x04);
367 if (ret < 0)
368 return ret;
369
370
371 msleep(100);
372
373
374 if (c->msg[0] & 0x02) {
375 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
376 if (ret < 0)
377 return ret;
378 }
379
380 return 0;
381}
382
383static int mt312_send_burst(struct dvb_frontend *fe,
384 const enum fe_sec_mini_cmd c)
385{
386 struct mt312_state *state = fe->demodulator_priv;
387 const u8 mini_tab[2] = { 0x02, 0x03 };
388
389 int ret;
390 u8 diseqc_mode;
391
392 if (c > SEC_MINI_B)
393 return -EINVAL;
394
395 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
396 if (ret < 0)
397 return ret;
398
399 ret = mt312_writereg(state, DISEQC_MODE,
400 (diseqc_mode & 0x40) | mini_tab[c]);
401 if (ret < 0)
402 return ret;
403
404 return 0;
405}
406
407static int mt312_set_tone(struct dvb_frontend *fe,
408 const enum fe_sec_tone_mode t)
409{
410 struct mt312_state *state = fe->demodulator_priv;
411 const u8 tone_tab[2] = { 0x01, 0x00 };
412
413 int ret;
414 u8 diseqc_mode;
415
416 if (t > SEC_TONE_OFF)
417 return -EINVAL;
418
419 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
420 if (ret < 0)
421 return ret;
422
423 ret = mt312_writereg(state, DISEQC_MODE,
424 (diseqc_mode & 0x40) | tone_tab[t]);
425 if (ret < 0)
426 return ret;
427
428 return 0;
429}
430
431static int mt312_set_voltage(struct dvb_frontend *fe,
432 const enum fe_sec_voltage v)
433{
434 struct mt312_state *state = fe->demodulator_priv;
435 const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
436 u8 val;
437
438 if (v > SEC_VOLTAGE_OFF)
439 return -EINVAL;
440
441 val = volt_tab[v];
442 if (state->config->voltage_inverted)
443 val ^= 0x40;
444
445 return mt312_writereg(state, DISEQC_MODE, val);
446}
447
448static int mt312_read_status(struct dvb_frontend *fe, enum fe_status *s)
449{
450 struct mt312_state *state = fe->demodulator_priv;
451 int ret;
452 u8 status[3];
453
454 *s = 0;
455
456 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
457 if (ret < 0)
458 return ret;
459
460 dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x,"
461 " FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]);
462
463 if (status[0] & 0xc0)
464 *s |= FE_HAS_SIGNAL;
465 if (status[0] & 0x04)
466 *s |= FE_HAS_CARRIER;
467 if (status[2] & 0x02)
468 *s |= FE_HAS_VITERBI;
469 if (status[2] & 0x04)
470 *s |= FE_HAS_SYNC;
471 if (status[0] & 0x01)
472 *s |= FE_HAS_LOCK;
473
474 return 0;
475}
476
477static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber)
478{
479 struct mt312_state *state = fe->demodulator_priv;
480 int ret;
481 u8 buf[3];
482
483 ret = mt312_read(state, RS_BERCNT_H, buf, 3);
484 if (ret < 0)
485 return ret;
486
487 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
488
489 return 0;
490}
491
492static int mt312_read_signal_strength(struct dvb_frontend *fe,
493 u16 *signal_strength)
494{
495 struct mt312_state *state = fe->demodulator_priv;
496 int ret;
497 u8 buf[3];
498 u16 agc;
499 s16 err_db;
500
501 ret = mt312_read(state, AGC_H, buf, sizeof(buf));
502 if (ret < 0)
503 return ret;
504
505 agc = (buf[0] << 6) | (buf[1] >> 2);
506 err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
507
508 *signal_strength = agc;
509
510 dprintk("agc=%08x err_db=%hd\n", agc, err_db);
511
512 return 0;
513}
514
515static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr)
516{
517 struct mt312_state *state = fe->demodulator_priv;
518 int ret;
519 u8 buf[2];
520
521 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
522 if (ret < 0)
523 return ret;
524
525 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
526
527 return 0;
528}
529
530static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
531{
532 struct mt312_state *state = fe->demodulator_priv;
533 int ret;
534 u8 buf[2];
535
536 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
537 if (ret < 0)
538 return ret;
539
540 *ubc = (buf[0] << 8) | buf[1];
541
542 return 0;
543}
544
545static int mt312_set_frontend(struct dvb_frontend *fe)
546{
547 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
548 struct mt312_state *state = fe->demodulator_priv;
549 int ret;
550 u8 buf[5], config_val;
551 u16 sr;
552
553 const u8 fec_tab[10] =
554 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
555 const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
556
557 dprintk("%s: Freq %d\n", __func__, p->frequency);
558
559 if ((p->frequency < fe->ops.info.frequency_min)
560 || (p->frequency > fe->ops.info.frequency_max))
561 return -EINVAL;
562
563 if (((int)p->inversion < INVERSION_OFF)
564 || (p->inversion > INVERSION_ON))
565 return -EINVAL;
566
567 if ((p->symbol_rate < fe->ops.info.symbol_rate_min)
568 || (p->symbol_rate > fe->ops.info.symbol_rate_max))
569 return -EINVAL;
570
571 if (((int)p->fec_inner < FEC_NONE)
572 || (p->fec_inner > FEC_AUTO))
573 return -EINVAL;
574
575 if ((p->fec_inner == FEC_4_5)
576 || (p->fec_inner == FEC_8_9))
577 return -EINVAL;
578
579 switch (state->id) {
580 case ID_VP310:
581
582
583
584
585 ret = mt312_readreg(state, CONFIG, &config_val);
586 if (ret < 0)
587 return ret;
588 if (p->symbol_rate >= 30000000) {
589
590 if (state->freq_mult == 6) {
591
592 state->freq_mult = 9;
593 ret = mt312_initfe(fe);
594 if (ret < 0)
595 return ret;
596 }
597 } else {
598 if (state->freq_mult == 9) {
599
600 state->freq_mult = 6;
601 ret = mt312_initfe(fe);
602 if (ret < 0)
603 return ret;
604 }
605 }
606 break;
607
608 case ID_MT312:
609 case ID_ZL10313:
610 break;
611
612 default:
613 return -EINVAL;
614 }
615
616 if (fe->ops.tuner_ops.set_params) {
617 fe->ops.tuner_ops.set_params(fe);
618 if (fe->ops.i2c_gate_ctrl)
619 fe->ops.i2c_gate_ctrl(fe, 0);
620 }
621
622
623 sr = mt312_div(p->symbol_rate * 4, 15625);
624
625
626 buf[0] = (sr >> 8) & 0x3f;
627 buf[1] = (sr >> 0) & 0xff;
628
629
630 buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner];
631
632
633 buf[3] = 0x40;
634
635 if (p->symbol_rate < 10000000)
636 buf[3] |= 0x04;
637
638
639 buf[4] = 0x01;
640
641 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
642 if (ret < 0)
643 return ret;
644
645 mt312_reset(state, 0);
646
647 return 0;
648}
649
650static int mt312_get_frontend(struct dvb_frontend *fe,
651 struct dtv_frontend_properties *p)
652{
653 struct mt312_state *state = fe->demodulator_priv;
654 int ret;
655
656 ret = mt312_get_inversion(state, &p->inversion);
657 if (ret < 0)
658 return ret;
659
660 ret = mt312_get_symbol_rate(state, &p->symbol_rate);
661 if (ret < 0)
662 return ret;
663
664 ret = mt312_get_code_rate(state, &p->fec_inner);
665 if (ret < 0)
666 return ret;
667
668 return 0;
669}
670
671static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
672{
673 struct mt312_state *state = fe->demodulator_priv;
674
675 u8 val = 0x00;
676 int ret;
677
678 switch (state->id) {
679 case ID_ZL10313:
680 ret = mt312_readreg(state, GPP_CTRL, &val);
681 if (ret < 0)
682 goto error;
683
684
685 val &= 0x80;
686 break;
687 }
688
689 if (enable)
690 val |= 0x40;
691 else
692 val &= ~0x40;
693
694 ret = mt312_writereg(state, GPP_CTRL, val);
695
696error:
697 return ret;
698}
699
700static int mt312_sleep(struct dvb_frontend *fe)
701{
702 struct mt312_state *state = fe->demodulator_priv;
703 int ret;
704 u8 config;
705
706
707 ret = mt312_reset(state, 1);
708 if (ret < 0)
709 return ret;
710
711 if (state->id == ID_ZL10313) {
712
713 ret = mt312_writereg(state, GPP_CTRL, 0x00);
714 if (ret < 0)
715 return ret;
716
717
718 ret = mt312_writereg(state, HW_CTRL, 0x0d);
719 if (ret < 0)
720 return ret;
721 }
722
723 ret = mt312_readreg(state, CONFIG, &config);
724 if (ret < 0)
725 return ret;
726
727
728 ret = mt312_writereg(state, CONFIG, config & 0x7f);
729 if (ret < 0)
730 return ret;
731
732 return 0;
733}
734
735static int mt312_get_tune_settings(struct dvb_frontend *fe,
736 struct dvb_frontend_tune_settings *fesettings)
737{
738 fesettings->min_delay_ms = 50;
739 fesettings->step_size = 0;
740 fesettings->max_drift = 0;
741 return 0;
742}
743
744static void mt312_release(struct dvb_frontend *fe)
745{
746 struct mt312_state *state = fe->demodulator_priv;
747 kfree(state);
748}
749
750#define MT312_SYS_CLK 90000000UL
751static struct dvb_frontend_ops mt312_ops = {
752 .delsys = { SYS_DVBS },
753 .info = {
754 .name = "Zarlink ???? DVB-S",
755 .frequency_min = 950000,
756 .frequency_max = 2150000,
757
758 .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
759 .symbol_rate_min = MT312_SYS_CLK / 128,
760 .symbol_rate_max = MT312_SYS_CLK / 2,
761 .caps =
762 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
763 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
764 FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
765 FE_CAN_RECOVER
766 },
767
768 .release = mt312_release,
769
770 .init = mt312_initfe,
771 .sleep = mt312_sleep,
772 .i2c_gate_ctrl = mt312_i2c_gate_ctrl,
773
774 .set_frontend = mt312_set_frontend,
775 .get_frontend = mt312_get_frontend,
776 .get_tune_settings = mt312_get_tune_settings,
777
778 .read_status = mt312_read_status,
779 .read_ber = mt312_read_ber,
780 .read_signal_strength = mt312_read_signal_strength,
781 .read_snr = mt312_read_snr,
782 .read_ucblocks = mt312_read_ucblocks,
783
784 .diseqc_send_master_cmd = mt312_send_master_cmd,
785 .diseqc_send_burst = mt312_send_burst,
786 .set_tone = mt312_set_tone,
787 .set_voltage = mt312_set_voltage,
788};
789
790struct dvb_frontend *mt312_attach(const struct mt312_config *config,
791 struct i2c_adapter *i2c)
792{
793 struct mt312_state *state = NULL;
794
795
796 state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL);
797 if (state == NULL)
798 goto error;
799
800
801 state->config = config;
802 state->i2c = i2c;
803
804
805 if (mt312_readreg(state, ID, &state->id) < 0)
806 goto error;
807
808
809 memcpy(&state->frontend.ops, &mt312_ops,
810 sizeof(struct dvb_frontend_ops));
811 state->frontend.demodulator_priv = state;
812
813 switch (state->id) {
814 case ID_VP310:
815 strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S");
816 state->xtal = MT312_PLL_CLK;
817 state->freq_mult = 9;
818 break;
819 case ID_MT312:
820 strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S");
821 state->xtal = MT312_PLL_CLK;
822 state->freq_mult = 6;
823 break;
824 case ID_ZL10313:
825 strcpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S");
826 state->xtal = MT312_PLL_CLK_10_111;
827 state->freq_mult = 9;
828 break;
829 default:
830 printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313"
831 " are supported chips.\n");
832 goto error;
833 }
834
835 return &state->frontend;
836
837error:
838 kfree(state);
839 return NULL;
840}
841EXPORT_SYMBOL(mt312_attach);
842
843module_param(debug, int, 0644);
844MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
845
846MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver");
847MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
848MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");
849MODULE_LICENSE("GPL");
850
851
