LXR linux/drivers/media/usb/dvb-usb-v2/rtl28xxu.h

   1/*
   2 * Realtek RTL28xxU DVB USB driver
   3 *
   4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
   5 * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
   6 *
   7 *    This program is free software; you can redistribute it and/or modify
   8 *    it under the terms of the GNU General Public License as published by
   9 *    the Free Software Foundation; either version 2 of the License, or
  10 *    (at your option) any later version.
  11 *
  12 *    This program is distributed in the hope that it will be useful,
  13 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 *    GNU General Public License for more details.
  16 *
  17 *    You should have received a copy of the GNU General Public License along
  18 *    with this program; if not, write to the Free Software Foundation, Inc.,
  19 *    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  20 */
  21
  22#ifndef RTL28XXU_H
  23#define RTL28XXU_H
  24
  25#include <linux/platform_device.h>
  26
  27#include "dvb_usb.h"
  28
  29#include "rtl2830.h"
  30#include "rtl2832.h"
  31#include "rtl2832_sdr.h"
  32#include "mn88472.h"
  33#include "mn88473.h"
  34
  35#include "qt1010.h"
  36#include "mt2060.h"
  37#include "mxl5005s.h"
  38#include "fc0012.h"
  39#include "fc0013.h"
  40#include "e4000.h"
  41#include "fc2580.h"
  42#include "tua9001.h"
  43#include "r820t.h"
  44#include "si2168.h"
  45#include "si2157.h"
  46
  47/*
  48 * USB commands
  49 * (usb_control_msg() index parameter)
  50 */
  51
  52#define DEMOD            0x0000
  53#define USB              0x0100
  54#define SYS              0x0200
  55#define I2C              0x0300
  56#define I2C_DA           0x0600
  57
  58#define CMD_WR_FLAG      0x0010
  59#define CMD_DEMOD_RD     0x0000
  60#define CMD_DEMOD_WR     0x0010
  61#define CMD_USB_RD       0x0100
  62#define CMD_USB_WR       0x0110
  63#define CMD_SYS_RD       0x0200
  64#define CMD_IR_RD        0x0201
  65#define CMD_IR_WR        0x0211
  66#define CMD_SYS_WR       0x0210
  67#define CMD_I2C_RD       0x0300
  68#define CMD_I2C_WR       0x0310
  69#define CMD_I2C_DA_RD    0x0600
  70#define CMD_I2C_DA_WR    0x0610
  71
  72
  73struct rtl28xxu_dev {
  74        u8 buf[128];
  75        u8 chip_id;
  76        u8 tuner;
  77        char *tuner_name;
  78        u8 page; /* integrated demod active register page */
  79        struct i2c_adapter *demod_i2c_adapter;
  80        bool rc_active;
  81        bool new_i2c_write;
  82        struct i2c_client *i2c_client_demod;
  83        struct i2c_client *i2c_client_tuner;
  84        struct i2c_client *i2c_client_slave_demod;
  85        struct platform_device *platform_device_sdr;
  86        #define SLAVE_DEMOD_NONE           0
  87        #define SLAVE_DEMOD_MN88472        1
  88        #define SLAVE_DEMOD_MN88473        2
  89        #define SLAVE_DEMOD_SI2168         3
  90        unsigned int slave_demod:2;
  91        union {
  92                struct rtl2830_platform_data rtl2830_platform_data;
  93                struct rtl2832_platform_data rtl2832_platform_data;
  94        };
  95};
  96
  97enum rtl28xxu_chip_id {
  98        CHIP_ID_NONE,
  99        CHIP_ID_RTL2831U,
 100        CHIP_ID_RTL2832U,
 101};
 102
 103/* XXX: Hack. This must be keep sync with rtl2832 demod driver. */
 104enum rtl28xxu_tuner {
 105        TUNER_NONE,
 106
 107        TUNER_RTL2830_QT1010          = 0x10,
 108        TUNER_RTL2830_MT2060,
 109        TUNER_RTL2830_MXL5005S,
 110
 111        TUNER_RTL2832_MT2266          = 0x20,
 112        TUNER_RTL2832_FC2580,
 113        TUNER_RTL2832_MT2063,
 114        TUNER_RTL2832_MAX3543,
 115        TUNER_RTL2832_TUA9001,
 116        TUNER_RTL2832_MXL5007T,
 117        TUNER_RTL2832_FC0012,
 118        TUNER_RTL2832_E4000,
 119        TUNER_RTL2832_TDA18272,
 120        TUNER_RTL2832_FC0013,
 121        TUNER_RTL2832_R820T,
 122        TUNER_RTL2832_R828D,
 123        TUNER_RTL2832_SI2157,
 124};
 125
 126struct rtl28xxu_req {
 127        u16 value;
 128        u16 index;
 129        u16 size;
 130        u8 *data;
 131};
 132
 133struct rtl28xxu_reg_val {
 134        u16 reg;
 135        u8 val;
 136};
 137
 138struct rtl28xxu_reg_val_mask {
 139        u16 reg;
 140        u8 val;
 141        u8 mask;
 142};
 143
 144/*
 145 * memory map
 146 *
 147 * 0x0000 DEMOD : demodulator
 148 * 0x2000 USB   : SIE, USB endpoint, debug, DMA
 149 * 0x3000 SYS   : system
 150 * 0xfc00 RC    : remote controller (not RTL2831U)
 151 */
 152
 153/*
 154 * USB registers
 155 */
 156/* SIE Control Registers */
 157#define USB_SYSCTL         0x2000 /* USB system control */
 158#define USB_SYSCTL_0       0x2000 /* USB system control */
 159#define USB_SYSCTL_1       0x2001 /* USB system control */
 160#define USB_SYSCTL_2       0x2002 /* USB system control */
 161#define USB_SYSCTL_3       0x2003 /* USB system control */
 162#define USB_IRQSTAT        0x2008 /* SIE interrupt status */
 163#define USB_IRQEN          0x200C /* SIE interrupt enable */
 164#define USB_CTRL           0x2010 /* USB control */
 165#define USB_STAT           0x2014 /* USB status */
 166#define USB_DEVADDR        0x2018 /* USB device address */
 167#define USB_TEST           0x201C /* USB test mode */
 168#define USB_FRAME_NUMBER   0x2020 /* frame number */
 169#define USB_FIFO_ADDR      0x2028 /* address of SIE FIFO RAM */
 170#define USB_FIFO_CMD       0x202A /* SIE FIFO RAM access command */
 171#define USB_FIFO_DATA      0x2030 /* SIE FIFO RAM data */
 172/* Endpoint Registers */
 173#define EP0_SETUPA         0x20F8 /* EP 0 setup packet lower byte */
 174#define EP0_SETUPB         0x20FC /* EP 0 setup packet higher byte */
 175#define USB_EP0_CFG        0x2104 /* EP 0 configure */
 176#define USB_EP0_CTL        0x2108 /* EP 0 control */
 177#define USB_EP0_STAT       0x210C /* EP 0 status */
 178#define USB_EP0_IRQSTAT    0x2110 /* EP 0 interrupt status */
 179#define USB_EP0_IRQEN      0x2114 /* EP 0 interrupt enable */
 180#define USB_EP0_MAXPKT     0x2118 /* EP 0 max packet size */
 181#define USB_EP0_BC         0x2120 /* EP 0 FIFO byte counter */
 182#define USB_EPA_CFG        0x2144 /* EP A configure */
 183#define USB_EPA_CFG_0      0x2144 /* EP A configure */
 184#define USB_EPA_CFG_1      0x2145 /* EP A configure */
 185#define USB_EPA_CFG_2      0x2146 /* EP A configure */
 186#define USB_EPA_CFG_3      0x2147 /* EP A configure */
 187#define USB_EPA_CTL        0x2148 /* EP A control */
 188#define USB_EPA_CTL_0      0x2148 /* EP A control */
 189#define USB_EPA_CTL_1      0x2149 /* EP A control */
 190#define USB_EPA_CTL_2      0x214A /* EP A control */
 191#define USB_EPA_CTL_3      0x214B /* EP A control */
 192#define USB_EPA_STAT       0x214C /* EP A status */
 193#define USB_EPA_IRQSTAT    0x2150 /* EP A interrupt status */
 194#define USB_EPA_IRQEN      0x2154 /* EP A interrupt enable */
 195#define USB_EPA_MAXPKT     0x2158 /* EP A max packet size */
 196#define USB_EPA_MAXPKT_0   0x2158 /* EP A max packet size */
 197#define USB_EPA_MAXPKT_1   0x2159 /* EP A max packet size */
 198#define USB_EPA_MAXPKT_2   0x215A /* EP A max packet size */
 199#define USB_EPA_MAXPKT_3   0x215B /* EP A max packet size */
 200#define USB_EPA_FIFO_CFG   0x2160 /* EP A FIFO configure */
 201#define USB_EPA_FIFO_CFG_0 0x2160 /* EP A FIFO configure */
 202#define USB_EPA_FIFO_CFG_1 0x2161 /* EP A FIFO configure */
 203#define USB_EPA_FIFO_CFG_2 0x2162 /* EP A FIFO configure */
 204#define USB_EPA_FIFO_CFG_3 0x2163 /* EP A FIFO configure */
 205/* Debug Registers */
 206#define USB_PHYTSTDIS      0x2F04 /* PHY test disable */
 207#define USB_TOUT_VAL       0x2F08 /* USB time-out time */
 208#define USB_VDRCTRL        0x2F10 /* UTMI vendor signal control */
 209#define USB_VSTAIN         0x2F14 /* UTMI vendor signal status in */
 210#define USB_VLOADM         0x2F18 /* UTMI load vendor signal status in */
 211#define USB_VSTAOUT        0x2F1C /* UTMI vendor signal status out */
 212#define USB_UTMI_TST       0x2F80 /* UTMI test */
 213#define USB_UTMI_STATUS    0x2F84 /* UTMI status */
 214#define USB_TSTCTL         0x2F88 /* test control */
 215#define USB_TSTCTL2        0x2F8C /* test control 2 */
 216#define USB_PID_FORCE      0x2F90 /* force PID */
 217#define USB_PKTERR_CNT     0x2F94 /* packet error counter */
 218#define USB_RXERR_CNT      0x2F98 /* RX error counter */
 219#define USB_MEM_BIST       0x2F9C /* MEM BIST test */
 220#define USB_SLBBIST        0x2FA0 /* self-loop-back BIST */
 221#define USB_CNTTEST        0x2FA4 /* counter test */
 222#define USB_PHYTST         0x2FC0 /* USB PHY test */
 223#define USB_DBGIDX         0x2FF0 /* select individual block debug signal */
 224#define USB_DBGMUX         0x2FF4 /* debug signal module mux */
 225
 226/*
 227 * SYS registers
 228 */
 229/* demod control registers */
 230#define SYS_SYS0           0x3000 /* include DEMOD_CTL, GPO, GPI, GPOE */
 231#define SYS_DEMOD_CTL      0x3000 /* control register for DVB-T demodulator */
 232/* GPIO registers */
 233#define SYS_GPIO_OUT_VAL   0x3001 /* output value of GPIO */
 234#define SYS_GPIO_IN_VAL    0x3002 /* input value of GPIO */
 235#define SYS_GPIO_OUT_EN    0x3003 /* output enable of GPIO */
 236#define SYS_SYS1           0x3004 /* include GPD, SYSINTE, SYSINTS, GP_CFG0 */
 237#define SYS_GPIO_DIR       0x3004 /* direction control for GPIO */
 238#define SYS_SYSINTE        0x3005 /* system interrupt enable */
 239#define SYS_SYSINTS        0x3006 /* system interrupt status */
 240#define SYS_GPIO_CFG0      0x3007 /* PAD configuration for GPIO0-GPIO3 */
 241#define SYS_SYS2           0x3008 /* include GP_CFG1 and 3 reserved bytes */
 242#define SYS_GPIO_CFG1      0x3008 /* PAD configuration for GPIO4 */
 243#define SYS_DEMOD_CTL1     0x300B
 244
 245/* IrDA registers */
 246#define SYS_IRRC_PSR       0x3020 /* IR protocol selection */
 247#define SYS_IRRC_PER       0x3024 /* IR protocol extension */
 248#define SYS_IRRC_SF        0x3028 /* IR sampling frequency */
 249#define SYS_IRRC_DPIR      0x302C /* IR data package interval */
 250#define SYS_IRRC_CR        0x3030 /* IR control */
 251#define SYS_IRRC_RP        0x3034 /* IR read port */
 252#define SYS_IRRC_SR        0x3038 /* IR status */
 253/* I2C master registers */
 254#define SYS_I2CCR          0x3040 /* I2C clock */
 255#define SYS_I2CMCR         0x3044 /* I2C master control */
 256#define SYS_I2CMSTR        0x3048 /* I2C master SCL timing */
 257#define SYS_I2CMSR         0x304C /* I2C master status */
 258#define SYS_I2CMFR         0x3050 /* I2C master FIFO */
 259
 260/*
 261 * IR registers
 262 */
 263#define IR_RX_BUF          0xFC00
 264#define IR_RX_IE           0xFD00
 265#define IR_RX_IF           0xFD01
 266#define IR_RX_CTRL         0xFD02
 267#define IR_RX_CFG          0xFD03
 268#define IR_MAX_DURATION0   0xFD04
 269#define IR_MAX_DURATION1   0xFD05
 270#define IR_IDLE_LEN0       0xFD06
 271#define IR_IDLE_LEN1       0xFD07
 272#define IR_GLITCH_LEN      0xFD08
 273#define IR_RX_BUF_CTRL     0xFD09
 274#define IR_RX_BUF_DATA     0xFD0A
 275#define IR_RX_BC           0xFD0B
 276#define IR_RX_CLK          0xFD0C
 277#define IR_RX_C_COUNT_L    0xFD0D
 278#define IR_RX_C_COUNT_H    0xFD0E
 279#define IR_SUSPEND_CTRL    0xFD10
 280#define IR_ERR_TOL_CTRL    0xFD11
 281#define IR_UNIT_LEN        0xFD12
 282#define IR_ERR_TOL_LEN     0xFD13
 283#define IR_MAX_H_TOL_LEN   0xFD14
 284#define IR_MAX_L_TOL_LEN   0xFD15
 285#define IR_MASK_CTRL       0xFD16
 286#define IR_MASK_DATA       0xFD17
 287#define IR_RES_MASK_ADDR   0xFD18
 288#define IR_RES_MASK_T_LEN  0xFD19
 289
 290#endif
 291